firmware: ti_sci: Add support for processor control services

TI-SCI message protocol provides support for controlling of various physical cores available in SoC. In order to control which host is capable of controlling a physical processor core, there is a processor access control list that needs to be populated as part of the board configuration data. Introduce support for the set of TI-SCI message protocol apis that provide us with this capability of controlling physical cores. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

firmware: ti_sci: Add support for processor control services
TI-SCI message protocol provides support for controlling of various physical cores available in SoC. In order to control which host is capable of controlling a physical processor core, there is a processor access control list that needs to be populated as part of the board configuration data. Introduce support for the set of TI-SCI message protocol apis that provide us with this capability of controlling physical cores. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Lokesh Vutla · Tom Rini
1 parent f369b0f26c
Showing 3 changed files with 589 additions and 0 deletions Side-by-side Diff
drivers/firmware/ti_sci.c
drivers/firmware/ti_sci.h
include/linux/soc/ti/ti_sci_protocol.h
@@ -1441,6 +1441,368 @@
 	return ret;
 }
  
+/**
+ * ti_sci_cmd_proc_request() - Command to request a physical processor control
+ * @handle:	Pointer to TI SCI handle
+ * @proc_id:	Processor ID this request is for
+ *
+ * Return: 0 if all went well, else returns appropriate error value.
+ */
+static int ti_sci_cmd_proc_request(const struct ti_sci_handle *handle,
+				   u8 proc_id)
+{
+	struct ti_sci_msg_req_proc_request req;
+	struct ti_sci_msg_hdr *resp;
+	struct ti_sci_info *info;
+	struct ti_sci_xfer *xfer;
+	int ret = 0;
+
+	if (IS_ERR(handle))
+		return PTR_ERR(handle);
+	if (!handle)
+		return -EINVAL;
+
+	info = handle_to_ti_sci_info(handle);
+
+	xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_PROC_REQUEST,
+				     TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
+				     (u32 *)&req, sizeof(req), sizeof(*resp));
+	if (IS_ERR(xfer)) {
+		ret = PTR_ERR(xfer);
+		dev_err(info->dev, "Message alloc failed(%d)\n", ret);
+		return ret;
+	}
+	req.processor_id = proc_id;
+
+	ret = ti_sci_do_xfer(info, xfer);
+	if (ret) {
+		dev_err(info->dev, "Mbox send fail %d\n", ret);
+		return ret;
+	}
+
+	resp = (struct ti_sci_msg_hdr *)xfer->tx_message.buf;
+
+	if (!ti_sci_is_response_ack(resp))
+		ret = -ENODEV;
+
+	return ret;
+}
+
+/**
+ * ti_sci_cmd_proc_release() - Command to release a physical processor control
+ * @handle:	Pointer to TI SCI handle
+ * @proc_id:	Processor ID this request is for
+ *
+ * Return: 0 if all went well, else returns appropriate error value.
+ */
+static int ti_sci_cmd_proc_release(const struct ti_sci_handle *handle,
+				   u8 proc_id)
+{
+	struct ti_sci_msg_req_proc_release req;
+	struct ti_sci_msg_hdr *resp;
+	struct ti_sci_info *info;
+	struct ti_sci_xfer *xfer;
+	int ret = 0;
+
+	if (IS_ERR(handle))
+		return PTR_ERR(handle);
+	if (!handle)
+		return -EINVAL;
+
+	info = handle_to_ti_sci_info(handle);
+
+	xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_PROC_RELEASE,
+				     TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
+				     (u32 *)&req, sizeof(req), sizeof(*resp));
+	if (IS_ERR(xfer)) {
+		ret = PTR_ERR(xfer);
+		dev_err(info->dev, "Message alloc failed(%d)\n", ret);
+		return ret;
+	}
+	req.processor_id = proc_id;
+
+	ret = ti_sci_do_xfer(info, xfer);
+	if (ret) {
+		dev_err(info->dev, "Mbox send fail %d\n", ret);
+		return ret;
+	}
+
+	resp = (struct ti_sci_msg_hdr *)xfer->tx_message.buf;
+
+	if (!ti_sci_is_response_ack(resp))
+		ret = -ENODEV;
+
+	return ret;
+}
+
+/**
+ * ti_sci_cmd_proc_handover() - Command to handover a physical processor
+ *				control to a host in the processor's access
+ *				control list.
+ * @handle:	Pointer to TI SCI handle
+ * @proc_id:	Processor ID this request is for
+ * @host_id:	Host ID to get the control of the processor
+ *
+ * Return: 0 if all went well, else returns appropriate error value.
+ */
+static int ti_sci_cmd_proc_handover(const struct ti_sci_handle *handle,
+				    u8 proc_id, u8 host_id)
+{
+	struct ti_sci_msg_req_proc_handover req;
+	struct ti_sci_msg_hdr *resp;
+	struct ti_sci_info *info;
+	struct ti_sci_xfer *xfer;
+	int ret = 0;
+
+	if (IS_ERR(handle))
+		return PTR_ERR(handle);
+	if (!handle)
+		return -EINVAL;
+
+	info = handle_to_ti_sci_info(handle);
+
+	xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_PROC_HANDOVER,
+				     TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
+				     (u32 *)&req, sizeof(req), sizeof(*resp));
+	if (IS_ERR(xfer)) {
+		ret = PTR_ERR(xfer);
+		dev_err(info->dev, "Message alloc failed(%d)\n", ret);
+		return ret;
+	}
+	req.processor_id = proc_id;
+	req.host_id = host_id;
+
+	ret = ti_sci_do_xfer(info, xfer);
+	if (ret) {
+		dev_err(info->dev, "Mbox send fail %d\n", ret);
+		return ret;
+	}
+
+	resp = (struct ti_sci_msg_hdr *)xfer->tx_message.buf;
+
+	if (!ti_sci_is_response_ack(resp))
+		ret = -ENODEV;
+
+	return ret;
+}
+
+/**
+ * ti_sci_cmd_set_proc_boot_cfg() - Command to set the processor boot
+ *				    configuration flags
+ * @handle:		Pointer to TI SCI handle
+ * @proc_id:		Processor ID this request is for
+ * @config_flags_set:	Configuration flags to be set
+ * @config_flags_clear:	Configuration flags to be cleared.
+ *
+ * Return: 0 if all went well, else returns appropriate error value.
+ */
+static int ti_sci_cmd_set_proc_boot_cfg(const struct ti_sci_handle *handle,
+					u8 proc_id, u64 bootvector,
+					u32 config_flags_set,
+					u32 config_flags_clear)
+{
+	struct ti_sci_msg_req_set_proc_boot_config req;
+	struct ti_sci_msg_hdr *resp;
+	struct ti_sci_info *info;
+	struct ti_sci_xfer *xfer;
+	int ret = 0;
+
+	if (IS_ERR(handle))
+		return PTR_ERR(handle);
+	if (!handle)
+		return -EINVAL;
+
+	info = handle_to_ti_sci_info(handle);
+
+	xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_SET_PROC_BOOT_CONFIG,
+				     TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
+				     (u32 *)&req, sizeof(req), sizeof(*resp));
+	if (IS_ERR(xfer)) {
+		ret = PTR_ERR(xfer);
+		dev_err(info->dev, "Message alloc failed(%d)\n", ret);
+		return ret;
+	}
+	req.processor_id = proc_id;
+	req.bootvector_low = bootvector & TISCI_ADDR_LOW_MASK;
+	req.bootvector_high = (bootvector & TISCI_ADDR_HIGH_MASK) >>
+				TISCI_ADDR_HIGH_SHIFT;
+	req.config_flags_set = config_flags_set;
+	req.config_flags_clear = config_flags_clear;
+
+	ret = ti_sci_do_xfer(info, xfer);
+	if (ret) {
+		dev_err(info->dev, "Mbox send fail %d\n", ret);
+		return ret;
+	}
+
+	resp = (struct ti_sci_msg_hdr *)xfer->tx_message.buf;
+
+	if (!ti_sci_is_response_ack(resp))
+		ret = -ENODEV;
+
+	return ret;
+}
+
+/**
+ * ti_sci_cmd_set_proc_boot_ctrl() - Command to set the processor boot
+ *				     control flags
+ * @handle:			Pointer to TI SCI handle
+ * @proc_id:			Processor ID this request is for
+ * @control_flags_set:		Control flags to be set
+ * @control_flags_clear:	Control flags to be cleared
+ *
+ * Return: 0 if all went well, else returns appropriate error value.
+ */
+static int ti_sci_cmd_set_proc_boot_ctrl(const struct ti_sci_handle *handle,
+					 u8 proc_id, u32 control_flags_set,
+					 u32 control_flags_clear)
+{
+	struct ti_sci_msg_req_set_proc_boot_ctrl req;
+	struct ti_sci_msg_hdr *resp;
+	struct ti_sci_info *info;
+	struct ti_sci_xfer *xfer;
+	int ret = 0;
+
+	if (IS_ERR(handle))
+		return PTR_ERR(handle);
+	if (!handle)
+		return -EINVAL;
+
+	info = handle_to_ti_sci_info(handle);
+
+	xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_SET_PROC_BOOT_CTRL,
+				     TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
+				     (u32 *)&req, sizeof(req), sizeof(*resp));
+	if (IS_ERR(xfer)) {
+		ret = PTR_ERR(xfer);
+		dev_err(info->dev, "Message alloc failed(%d)\n", ret);
+		return ret;
+	}
+	req.processor_id = proc_id;
+	req.control_flags_set = control_flags_set;
+	req.control_flags_clear = control_flags_clear;
+
+	ret = ti_sci_do_xfer(info, xfer);
+	if (ret) {
+		dev_err(info->dev, "Mbox send fail %d\n", ret);
+		return ret;
+	}
+
+	resp = (struct ti_sci_msg_hdr *)xfer->tx_message.buf;
+
+	if (!ti_sci_is_response_ack(resp))
+		ret = -ENODEV;
+
+	return ret;
+}
+
+/**
+ * ti_sci_cmd_proc_auth_boot_image() - Command to authenticate and load the
+ *			image and then set the processor configuration flags.
+ * @handle:	Pointer to TI SCI handle
+ * @proc_id:	Processor ID this request is for
+ * @cert_addr:	Memory address at which payload image certificate is located.
+ *
+ * Return: 0 if all went well, else returns appropriate error value.
+ */
+static int ti_sci_cmd_proc_auth_boot_image(const struct ti_sci_handle *handle,
+					   u8 proc_id, u64 cert_addr)
+{
+	struct ti_sci_msg_req_proc_auth_boot_image req;
+	struct ti_sci_msg_hdr *resp;
+	struct ti_sci_info *info;
+	struct ti_sci_xfer *xfer;
+	int ret = 0;
+
+	if (IS_ERR(handle))
+		return PTR_ERR(handle);
+	if (!handle)
+		return -EINVAL;
+
+	info = handle_to_ti_sci_info(handle);
+
+	xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_PROC_AUTH_BOOT_IMIAGE,
+				     TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
+				     (u32 *)&req, sizeof(req), sizeof(*resp));
+	if (IS_ERR(xfer)) {
+		ret = PTR_ERR(xfer);
+		dev_err(info->dev, "Message alloc failed(%d)\n", ret);
+		return ret;
+	}
+	req.processor_id = proc_id;
+	req.cert_addr_low = cert_addr & TISCI_ADDR_LOW_MASK;
+	req.cert_addr_high = (cert_addr & TISCI_ADDR_HIGH_MASK) >>
+				TISCI_ADDR_HIGH_SHIFT;
+
+	ret = ti_sci_do_xfer(info, xfer);
+	if (ret) {
+		dev_err(info->dev, "Mbox send fail %d\n", ret);
+		return ret;
+	}
+
+	resp = (struct ti_sci_msg_hdr *)xfer->tx_message.buf;
+
+	if (!ti_sci_is_response_ack(resp))
+		ret = -ENODEV;
+
+	return ret;
+}
+
+/**
+ * ti_sci_cmd_get_proc_boot_status() - Command to get the processor boot status
+ * @handle:	Pointer to TI SCI handle
+ * @proc_id:	Processor ID this request is for
+ *
+ * Return: 0 if all went well, else returns appropriate error value.
+ */
+static int ti_sci_cmd_get_proc_boot_status(const struct ti_sci_handle *handle,
+					   u8 proc_id, u64 *bv, u32 *cfg_flags,
+					   u32 *ctrl_flags, u32 *sts_flags)
+{
+	struct ti_sci_msg_resp_get_proc_boot_status *resp;
+	struct ti_sci_msg_req_get_proc_boot_status req;
+	struct ti_sci_info *info;
+	struct ti_sci_xfer *xfer;
+	int ret = 0;
+
+	if (IS_ERR(handle))
+		return PTR_ERR(handle);
+	if (!handle)
+		return -EINVAL;
+
+	info = handle_to_ti_sci_info(handle);
+
+	xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_GET_PROC_BOOT_STATUS,
+				     TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
+				     (u32 *)&req, sizeof(req), sizeof(*resp));
+	if (IS_ERR(xfer)) {
+		ret = PTR_ERR(xfer);
+		dev_err(info->dev, "Message alloc failed(%d)\n", ret);
+		return ret;
+	}
+	req.processor_id = proc_id;
+
+	ret = ti_sci_do_xfer(info, xfer);
+	if (ret) {
+		dev_err(info->dev, "Mbox send fail %d\n", ret);
+		return ret;
+	}
+
+	resp = (struct ti_sci_msg_resp_get_proc_boot_status *)
+							xfer->tx_message.buf;
+
+	if (!ti_sci_is_response_ack(resp))
+		return -ENODEV;
+	*bv = (resp->bootvector_low & TISCI_ADDR_LOW_MASK) |
+			(((u64)resp->bootvector_high  <<
+			  TISCI_ADDR_HIGH_SHIFT) & TISCI_ADDR_HIGH_MASK);
+	*cfg_flags = resp->config_flags;
+	*ctrl_flags = resp->control_flags;
+	*sts_flags = resp->status_flags;
+
+	return ret;
+}
+
 /*
  * ti_sci_setup_ops() - Setup the operations structures
  * @info:	pointer to TISCI pointer
@@ -1452,6 +1814,7 @@
 	struct ti_sci_dev_ops *dops = &ops->dev_ops;
 	struct ti_sci_clk_ops *cops = &ops->clk_ops;
 	struct ti_sci_core_ops *core_ops = &ops->core_ops;
+	struct ti_sci_proc_ops *pops = &ops->proc_ops;
  
 	bops->board_config = ti_sci_cmd_set_board_config;
 	bops->board_config_rm = ti_sci_cmd_set_board_config_rm;
@@ -1486,6 +1849,14 @@
 	cops->get_freq = ti_sci_cmd_clk_get_freq;
  
 	core_ops->reboot_device = ti_sci_cmd_core_reboot;
+
+	pops->proc_request = ti_sci_cmd_proc_request;
+	pops->proc_release = ti_sci_cmd_proc_release;
+	pops->proc_handover = ti_sci_cmd_proc_handover;
+	pops->set_proc_boot_cfg = ti_sci_cmd_set_proc_boot_cfg;
+	pops->set_proc_boot_ctrl = ti_sci_cmd_set_proc_boot_ctrl;
+	pops->proc_auth_boot_image = ti_sci_cmd_proc_auth_boot_image;
+	pops->get_proc_boot_status = ti_sci_cmd_get_proc_boot_status;
 }
  
 /**
@@ -41,6 +41,15 @@
 #define TI_SCI_MSG_QUERY_CLOCK_FREQ	0x010d
 #define TI_SCI_MSG_GET_CLOCK_FREQ	0x010e
  
+/* Processor Control Messages */
+#define TISCI_MSG_PROC_REQUEST		0xc000
+#define TISCI_MSG_PROC_RELEASE		0xc001
+#define TISCI_MSG_PROC_HANDOVER		0xc005
+#define TISCI_MSG_SET_PROC_BOOT_CONFIG	0xc100
+#define TISCI_MSG_SET_PROC_BOOT_CTRL	0xc101
+#define TISCI_MSG_PROC_AUTH_BOOT_IMIAGE	0xc120
+#define TISCI_MSG_GET_PROC_BOOT_STATUS	0xc400
+
 /**
  * struct ti_sci_msg_hdr - Generic Message Header for All messages and responses
  * @type:	Type of messages: One of TI_SCI_MSG* values
@@ -494,6 +503,178 @@
 struct ti_sci_msg_resp_get_clock_freq {
 	struct ti_sci_msg_hdr hdr;
 	u64 freq_hz;
+} __packed;
+
+#define TISCI_ADDR_LOW_MASK		GENMASK_ULL(31, 0)
+#define TISCI_ADDR_HIGH_MASK		GENMASK_ULL(63, 32)
+#define TISCI_ADDR_HIGH_SHIFT		32
+
+/**
+ * struct ti_sci_msg_req_proc_request - Request a processor
+ *
+ * @hdr:		Generic Header
+ * @processor_id:	ID of processor
+ *
+ * Request type is TISCI_MSG_PROC_REQUEST, response is a generic ACK/NACK
+ * message.
+ */
+struct ti_sci_msg_req_proc_request {
+	struct ti_sci_msg_hdr hdr;
+	u8 processor_id;
+} __packed;
+
+/**
+ * struct ti_sci_msg_req_proc_release - Release a processor
+ *
+ * @hdr:		Generic Header
+ * @processor_id:	ID of processor
+ *
+ * Request type is TISCI_MSG_PROC_RELEASE, response is a generic ACK/NACK
+ * message.
+ */
+struct ti_sci_msg_req_proc_release {
+	struct ti_sci_msg_hdr hdr;
+	u8 processor_id;
+} __packed;
+
+/**
+ * struct ti_sci_msg_req_proc_handover - Handover a processor to a host
+ *
+ * @hdr:		Generic Header
+ * @processor_id:	ID of processor
+ * @host_id:		New Host we want to give control to
+ *
+ * Request type is TISCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK
+ * message.
+ */
+struct ti_sci_msg_req_proc_handover {
+	struct ti_sci_msg_hdr hdr;
+	u8 processor_id;
+	u8 host_id;
+} __packed;
+
+/* A53 Config Flags */
+#define PROC_BOOT_CFG_FLAG_ARMV8_DBG_EN         0x00000001
+#define PROC_BOOT_CFG_FLAG_ARMV8_DBG_NIDEN      0x00000002
+#define PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPIDEN     0x00000004
+#define PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPNIDEN    0x00000008
+#define PROC_BOOT_CFG_FLAG_ARMV8_AARCH32        0x00000100
+
+/* R5 Config Flags */
+#define PROC_BOOT_CFG_FLAG_R5_DBG_EN            0x00000001
+#define PROC_BOOT_CFG_FLAG_R5_DBG_NIDEN         0x00000002
+#define PROC_BOOT_CFG_FLAG_R5_LOCKSTEP          0x00000100
+#define PROC_BOOT_CFG_FLAG_R5_TEINIT            0x00000200
+#define PROC_BOOT_CFG_FLAG_R5_NMFI_EN           0x00000400
+#define PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE       0x00000800
+#define PROC_BOOT_CFG_FLAG_R5_BTCM_EN           0x00001000
+#define PROC_BOOT_CFG_FLAG_R5_ATCM_EN           0x00002000
+
+/**
+ * struct ti_sci_msg_req_set_proc_boot_config - Set Processor boot configuration
+ * @hdr:		Generic Header
+ * @processor_id:	ID of processor
+ * @bootvector_low:	Lower 32bit (Little Endian) of boot vector
+ * @bootvector_high:	Higher 32bit (Little Endian) of boot vector
+ * @config_flags_set:	Optional Processor specific Config Flags to set.
+ *			Setting a bit here implies required bit sets to 1.
+ * @config_flags_clear:	Optional Processor specific Config Flags to clear.
+ *			Setting a bit here implies required bit gets cleared.
+ *
+ * Request type is TISCI_MSG_SET_PROC_BOOT_CONFIG, response is a generic
+ * ACK/NACK message.
+ */
+struct ti_sci_msg_req_set_proc_boot_config {
+	struct ti_sci_msg_hdr hdr;
+	u8 processor_id;
+	u32 bootvector_low;
+	u32 bootvector_high;
+	u32 config_flags_set;
+	u32 config_flags_clear;
+} __packed;
+
+/* R5 Control Flags */
+#define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT                0x00000001
+
+/**
+ * struct ti_sci_msg_req_set_proc_boot_ctrl - Set Processor boot control flags
+ * @hdr:		Generic Header
+ * @processor_id:	ID of processor
+ * @control_flags_set:	Optional Processor specific Control Flags to set.
+ *			Setting a bit here implies required bit sets to 1.
+ * @control_flags_clear:Optional Processor specific Control Flags to clear.
+ *			Setting a bit here implies required bit gets cleared.
+ *
+ * Request type is TISCI_MSG_SET_PROC_BOOT_CTRL, response is a generic ACK/NACK
+ * message.
+ */
+struct ti_sci_msg_req_set_proc_boot_ctrl {
+	struct ti_sci_msg_hdr hdr;
+	u8 processor_id;
+	u32 control_flags_set;
+	u32 control_flags_clear;
+} __packed;
+
+/**
+ * struct ti_sci_msg_req_proc_auth_start_image - Authenticate and start image
+ * @hdr:		Generic Header
+ * @processor_id:	ID of processor
+ * @cert_addr_low:	Lower 32bit (Little Endian) of certificate
+ * @cert_addr_high:	Higher 32bit (Little Endian) of certificate
+ *
+ * Request type is TISCI_MSG_PROC_AUTH_BOOT_IMAGE, response is a generic
+ * ACK/NACK message.
+ */
+struct ti_sci_msg_req_proc_auth_boot_image {
+	struct ti_sci_msg_hdr hdr;
+	u8 processor_id;
+	u32 cert_addr_low;
+	u32 cert_addr_high;
+} __packed;
+
+/**
+ * struct ti_sci_msg_req_get_proc_boot_status - Get processor boot status
+ * @hdr:		Generic Header
+ * @processor_id:	ID of processor
+ *
+ * Request type is TISCI_MSG_GET_PROC_BOOT_STATUS, response is appropriate
+ * message, or NACK in case of inability to satisfy request.
+ */
+struct ti_sci_msg_req_get_proc_boot_status {
+	struct ti_sci_msg_hdr hdr;
+	u8 processor_id;
+} __packed;
+
+/* ARMv8 Status Flags */
+#define PROC_BOOT_STATUS_FLAG_ARMV8_WFE			0x00000001
+#define PROC_BOOT_STATUS_FLAG_ARMV8_WFI			0x00000002
+
+/* R5 Status Flags */
+#define PROC_BOOT_STATUS_FLAG_R5_WFE			0x00000001
+#define PROC_BOOT_STATUS_FLAG_R5_WFI			0x00000002
+#define PROC_BOOT_STATUS_FLAG_R5_CLK_GATED		0x00000004
+#define PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED	0x00000100
+
+/**
+ * struct ti_sci_msg_resp_get_proc_boot_status - Processor boot status response
+ * @hdr:		Generic Header
+ * @processor_id:	ID of processor
+ * @bootvector_low:	Lower 32bit (Little Endian) of boot vector
+ * @bootvector_high:	Higher 32bit (Little Endian) of boot vector
+ * @config_flags:	Optional Processor specific Config Flags set.
+ * @control_flags:	Optional Processor specific Control Flags.
+ * @status_flags:	Optional Processor specific Status Flags set.
+ *
+ * Response to TISCI_MSG_GET_PROC_BOOT_STATUS.
+ */
+struct ti_sci_msg_resp_get_proc_boot_status {
+	struct ti_sci_msg_hdr hdr;
+	u8 processor_id;
+	u32 bootvector_low;
+	u32 bootvector_high;
+	u32 config_flags;
+	u32 control_flags;
+	u32 status_flags;
 } __packed;
  
 #endif /* __TI_SCI_H */
@@ -223,17 +223,54 @@
 };
  
 /**
+ * struct ti_sci_proc_ops - Processor specific operations.
+ *
+ * @proc_request: Request for controlling a physical processor.
+ *		The requesting host should be in the processor access list.
+ * @proc_release: Relinquish a physical processor control
+ * @proc_handover: Handover a physical processor control to another host
+ *		   in the permitted list.
+ * @set_proc_boot_cfg: Base configuration of the processor
+ * @set_proc_boot_ctrl: Setup limited control flags in specific cases.
+ * @proc_auth_boot_image:
+ * @get_proc_boot_status: Get the state of physical processor
+ *
+ * NOTE: for all these functions, the following parameters are generic in
+ * nature:
+ * -handle:	Pointer to TISCI handle as retrieved by *ti_sci_get_handle
+ * -pid:	Processor ID
+ *
+ */
+struct ti_sci_proc_ops {
+	int (*proc_request)(const struct ti_sci_handle *handle, u8 pid);
+	int (*proc_release)(const struct ti_sci_handle *handle, u8 pid);
+	int (*proc_handover)(const struct ti_sci_handle *handle, u8 pid,
+			     u8 hid);
+	int (*set_proc_boot_cfg)(const struct ti_sci_handle *handle, u8 pid,
+				 u64 bv, u32 cfg_set, u32 cfg_clr);
+	int (*set_proc_boot_ctrl)(const struct ti_sci_handle *handle, u8 pid,
+				  u32 ctrl_set, u32 ctrl_clr);
+	int (*proc_auth_boot_image)(const struct ti_sci_handle *handle, u8 pid,
+				    u64 caddr);
+	int (*get_proc_boot_status)(const struct ti_sci_handle *handle, u8 pid,
+				    u64 *bv, u32 *cfg_flags, u32 *ctrl_flags,
+				    u32 *sts_flags);
+};
+
+/**
  * struct ti_sci_ops - Function support for TI SCI
  * @board_ops:	Miscellaneous operations
  * @dev_ops:	Device specific operations
  * @clk_ops:	Clock specific operations
  * @core_ops:	Core specific operations
+ * @proc_ops:	Processor specific operations
  */
 struct ti_sci_ops {
 	struct ti_sci_board_ops board_ops;
 	struct ti_sci_dev_ops dev_ops;
 	struct ti_sci_clk_ops clk_ops;
 	struct ti_sci_core_ops core_ops;
+	struct ti_sci_proc_ops proc_ops;
 };
  
 /**
...	...	@@ -1441,6 +1441,368 @@
1441	1441	return ret;
1442	1442	}
1443	1443
	1444	+/**
	1445	+ * ti_sci_cmd_proc_request() - Command to request a physical processor control
	1446	+ * @handle: Pointer to TI SCI handle
	1447	+ * @proc_id: Processor ID this request is for
	1448	+ *
	1449	+ * Return: 0 if all went well, else returns appropriate error value.
	1450	+ */
	1451	+static int ti_sci_cmd_proc_request(const struct ti_sci_handle *handle,
	1452	+ u8 proc_id)
	1453	+{
	1454	+ struct ti_sci_msg_req_proc_request req;
	1455	+ struct ti_sci_msg_hdr *resp;
	1456	+ struct ti_sci_info *info;
	1457	+ struct ti_sci_xfer *xfer;
	1458	+ int ret = 0;
	1459	+
	1460	+ if (IS_ERR(handle))
	1461	+ return PTR_ERR(handle);
	1462	+ if (!handle)
	1463	+ return -EINVAL;
	1464	+
	1465	+ info = handle_to_ti_sci_info(handle);
	1466	+
	1467	+ xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_PROC_REQUEST,
	1468	+ TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
	1469	+ (u32 )&req, sizeof(req), sizeof(resp));
	1470	+ if (IS_ERR(xfer)) {
	1471	+ ret = PTR_ERR(xfer);
	1472	+ dev_err(info->dev, "Message alloc failed(%d)\n", ret);
	1473	+ return ret;
	1474	+ }
	1475	+ req.processor_id = proc_id;
	1476	+
	1477	+ ret = ti_sci_do_xfer(info, xfer);
	1478	+ if (ret) {
	1479	+ dev_err(info->dev, "Mbox send fail %d\n", ret);
	1480	+ return ret;
	1481	+ }
	1482	+
	1483	+ resp = (struct ti_sci_msg_hdr *)xfer->tx_message.buf;
	1484	+
	1485	+ if (!ti_sci_is_response_ack(resp))
	1486	+ ret = -ENODEV;
	1487	+
	1488	+ return ret;
	1489	+}
	1490	+
	1491	+/**
	1492	+ * ti_sci_cmd_proc_release() - Command to release a physical processor control
	1493	+ * @handle: Pointer to TI SCI handle
	1494	+ * @proc_id: Processor ID this request is for
	1495	+ *
	1496	+ * Return: 0 if all went well, else returns appropriate error value.
	1497	+ */
	1498	+static int ti_sci_cmd_proc_release(const struct ti_sci_handle *handle,
	1499	+ u8 proc_id)
	1500	+{
	1501	+ struct ti_sci_msg_req_proc_release req;
	1502	+ struct ti_sci_msg_hdr *resp;
	1503	+ struct ti_sci_info *info;
	1504	+ struct ti_sci_xfer *xfer;
	1505	+ int ret = 0;
	1506	+
	1507	+ if (IS_ERR(handle))
	1508	+ return PTR_ERR(handle);
	1509	+ if (!handle)
	1510	+ return -EINVAL;
	1511	+
	1512	+ info = handle_to_ti_sci_info(handle);
	1513	+
	1514	+ xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_PROC_RELEASE,
	1515	+ TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
	1516	+ (u32 )&req, sizeof(req), sizeof(resp));
	1517	+ if (IS_ERR(xfer)) {
	1518	+ ret = PTR_ERR(xfer);
	1519	+ dev_err(info->dev, "Message alloc failed(%d)\n", ret);
	1520	+ return ret;
	1521	+ }
	1522	+ req.processor_id = proc_id;
	1523	+
	1524	+ ret = ti_sci_do_xfer(info, xfer);
	1525	+ if (ret) {
	1526	+ dev_err(info->dev, "Mbox send fail %d\n", ret);
	1527	+ return ret;
	1528	+ }
	1529	+
	1530	+ resp = (struct ti_sci_msg_hdr *)xfer->tx_message.buf;
	1531	+
	1532	+ if (!ti_sci_is_response_ack(resp))
	1533	+ ret = -ENODEV;
	1534	+
	1535	+ return ret;
	1536	+}
	1537	+
	1538	+/**
	1539	+ * ti_sci_cmd_proc_handover() - Command to handover a physical processor
	1540	+ * control to a host in the processor's access
	1541	+ * control list.
	1542	+ * @handle: Pointer to TI SCI handle
	1543	+ * @proc_id: Processor ID this request is for
	1544	+ * @host_id: Host ID to get the control of the processor
	1545	+ *
	1546	+ * Return: 0 if all went well, else returns appropriate error value.
	1547	+ */
	1548	+static int ti_sci_cmd_proc_handover(const struct ti_sci_handle *handle,
	1549	+ u8 proc_id, u8 host_id)
	1550	+{
	1551	+ struct ti_sci_msg_req_proc_handover req;
	1552	+ struct ti_sci_msg_hdr *resp;
	1553	+ struct ti_sci_info *info;
	1554	+ struct ti_sci_xfer *xfer;
	1555	+ int ret = 0;
	1556	+
	1557	+ if (IS_ERR(handle))
	1558	+ return PTR_ERR(handle);
	1559	+ if (!handle)
	1560	+ return -EINVAL;
	1561	+
	1562	+ info = handle_to_ti_sci_info(handle);
	1563	+
	1564	+ xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_PROC_HANDOVER,
	1565	+ TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
	1566	+ (u32 )&req, sizeof(req), sizeof(resp));
	1567	+ if (IS_ERR(xfer)) {
	1568	+ ret = PTR_ERR(xfer);
	1569	+ dev_err(info->dev, "Message alloc failed(%d)\n", ret);
	1570	+ return ret;
	1571	+ }
	1572	+ req.processor_id = proc_id;
	1573	+ req.host_id = host_id;
	1574	+
	1575	+ ret = ti_sci_do_xfer(info, xfer);
	1576	+ if (ret) {
	1577	+ dev_err(info->dev, "Mbox send fail %d\n", ret);
	1578	+ return ret;
	1579	+ }
	1580	+
	1581	+ resp = (struct ti_sci_msg_hdr *)xfer->tx_message.buf;
	1582	+
	1583	+ if (!ti_sci_is_response_ack(resp))
	1584	+ ret = -ENODEV;
	1585	+
	1586	+ return ret;
	1587	+}
	1588	+
	1589	+/**
	1590	+ * ti_sci_cmd_set_proc_boot_cfg() - Command to set the processor boot
	1591	+ * configuration flags
	1592	+ * @handle: Pointer to TI SCI handle
	1593	+ * @proc_id: Processor ID this request is for
	1594	+ * @config_flags_set: Configuration flags to be set
	1595	+ * @config_flags_clear: Configuration flags to be cleared.
	1596	+ *
	1597	+ * Return: 0 if all went well, else returns appropriate error value.
	1598	+ */
	1599	+static int ti_sci_cmd_set_proc_boot_cfg(const struct ti_sci_handle *handle,
	1600	+ u8 proc_id, u64 bootvector,
	1601	+ u32 config_flags_set,
	1602	+ u32 config_flags_clear)
	1603	+{
	1604	+ struct ti_sci_msg_req_set_proc_boot_config req;
	1605	+ struct ti_sci_msg_hdr *resp;
	1606	+ struct ti_sci_info *info;
	1607	+ struct ti_sci_xfer *xfer;
	1608	+ int ret = 0;
	1609	+
	1610	+ if (IS_ERR(handle))
	1611	+ return PTR_ERR(handle);
	1612	+ if (!handle)
	1613	+ return -EINVAL;
	1614	+
	1615	+ info = handle_to_ti_sci_info(handle);
	1616	+
	1617	+ xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_SET_PROC_BOOT_CONFIG,
	1618	+ TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
	1619	+ (u32 )&req, sizeof(req), sizeof(resp));
	1620	+ if (IS_ERR(xfer)) {
	1621	+ ret = PTR_ERR(xfer);
	1622	+ dev_err(info->dev, "Message alloc failed(%d)\n", ret);
	1623	+ return ret;
	1624	+ }
	1625	+ req.processor_id = proc_id;
	1626	+ req.bootvector_low = bootvector & TISCI_ADDR_LOW_MASK;
	1627	+ req.bootvector_high = (bootvector & TISCI_ADDR_HIGH_MASK) >>
	1628	+ TISCI_ADDR_HIGH_SHIFT;
	1629	+ req.config_flags_set = config_flags_set;
	1630	+ req.config_flags_clear = config_flags_clear;
	1631	+
	1632	+ ret = ti_sci_do_xfer(info, xfer);
	1633	+ if (ret) {
	1634	+ dev_err(info->dev, "Mbox send fail %d\n", ret);
	1635	+ return ret;
	1636	+ }
	1637	+
	1638	+ resp = (struct ti_sci_msg_hdr *)xfer->tx_message.buf;
	1639	+
	1640	+ if (!ti_sci_is_response_ack(resp))
	1641	+ ret = -ENODEV;
	1642	+
	1643	+ return ret;
	1644	+}
	1645	+
	1646	+/**
	1647	+ * ti_sci_cmd_set_proc_boot_ctrl() - Command to set the processor boot
	1648	+ * control flags
	1649	+ * @handle: Pointer to TI SCI handle
	1650	+ * @proc_id: Processor ID this request is for
	1651	+ * @control_flags_set: Control flags to be set
	1652	+ * @control_flags_clear: Control flags to be cleared
	1653	+ *
	1654	+ * Return: 0 if all went well, else returns appropriate error value.
	1655	+ */
	1656	+static int ti_sci_cmd_set_proc_boot_ctrl(const struct ti_sci_handle *handle,
	1657	+ u8 proc_id, u32 control_flags_set,
	1658	+ u32 control_flags_clear)
	1659	+{
	1660	+ struct ti_sci_msg_req_set_proc_boot_ctrl req;
	1661	+ struct ti_sci_msg_hdr *resp;
	1662	+ struct ti_sci_info *info;
	1663	+ struct ti_sci_xfer *xfer;
	1664	+ int ret = 0;
	1665	+
	1666	+ if (IS_ERR(handle))
	1667	+ return PTR_ERR(handle);
	1668	+ if (!handle)
	1669	+ return -EINVAL;
	1670	+
	1671	+ info = handle_to_ti_sci_info(handle);
	1672	+
	1673	+ xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_SET_PROC_BOOT_CTRL,
	1674	+ TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
	1675	+ (u32 )&req, sizeof(req), sizeof(resp));
	1676	+ if (IS_ERR(xfer)) {
	1677	+ ret = PTR_ERR(xfer);
	1678	+ dev_err(info->dev, "Message alloc failed(%d)\n", ret);
	1679	+ return ret;
	1680	+ }
	1681	+ req.processor_id = proc_id;
	1682	+ req.control_flags_set = control_flags_set;
	1683	+ req.control_flags_clear = control_flags_clear;
	1684	+
	1685	+ ret = ti_sci_do_xfer(info, xfer);
	1686	+ if (ret) {
	1687	+ dev_err(info->dev, "Mbox send fail %d\n", ret);
	1688	+ return ret;
	1689	+ }
	1690	+
	1691	+ resp = (struct ti_sci_msg_hdr *)xfer->tx_message.buf;
	1692	+
	1693	+ if (!ti_sci_is_response_ack(resp))
	1694	+ ret = -ENODEV;
	1695	+
	1696	+ return ret;
	1697	+}
	1698	+
	1699	+/**
	1700	+ * ti_sci_cmd_proc_auth_boot_image() - Command to authenticate and load the
	1701	+ * image and then set the processor configuration flags.
	1702	+ * @handle: Pointer to TI SCI handle
	1703	+ * @proc_id: Processor ID this request is for
	1704	+ * @cert_addr: Memory address at which payload image certificate is located.
	1705	+ *
	1706	+ * Return: 0 if all went well, else returns appropriate error value.
	1707	+ */
	1708	+static int ti_sci_cmd_proc_auth_boot_image(const struct ti_sci_handle *handle,
	1709	+ u8 proc_id, u64 cert_addr)
	1710	+{
	1711	+ struct ti_sci_msg_req_proc_auth_boot_image req;
	1712	+ struct ti_sci_msg_hdr *resp;
	1713	+ struct ti_sci_info *info;
	1714	+ struct ti_sci_xfer *xfer;
	1715	+ int ret = 0;
	1716	+
	1717	+ if (IS_ERR(handle))
	1718	+ return PTR_ERR(handle);
	1719	+ if (!handle)
	1720	+ return -EINVAL;
	1721	+
	1722	+ info = handle_to_ti_sci_info(handle);
	1723	+
	1724	+ xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_PROC_AUTH_BOOT_IMIAGE,
	1725	+ TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
	1726	+ (u32 )&req, sizeof(req), sizeof(resp));
	1727	+ if (IS_ERR(xfer)) {
	1728	+ ret = PTR_ERR(xfer);
	1729	+ dev_err(info->dev, "Message alloc failed(%d)\n", ret);
	1730	+ return ret;
	1731	+ }
	1732	+ req.processor_id = proc_id;
	1733	+ req.cert_addr_low = cert_addr & TISCI_ADDR_LOW_MASK;
	1734	+ req.cert_addr_high = (cert_addr & TISCI_ADDR_HIGH_MASK) >>
	1735	+ TISCI_ADDR_HIGH_SHIFT;
	1736	+
	1737	+ ret = ti_sci_do_xfer(info, xfer);
	1738	+ if (ret) {
	1739	+ dev_err(info->dev, "Mbox send fail %d\n", ret);
	1740	+ return ret;
	1741	+ }
	1742	+
	1743	+ resp = (struct ti_sci_msg_hdr *)xfer->tx_message.buf;
	1744	+
	1745	+ if (!ti_sci_is_response_ack(resp))
	1746	+ ret = -ENODEV;
	1747	+
	1748	+ return ret;
	1749	+}
	1750	+
	1751	+/**
	1752	+ * ti_sci_cmd_get_proc_boot_status() - Command to get the processor boot status
	1753	+ * @handle: Pointer to TI SCI handle
	1754	+ * @proc_id: Processor ID this request is for
	1755	+ *
	1756	+ * Return: 0 if all went well, else returns appropriate error value.
	1757	+ */
	1758	+static int ti_sci_cmd_get_proc_boot_status(const struct ti_sci_handle *handle,
	1759	+ u8 proc_id, u64 bv, u32 cfg_flags,
	1760	+ u32 ctrl_flags, u32 sts_flags)
	1761	+{
	1762	+ struct ti_sci_msg_resp_get_proc_boot_status *resp;
	1763	+ struct ti_sci_msg_req_get_proc_boot_status req;
	1764	+ struct ti_sci_info *info;
	1765	+ struct ti_sci_xfer *xfer;
	1766	+ int ret = 0;
	1767	+
	1768	+ if (IS_ERR(handle))
	1769	+ return PTR_ERR(handle);
	1770	+ if (!handle)
	1771	+ return -EINVAL;
	1772	+
	1773	+ info = handle_to_ti_sci_info(handle);
	1774	+
	1775	+ xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_GET_PROC_BOOT_STATUS,
	1776	+ TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
	1777	+ (u32 )&req, sizeof(req), sizeof(resp));
	1778	+ if (IS_ERR(xfer)) {
	1779	+ ret = PTR_ERR(xfer);
	1780	+ dev_err(info->dev, "Message alloc failed(%d)\n", ret);
	1781	+ return ret;
	1782	+ }
	1783	+ req.processor_id = proc_id;
	1784	+
	1785	+ ret = ti_sci_do_xfer(info, xfer);
	1786	+ if (ret) {
	1787	+ dev_err(info->dev, "Mbox send fail %d\n", ret);
	1788	+ return ret;
	1789	+ }
	1790	+
	1791	+ resp = (struct ti_sci_msg_resp_get_proc_boot_status *)
	1792	+ xfer->tx_message.buf;
	1793	+
	1794	+ if (!ti_sci_is_response_ack(resp))
	1795	+ return -ENODEV;
	1796	+ *bv = (resp->bootvector_low & TISCI_ADDR_LOW_MASK) \|
	1797	+ (((u64)resp->bootvector_high <<
	1798	+ TISCI_ADDR_HIGH_SHIFT) & TISCI_ADDR_HIGH_MASK);
	1799	+ *cfg_flags = resp->config_flags;
	1800	+ *ctrl_flags = resp->control_flags;
	1801	+ *sts_flags = resp->status_flags;
	1802	+
	1803	+ return ret;
	1804	+}
	1805	+
1444	1806	/*
1445	1807	* ti_sci_setup_ops() - Setup the operations structures
1446	1808	* @info: pointer to TISCI pointer
...	...	@@ -1452,6 +1814,7 @@
1452	1814	struct ti_sci_dev_ops *dops = &ops->dev_ops;
1453	1815	struct ti_sci_clk_ops *cops = &ops->clk_ops;
1454	1816	struct ti_sci_core_ops *core_ops = &ops->core_ops;
	1817	+ struct ti_sci_proc_ops *pops = &ops->proc_ops;
1455	1818
1456	1819	bops->board_config = ti_sci_cmd_set_board_config;
1457	1820	bops->board_config_rm = ti_sci_cmd_set_board_config_rm;
...	...	@@ -1486,6 +1849,14 @@
1486	1849	cops->get_freq = ti_sci_cmd_clk_get_freq;
1487	1850
1488	1851	core_ops->reboot_device = ti_sci_cmd_core_reboot;
	1852	+
	1853	+ pops->proc_request = ti_sci_cmd_proc_request;
	1854	+ pops->proc_release = ti_sci_cmd_proc_release;
	1855	+ pops->proc_handover = ti_sci_cmd_proc_handover;
	1856	+ pops->set_proc_boot_cfg = ti_sci_cmd_set_proc_boot_cfg;
	1857	+ pops->set_proc_boot_ctrl = ti_sci_cmd_set_proc_boot_ctrl;
	1858	+ pops->proc_auth_boot_image = ti_sci_cmd_proc_auth_boot_image;
	1859	+ pops->get_proc_boot_status = ti_sci_cmd_get_proc_boot_status;
1489	1860	}
1490	1861
1491	1862	/**
...	...	@@ -41,6 +41,15 @@
41	41	#define TI_SCI_MSG_QUERY_CLOCK_FREQ 0x010d
42	42	#define TI_SCI_MSG_GET_CLOCK_FREQ 0x010e
43	43
	44	+/* Processor Control Messages */
	45	+#define TISCI_MSG_PROC_REQUEST 0xc000
	46	+#define TISCI_MSG_PROC_RELEASE 0xc001
	47	+#define TISCI_MSG_PROC_HANDOVER 0xc005
	48	+#define TISCI_MSG_SET_PROC_BOOT_CONFIG 0xc100
	49	+#define TISCI_MSG_SET_PROC_BOOT_CTRL 0xc101
	50	+#define TISCI_MSG_PROC_AUTH_BOOT_IMIAGE 0xc120
	51	+#define TISCI_MSG_GET_PROC_BOOT_STATUS 0xc400
	52	+
44	53	/**
45	54	* struct ti_sci_msg_hdr - Generic Message Header for All messages and responses
46	55	* @type: Type of messages: One of TI_SCI_MSG* values
...	...	@@ -494,6 +503,178 @@
494	503	struct ti_sci_msg_resp_get_clock_freq {
495	504	struct ti_sci_msg_hdr hdr;
496	505	u64 freq_hz;
	506	+} __packed;
	507	+
	508	+#define TISCI_ADDR_LOW_MASK GENMASK_ULL(31, 0)
	509	+#define TISCI_ADDR_HIGH_MASK GENMASK_ULL(63, 32)
	510	+#define TISCI_ADDR_HIGH_SHIFT 32
	511	+
	512	+/**
	513	+ * struct ti_sci_msg_req_proc_request - Request a processor
	514	+ *
	515	+ * @hdr: Generic Header
	516	+ * @processor_id: ID of processor
	517	+ *
	518	+ * Request type is TISCI_MSG_PROC_REQUEST, response is a generic ACK/NACK
	519	+ * message.
	520	+ */
	521	+struct ti_sci_msg_req_proc_request {
	522	+ struct ti_sci_msg_hdr hdr;
	523	+ u8 processor_id;
	524	+} __packed;
	525	+
	526	+/**
	527	+ * struct ti_sci_msg_req_proc_release - Release a processor
	528	+ *
	529	+ * @hdr: Generic Header
	530	+ * @processor_id: ID of processor
	531	+ *
	532	+ * Request type is TISCI_MSG_PROC_RELEASE, response is a generic ACK/NACK
	533	+ * message.
	534	+ */
	535	+struct ti_sci_msg_req_proc_release {
	536	+ struct ti_sci_msg_hdr hdr;
	537	+ u8 processor_id;
	538	+} __packed;
	539	+
	540	+/**
	541	+ * struct ti_sci_msg_req_proc_handover - Handover a processor to a host
	542	+ *
	543	+ * @hdr: Generic Header
	544	+ * @processor_id: ID of processor
	545	+ * @host_id: New Host we want to give control to
	546	+ *
	547	+ * Request type is TISCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK
	548	+ * message.
	549	+ */
	550	+struct ti_sci_msg_req_proc_handover {
	551	+ struct ti_sci_msg_hdr hdr;
	552	+ u8 processor_id;
	553	+ u8 host_id;
	554	+} __packed;
	555	+
	556	+/* A53 Config Flags */
	557	+#define PROC_BOOT_CFG_FLAG_ARMV8_DBG_EN 0x00000001
	558	+#define PROC_BOOT_CFG_FLAG_ARMV8_DBG_NIDEN 0x00000002
	559	+#define PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPIDEN 0x00000004
	560	+#define PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPNIDEN 0x00000008
	561	+#define PROC_BOOT_CFG_FLAG_ARMV8_AARCH32 0x00000100
	562	+
	563	+/* R5 Config Flags */
	564	+#define PROC_BOOT_CFG_FLAG_R5_DBG_EN 0x00000001
	565	+#define PROC_BOOT_CFG_FLAG_R5_DBG_NIDEN 0x00000002
	566	+#define PROC_BOOT_CFG_FLAG_R5_LOCKSTEP 0x00000100
	567	+#define PROC_BOOT_CFG_FLAG_R5_TEINIT 0x00000200
	568	+#define PROC_BOOT_CFG_FLAG_R5_NMFI_EN 0x00000400
	569	+#define PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE 0x00000800
	570	+#define PROC_BOOT_CFG_FLAG_R5_BTCM_EN 0x00001000
	571	+#define PROC_BOOT_CFG_FLAG_R5_ATCM_EN 0x00002000
	572	+
	573	+/**
	574	+ * struct ti_sci_msg_req_set_proc_boot_config - Set Processor boot configuration
	575	+ * @hdr: Generic Header
	576	+ * @processor_id: ID of processor
	577	+ * @bootvector_low: Lower 32bit (Little Endian) of boot vector
	578	+ * @bootvector_high: Higher 32bit (Little Endian) of boot vector
	579	+ * @config_flags_set: Optional Processor specific Config Flags to set.
	580	+ * Setting a bit here implies required bit sets to 1.
	581	+ * @config_flags_clear: Optional Processor specific Config Flags to clear.
	582	+ * Setting a bit here implies required bit gets cleared.
	583	+ *
	584	+ * Request type is TISCI_MSG_SET_PROC_BOOT_CONFIG, response is a generic
	585	+ * ACK/NACK message.
	586	+ */
	587	+struct ti_sci_msg_req_set_proc_boot_config {
	588	+ struct ti_sci_msg_hdr hdr;
	589	+ u8 processor_id;
	590	+ u32 bootvector_low;
	591	+ u32 bootvector_high;
	592	+ u32 config_flags_set;
	593	+ u32 config_flags_clear;
	594	+} __packed;
	595	+
	596	+/* R5 Control Flags */
	597	+#define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001
	598	+
	599	+/**
	600	+ * struct ti_sci_msg_req_set_proc_boot_ctrl - Set Processor boot control flags
	601	+ * @hdr: Generic Header
	602	+ * @processor_id: ID of processor
	603	+ * @control_flags_set: Optional Processor specific Control Flags to set.
	604	+ * Setting a bit here implies required bit sets to 1.
	605	+ * @control_flags_clear:Optional Processor specific Control Flags to clear.
	606	+ * Setting a bit here implies required bit gets cleared.
	607	+ *
	608	+ * Request type is TISCI_MSG_SET_PROC_BOOT_CTRL, response is a generic ACK/NACK
	609	+ * message.
	610	+ */
	611	+struct ti_sci_msg_req_set_proc_boot_ctrl {
	612	+ struct ti_sci_msg_hdr hdr;
	613	+ u8 processor_id;
	614	+ u32 control_flags_set;
	615	+ u32 control_flags_clear;
	616	+} __packed;
	617	+
	618	+/**
	619	+ * struct ti_sci_msg_req_proc_auth_start_image - Authenticate and start image
	620	+ * @hdr: Generic Header
	621	+ * @processor_id: ID of processor
	622	+ * @cert_addr_low: Lower 32bit (Little Endian) of certificate
	623	+ * @cert_addr_high: Higher 32bit (Little Endian) of certificate
	624	+ *
	625	+ * Request type is TISCI_MSG_PROC_AUTH_BOOT_IMAGE, response is a generic
	626	+ * ACK/NACK message.
	627	+ */
	628	+struct ti_sci_msg_req_proc_auth_boot_image {
	629	+ struct ti_sci_msg_hdr hdr;
	630	+ u8 processor_id;
	631	+ u32 cert_addr_low;
	632	+ u32 cert_addr_high;
	633	+} __packed;
	634	+
	635	+/**
	636	+ * struct ti_sci_msg_req_get_proc_boot_status - Get processor boot status
	637	+ * @hdr: Generic Header
	638	+ * @processor_id: ID of processor
	639	+ *
	640	+ * Request type is TISCI_MSG_GET_PROC_BOOT_STATUS, response is appropriate
	641	+ * message, or NACK in case of inability to satisfy request.
	642	+ */
	643	+struct ti_sci_msg_req_get_proc_boot_status {
	644	+ struct ti_sci_msg_hdr hdr;
	645	+ u8 processor_id;
	646	+} __packed;
	647	+
	648	+/* ARMv8 Status Flags */
	649	+#define PROC_BOOT_STATUS_FLAG_ARMV8_WFE 0x00000001
	650	+#define PROC_BOOT_STATUS_FLAG_ARMV8_WFI 0x00000002
	651	+
	652	+/* R5 Status Flags */
	653	+#define PROC_BOOT_STATUS_FLAG_R5_WFE 0x00000001
	654	+#define PROC_BOOT_STATUS_FLAG_R5_WFI 0x00000002
	655	+#define PROC_BOOT_STATUS_FLAG_R5_CLK_GATED 0x00000004
	656	+#define PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED 0x00000100
	657	+
	658	+/**
	659	+ * struct ti_sci_msg_resp_get_proc_boot_status - Processor boot status response
	660	+ * @hdr: Generic Header
	661	+ * @processor_id: ID of processor
	662	+ * @bootvector_low: Lower 32bit (Little Endian) of boot vector
	663	+ * @bootvector_high: Higher 32bit (Little Endian) of boot vector
	664	+ * @config_flags: Optional Processor specific Config Flags set.
	665	+ * @control_flags: Optional Processor specific Control Flags.
	666	+ * @status_flags: Optional Processor specific Status Flags set.
	667	+ *
	668	+ * Response to TISCI_MSG_GET_PROC_BOOT_STATUS.
	669	+ */
	670	+struct ti_sci_msg_resp_get_proc_boot_status {
	671	+ struct ti_sci_msg_hdr hdr;
	672	+ u8 processor_id;
	673	+ u32 bootvector_low;
	674	+ u32 bootvector_high;
	675	+ u32 config_flags;
	676	+ u32 control_flags;
	677	+ u32 status_flags;
497	678	} __packed;
498	679
499	680	#endif /* __TI_SCI_H */
...	...	@@ -223,17 +223,54 @@
223	223	};
224	224
225	225	/**
	226	+ * struct ti_sci_proc_ops - Processor specific operations.
	227	+ *
	228	+ * @proc_request: Request for controlling a physical processor.
	229	+ * The requesting host should be in the processor access list.
	230	+ * @proc_release: Relinquish a physical processor control
	231	+ * @proc_handover: Handover a physical processor control to another host
	232	+ * in the permitted list.
	233	+ * @set_proc_boot_cfg: Base configuration of the processor
	234	+ * @set_proc_boot_ctrl: Setup limited control flags in specific cases.
	235	+ * @proc_auth_boot_image:
	236	+ * @get_proc_boot_status: Get the state of physical processor
	237	+ *
	238	+ * NOTE: for all these functions, the following parameters are generic in
	239	+ * nature:
	240	+ * -handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
	241	+ * -pid: Processor ID
	242	+ *
	243	+ */
	244	+struct ti_sci_proc_ops {
	245	+ int (proc_request)(const struct ti_sci_handle handle, u8 pid);
	246	+ int (proc_release)(const struct ti_sci_handle handle, u8 pid);
	247	+ int (proc_handover)(const struct ti_sci_handle handle, u8 pid,
	248	+ u8 hid);
	249	+ int (set_proc_boot_cfg)(const struct ti_sci_handle handle, u8 pid,
	250	+ u64 bv, u32 cfg_set, u32 cfg_clr);
	251	+ int (set_proc_boot_ctrl)(const struct ti_sci_handle handle, u8 pid,
	252	+ u32 ctrl_set, u32 ctrl_clr);
	253	+ int (proc_auth_boot_image)(const struct ti_sci_handle handle, u8 pid,
	254	+ u64 caddr);
	255	+ int (get_proc_boot_status)(const struct ti_sci_handle handle, u8 pid,
	256	+ u64 bv, u32 cfg_flags, u32 *ctrl_flags,
	257	+ u32 *sts_flags);
	258	+};
	259	+
	260	+/**
226	261	* struct ti_sci_ops - Function support for TI SCI
227	262	* @board_ops: Miscellaneous operations
228	263	* @dev_ops: Device specific operations
229	264	* @clk_ops: Clock specific operations
230	265	* @core_ops: Core specific operations
	266	+ * @proc_ops: Processor specific operations
231	267	*/
232	268	struct ti_sci_ops {
233	269	struct ti_sci_board_ops board_ops;
234	270	struct ti_sci_dev_ops dev_ops;
235	271	struct ti_sci_clk_ops clk_ops;
236	272	struct ti_sci_core_ops core_ops;
	273	+ struct ti_sci_proc_ops proc_ops;
237	274	};
238	275
239	276	/**