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Commit cd12f615e4dd1dd24caab93f4157894783c6c1c0

Authored by Wolfgang Grandegger
Committed by Wolfgang Denk
1 parent d793b6bb1e
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

mpc52xx: add support for the IPEK01 board 

This patch adds support for the board IPEK01 based on the MPC5200.
The Futjitsu Lime graphics controller is configured in 16 bpp mode.

Signed-off-by: Wolfgang Grandegger <wg@denx.de>

Showing 7 changed files with 776 additions and 0 deletions Side-by-side Diff

... ... @@ -201,6 +201,8 @@
201 201  
202 202 Wolfgang Grandegger <wg@denx.de>
203 203  
  204 + ipek01 MPC5200
  205 +
204 206 CCM MPC855
205 207  
206 208 PN62 MPC8240
... ... @@ -63,6 +63,7 @@
63 63 icecube_5100 \
64 64 icecube_5200 \
65 65 inka4x0 \
  66 + ipek01 \
66 67 lite5200b \
67 68 mcc200 \
68 69 mecp5200 \
... ... @@ -606,6 +606,9 @@
606 606 inka4x0_config: unconfig
607 607 @$(MKCONFIG) inka4x0 ppc mpc5xxx inka4x0
608 608  
  609 +ipek01_config: unconfig
  610 + @$(MKCONFIG) -a ipek01 ppc mpc5xxx ipek01
  611 +
609 612 lite5200b_config \
610 613 lite5200b_PM_config \
611 614 lite5200b_LOWBOOT_config: unconfig
board/ipek01/Makefile
Diff comments   View file @ cd12f61
  1 +#
  2 +# (C) Copyright 2003-2006
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +include $(TOPDIR)/config.mk
  25 +
  26 +LIB = $(obj)lib$(BOARD).a
  27 +
  28 +COBJS := $(BOARD).o
  29 +
  30 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
  31 +OBJS := $(addprefix $(obj),$(COBJS))
  32 +SOBJS := $(addprefix $(obj),$(SOBJS))
  33 +
  34 +$(LIB): $(obj).depend $(OBJS)
  35 + $(AR) $(ARFLAGS) $@ $(OBJS)
  36 +
  37 +clean:
  38 + rm -f $(SOBJS) $(OBJS)
  39 +
  40 +distclean: clean
  41 + rm -f $(LIB) core *.bak .depend
  42 +
  43 +#########################################################################
  44 +
  45 +# defines $(obj).depend target
  46 +include $(SRCTREE)/rules.mk
  47 +
  48 +sinclude $(obj).depend
  49 +
  50 +#########################################################################
board/ipek01/config.mk
Diff comments   View file @ cd12f61
  1 +#
  2 +# (C) Copyright 2003-2004
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +#
  25 +# IPEK01 board
  26 +#
  27 +
  28 +TEXT_BASE = 0xfc000000
  29 +
  30 +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
board/ipek01/ipek01.c
Diff comments   View file @ cd12f61
  1 +/*
  2 + * (C) Copyright 2003-2004
  3 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 + *
  5 + * (C) Copyright 2004
  6 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
  7 + *
  8 + * (C) Copyright 2006
  9 + * MicroSys GmbH
  10 + *
  11 + * (C) Copyright 2009
  12 + * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
  13 + *
  14 + * See file CREDITS for list of people who contributed to this
  15 + * project.
  16 + *
  17 + * This program is free software; you can redistribute it and/or
  18 + * modify it under the terms of the GNU General Public License as
  19 + * published by the Free Software Foundation; either version 2 of
  20 + * the License, or (at your option) any later version.
  21 + *
  22 + * This program is distributed in the hope that it will be useful,
  23 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25 + * GNU General Public License for more details.
  26 + *
  27 + * You should have received a copy of the GNU General Public License
  28 + * along with this program; if not, write to the Free Software
  29 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30 + * MA 02111-1307 USA
  31 + */
  32 +
  33 +#include <common.h>
  34 +#include <mpc5xxx.h>
  35 +#include <pci.h>
  36 +#include <netdev.h>
  37 +#include <miiphy.h>
  38 +#include <libfdt.h>
  39 +#include <mb862xx.h>
  40 +#include <video_fb.h>
  41 +#include <asm/processor.h>
  42 +#include <asm/io.h>
  43 +
  44 +#ifdef CONFIG_OF_LIBFDT
  45 +#include <fdt_support.h>
  46 +#endif /* CONFIG_OF_LIBFDT */
  47 +
  48 +/* mt46v16m16-75 */
  49 +#ifdef CONFIG_MPC5200_DDR
  50 +/* Settings for XLB = 132 MHz */
  51 +#define SDRAM_MODE 0x018D0000
  52 +#define SDRAM_EMODE 0x40090000
  53 +#define SDRAM_CONTROL 0x714f0f00
  54 +#define SDRAM_CONFIG1 0x73722930
  55 +#define SDRAM_CONFIG2 0x47770000
  56 +#define SDRAM_TAPDELAY 0x10000000
  57 +#else
  58 +#error SDRAM is not supported on this board
  59 +#endif
  60 +
  61 +DECLARE_GLOBAL_DATA_PTR;
  62 +
  63 +static void sdram_start (int hi_addr)
  64 +{
  65 + struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
  66 + long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  67 +
  68 + /* unlock mode register */
  69 + out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit);
  70 +
  71 + /* precharge all banks */
  72 + out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
  73 +
  74 + /* set mode register: extended mode */
  75 + out_be32 (&sdram->mode, SDRAM_EMODE);
  76 +
  77 + /* set mode register: reset DLL */
  78 + out_be32 (&sdram->mode, SDRAM_MODE | 0x04000000);
  79 +
  80 + /* precharge all banks */
  81 + out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
  82 +
  83 + /* auto refresh */
  84 + out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit);
  85 +
  86 + /* set mode register */
  87 + out_be32 (&sdram->mode, SDRAM_MODE);
  88 +
  89 + /* normal operation */
  90 + out_be32 (&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit);
  91 +}
  92 +
  93 +/*
  94 + * ATTENTION: Although partially referenced initdram does NOT make real
  95 + * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
  96 + * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
  97 + */
  98 +
  99 +phys_size_t initdram (int board_type)
  100 +{
  101 + struct mpc5xxx_mmap_ctl *mmap_ctl =
  102 + (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
  103 + struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
  104 + struct mpc5xxx_cdm *cdm = (struct mpc5xxx_cdm *)MPC5XXX_CDM;
  105 + ulong dramsize = 0;
  106 + ulong dramsize2 = 0;
  107 + ulong test1, test2;
  108 +
  109 + /* setup SDRAM chip selects */
  110 + out_be32 (&mmap_ctl->sdram0, 0x0000001e); /* 2G at 0x0 */
  111 + out_be32 (&mmap_ctl->sdram1, 0x00000000); /* disabled */
  112 +
  113 + /* setup config registers */
  114 + out_be32 (&sdram->config1, SDRAM_CONFIG1);
  115 + out_be32 (&sdram->config2, SDRAM_CONFIG2);
  116 +
  117 + /* set tap delay */
  118 + out_be32 (&cdm->porcfg, SDRAM_TAPDELAY);
  119 +
  120 + /* find RAM size using SDRAM CS0 only */
  121 + sdram_start (0);
  122 + test1 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
  123 + sdram_start (1);
  124 + test2 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
  125 + if (test1 > test2) {
  126 + sdram_start (0);
  127 + dramsize = test1;
  128 + } else {
  129 + dramsize = test2;
  130 + }
  131 +
  132 + /* memory smaller than 1MB is impossible */
  133 + if (dramsize < (1 << 20))
  134 + dramsize = 0;
  135 +
  136 + /* set SDRAM CS0 size according to the amount of RAM found */
  137 + if (dramsize > 0)
  138 + out_be32 (&mmap_ctl->sdram0,
  139 + 0x13 + __builtin_ffs (dramsize >> 20) - 1);
  140 + else
  141 + out_be32 (&mmap_ctl->sdram1, 0); /* disabled */
  142 +
  143 + /*
  144 + * On MPC5200B we need to set the special configuration delay in the
  145 + * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
  146 + * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
  147 + *
  148 + * "The SDelay should be written to a value of 0x00000004. It is
  149 + * required to account for changes caused by normal wafer processing
  150 + * parameters."
  151 + */
  152 + out_be32 (&sdram->sdelay, 0x04);
  153 +
  154 + return dramsize + dramsize2;
  155 +}
  156 +
  157 +int checkboard (void)
  158 +{
  159 + puts ("Board: IPEK01 \n");
  160 + return 0;
  161 +}
  162 +
  163 +void flash_preinit (void)
  164 +{
  165 + struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
  166 +
  167 + /*
  168 + * Now, when we are in RAM, enable flash write
  169 + * access for detection process.
  170 + * Note that CS_BOOT cannot be cleared when
  171 + * executing in flash.
  172 + */
  173 + clrbits_be32 (&lpb->cs0_cfg, 0x1); /* clear RO */
  174 +}
  175 +
  176 +void flash_afterinit (ulong start, ulong size)
  177 +{
  178 + struct mpc5xxx_mmap_ctl *mmap_ctl =
  179 + (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
  180 +
  181 +#if defined(CONFIG_BOOT_ROM)
  182 + /* adjust mapping */
  183 + out_be32 (&mmap_ctl->cs1_start, START_REG (start));
  184 + out_be32 (&mmap_ctl->cs1_stop, STOP_REG (start, size));
  185 +#else
  186 + /* adjust mapping */
  187 + out_be32 (&mmap_ctl->boot_start, START_REG (start));
  188 + out_be32 (&mmap_ctl->cs0_start, START_REG (start));
  189 + out_be32 (&mmap_ctl->boot_stop, STOP_REG (start, size));
  190 + out_be32 (&mmap_ctl->cs0_stop, STOP_REG (start, size));
  191 +#endif
  192 +}
  193 +
  194 +extern flash_info_t flash_info[]; /* info for FLASH chips */
  195 +
  196 +int misc_init_r (void)
  197 +{
  198 + /* adjust flash start */
  199 + gd->bd->bi_flashstart = flash_info[0].start[0];
  200 + return (0);
  201 +}
  202 +
  203 +#ifdef CONFIG_PCI
  204 +static struct pci_controller hose;
  205 +
  206 +extern void pci_mpc5xxx_init (struct pci_controller *);
  207 +
  208 +void pci_init_board (void)
  209 +{
  210 + pci_mpc5xxx_init (&hose);
  211 +}
  212 +#endif
  213 +
  214 +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  215 +void ft_board_setup (void *blob, bd_t * bd)
  216 +{
  217 + ft_cpu_setup (blob, bd);
  218 + fdt_fixup_memory (blob, (u64) bd->bi_memstart, (u64) bd->bi_memsize);
  219 +}
  220 +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
  221 +
  222 +int board_eth_init(bd_t *bis)
  223 +{
  224 + cpu_eth_init(bis); /* Built in FEC comes first */
  225 + return pci_eth_init(bis);
  226 +}
  227 +
  228 +#ifdef CONFIG_VIDEO
  229 +extern GraphicDevice mb862xx;
  230 +
  231 +static const gdc_regs init_regs[] = {
  232 + {0x0100, 0x00000900},
  233 + {0x0020, 0x80190257},
  234 + {0x0024, 0x00000000},
  235 + {0x0028, 0x00000000},
  236 + {0x002c, 0x00000000},
  237 + {0x0110, 0x00000000},
  238 + {0x0114, 0x00000000},
  239 + {0x0118, 0x02570320},
  240 + {0x0004, 0x041f0000},
  241 + {0x0008, 0x031f031f},
  242 + {0x000c, 0x067f0347},
  243 + {0x0010, 0x02780000},
  244 + {0x0014, 0x0257025c},
  245 + {0x0018, 0x00000000},
  246 + {0x001c, 0x02570320},
  247 + {0x0100, 0x80010900},
  248 + {0x0, 0x0}
  249 +};
  250 +
  251 +const gdc_regs *board_get_regs (void)
  252 +{
  253 + return init_regs;
  254 +}
  255 +
  256 +/* Returns Lime base address */
  257 +unsigned int board_video_init (void)
  258 +{
  259 + if (mb862xx_probe (CONFIG_SYS_LIME_BASE) != MB862XX_TYPE_LIME)
  260 + return 0;
  261 +
  262 + mb862xx.winSizeX = 800;
  263 + mb862xx.winSizeY = 600;
  264 + mb862xx.gdfIndex = GDF_15BIT_555RGB;
  265 + mb862xx.gdfBytesPP = 2;
  266 +
  267 + return CONFIG_SYS_LIME_BASE;
  268 +}
  269 +
  270 +#if defined(CONFIG_CONSOLE_EXTRA_INFO)
  271 +/*
  272 + * Return text to be printed besides the logo.
  273 + */
  274 +void video_get_info_str (int line_number, char *info)
  275 +{
  276 + if (line_number == 1)
  277 + strcpy (info, " Board: IPEK01");
  278 + else
  279 + info[0] = '\0';
  280 +}
  281 +#endif
  282 +#endif /* CONFIG_VIDEO */
include/configs/ipek01.h
Diff comments   View file @ cd12f61
  1 +/*
  2 + * (C) Copyright 2006
  3 + * MicroSys GmbH
  4 + *
  5 + * (C) Copyright 2009
  6 + * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
  7 + *
  8 + * See file CREDITS for list of people who contributed to this
  9 + * project.
  10 + *
  11 + * This program is free software; you can redistribute it and/or
  12 + * modify it under the terms of the GNU General Public License as
  13 + * published by the Free Software Foundation; either version 2 of
  14 + * the License, or (at your option) any later version.
  15 + *
  16 + * This program is distributed in the hope that it will be useful,
  17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19 + * GNU General Public License for more details.
  20 + *
  21 + * You should have received a copy of the GNU General Public License
  22 + * along with this program; if not, write to the Free Software
  23 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 + * MA 02111-1307 USA
  25 + */
  26 +
  27 +#ifndef __CONFIG_H
  28 +#define __CONFIG_H
  29 +
  30 +/*
  31 + * High Level Configuration Options
  32 + */
  33 +
  34 +#define CONFIG_MPC5200
  35 +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
  36 +#define CONFIG_MPX5200 1 /* ... on MPX5200 board */
  37 +#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
  38 +#define CONFIG_IPEK01 /* Motherboard is ipek01 */
  39 +
  40 +#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
  41 +
  42 +#define CONFIG_MISC_INIT_R
  43 +
  44 +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  45 +#define BOOTFLAG_WARM 0x02 /* Software reboot */
  46 +
  47 +#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
  48 +#ifdef CONFIG_CMD_KGDB
  49 +#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  50 +#endif
  51 +
  52 +/*
  53 + * Serial console configuration
  54 + */
  55 +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
  56 +#define CONFIG_BAUDRATE 115200 /* ... at 9600 bps */
  57 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
  58 +
  59 +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
  60 +
  61 +/*
  62 + * Video configuration for LIME GDC
  63 + */
  64 +#define CONFIG_VIDEO
  65 +#ifdef CONFIG_VIDEO
  66 +#define CONFIG_VIDEO_MB862xx
  67 +#define CONFIG_VIDEO_MB862xx_ACCEL
  68 +#define VIDEO_FB_16BPP_WORD_SWAP
  69 +#define CONFIG_CFB_CONSOLE
  70 +#define CONFIG_VIDEO_LOGO
  71 +#define CONFIG_VIDEO_BMP_LOGO
  72 +#define CONFIG_CONSOLE_EXTRA_INFO
  73 +#define CONFIG_VGA_AS_SINGLE_DEVICE
  74 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV
  75 +#define CONFIG_VIDEO_SW_CURSOR
  76 +#define CONFIG_SPLASH_SCREEN
  77 +#define CONFIG_VIDEO_BMP_GZIP
  78 +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
  79 +/* Lime clock frequency */
  80 +#define CONFIG_SYS_MB862xx_CCF 0x90000 /* geo 166MHz other 133MHz */
  81 +/* SDRAM parameter */
  82 +#define CONFIG_SYS_MB862xx_MMR 0x41c767e3
  83 +#endif
  84 +
  85 +/*
  86 + * PCI Mapping:
  87 + * 0x40000000 - 0x4fffffff - PCI Memory
  88 + * 0x50000000 - 0x50ffffff - PCI IO Space
  89 + */
  90 +#define CONFIG_PCI 1
  91 +#define CONFIG_PCI_PNP 1
  92 +#define CONFIG_PCI_SCAN_SHOW 1
  93 +
  94 +#define CONFIG_PCI_MEM_BUS 0x40000000
  95 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
  96 +#define CONFIG_PCI_MEM_SIZE 0x10000000
  97 +
  98 +#define CONFIG_PCI_IO_BUS 0x50000000
  99 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
  100 +#define CONFIG_PCI_IO_SIZE 0x01000000
  101 +
  102 +#define CONFIG_NET_MULTI 1
  103 +#define CONFIG_MII 1
  104 +#define CONFIG_EEPRO100 1
  105 +#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
  106 +
  107 +/* Partitions */
  108 +#define CONFIG_DOS_PARTITION
  109 +
  110 +/* USB */
  111 +#define CONFIG_USB_OHCI_NEW
  112 +#define CONFIG_SYS_OHCI_BE_CONTROLLER
  113 +#define CONFIG_USB_STORAGE
  114 +
  115 +#define CONFIG_SYS_USB_OHCI_CPU_INIT
  116 +#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
  117 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
  118 +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
  119 +
  120 +/*
  121 + * Command line configuration.
  122 + */
  123 +#include <config_cmd_default.h>
  124 +
  125 +#ifdef CONFIG_VIDEO
  126 +#define CONFIG_CMD_BMP /* BMP support */
  127 +#endif
  128 +#define CONFIG_CMD_DATE /* support for RTC, date/time...*/
  129 +#define CONFIG_CMD_DHCP /* DHCP Support */
  130 +#define CONFIG_CMD_FAT /* FAT support */
  131 +#define CONFIG_CMD_I2C /* I2C serial bus support */
  132 +#define CONFIG_CMD_IDE /* IDE harddisk support */
  133 +#define CONFIG_CMD_IRQ /* irqinfo */
  134 +#define CONFIG_CMD_MII /* MII support */
  135 +#define CONFIG_CMD_PCI /* pciinfo */
  136 +#define CONFIG_CMD_USB /* USB Support */
  137 +
  138 +#define CONFIG_SYS_LOWBOOT 1
  139 +
  140 +/*
  141 + * Autobooting
  142 + */
  143 +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  144 +
  145 +#define CONFIG_PREBOOT "echo;" \
  146 + "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  147 + "echo"
  148 +
  149 +#undef CONFIG_BOOTARGS
  150 +
  151 +#define CONFIG_EXTRA_ENV_SETTINGS \
  152 + "netdev=eth0\0" \
  153 + "consoledev=ttyPSC0\0" \
  154 + "hostname=ipek01\0" \
  155 + "nfsargs=setenv bootargs root=/dev/nfs rw " \
  156 + "nfsroot=${serverip}:${rootpath}\0" \
  157 + "ramargs=setenv bootargs root=/dev/ram rw\0" \
  158 + "addip=setenv bootargs ${bootargs} " \
  159 + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  160 + ":${hostname}:${netdev}:off panic=1\0" \
  161 + "addtty=setenv bootargs ${bootargs} " \
  162 + "console=${consoledev},${baudrate}\0" \
  163 + "flash_nfs=run nfsargs addip addtty;" \
  164 + "bootm ${kernel_addr} - ${fdtaddr}\0" \
  165 + "flash_self=run ramargs addip addtty;" \
  166 + "bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0" \
  167 + "net_nfs=tftp 200000 ${bootfile}; tftp ${fdtaddr} ${fdtfile};" \
  168 + "run nfsargs addip addtty;" \
  169 + "bootm ${loadaddr} - ${fdtaddr}\0" \
  170 + "rootpath=/opt/eldk/ppc_6xx\0" \
  171 + "bootfile=ipek01/uImage\0" \
  172 + "load=tftp 100000 ipek01/u-boot.bin\0" \
  173 + "update=protect off FC000000 +60000; era FC000000 +60000; " \
  174 + "cp.b 100000 FC000000 ${filesize}\0" \
  175 + "upd=run load;run update\0" \
  176 + "fdtaddr=800000\0" \
  177 + "loadaddr=400000\0" \
  178 + "fdtfile=ipek01/ipek01.dtb\0" \
  179 + ""
  180 +
  181 +#define CONFIG_BOOTCOMMAND "run flash_self"
  182 +
  183 +/*
  184 + * IPB Bus clocking configuration.
  185 + */
  186 +#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* for 133MHz */
  187 +/* PCI clock must be 33, because board will not boot */
  188 +#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for 66MHz */
  189 +
  190 +/*
  191 + * Open firmware flat tree support
  192 + */
  193 +#define CONFIG_OF_LIBFDT 1
  194 +#define CONFIG_OF_BOARD_SETUP 1
  195 +
  196 +#define OF_CPU "PowerPC,5200@0"
  197 +#define OF_SOC "soc5200@f0000000"
  198 +#define OF_TBCLK (bd->bi_busfreq / 4)
  199 +
  200 +/*
  201 + * I2C configuration
  202 + */
  203 +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
  204 +#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
  205 +
  206 +#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
  207 +#define CONFIG_SYS_I2C_SLAVE 0x7F
  208 +
  209 +/*
  210 + * EEPROM configuration
  211 + */
  212 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
  213 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  214 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
  215 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
  216 +
  217 +/*
  218 + * RTC configuration
  219 + */
  220 +#define CONFIG_RTC_PCF8563
  221 +#define CONFIG_SYS_I2C_RTC_ADDR 0x51
  222 +
  223 +#define CONFIG_SYS_FLASH_BASE 0xFC000000
  224 +#define CONFIG_SYS_FLASH_SIZE 0x01000000
  225 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
  226 + CONFIG_SYS_MONITOR_LEN)
  227 +
  228 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
  229 +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
  230 +#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
  231 +
  232 +/* use CFI flash driver */
  233 +#define CONFIG_FLASH_CFI_DRIVER
  234 +#define CONFIG_SYS_FLASH_CFI
  235 +#define CONFIG_SYS_FLASH_EMPTY_INFO
  236 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
  237 +
  238 +/*
  239 + * Environment settings
  240 + */
  241 +#define CONFIG_ENV_IS_IN_FLASH 1
  242 +#define CONFIG_ENV_SIZE 0x10000
  243 +#define CONFIG_ENV_SECT_SIZE 0x20000
  244 +#define CONFIG_ENV_OVERWRITE 1
  245 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
  246 +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
  247 +
  248 +/*
  249 + * Memory map
  250 + */
  251 +#define CONFIG_SYS_MBAR 0xf0000000
  252 +#define CONFIG_SYS_SDRAM_BASE 0x00000000
  253 +#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
  254 +#define CONFIG_SYS_SRAM_BASE 0xF1000000
  255 +#define CONFIG_SYS_SRAM_SIZE 0x00200000
  256 +#define CONFIG_SYS_LIME_BASE 0xE4000000
  257 +#define CONFIG_SYS_LIME_SIZE 0x04000000
  258 +#define CONFIG_SYS_FPGA_BASE 0xC0000000
  259 +#define CONFIG_SYS_FPGA_SIZE 0x10000000
  260 +#define CONFIG_SYS_MPEG_BASE 0xe2000000
  261 +#define CONFIG_SYS_MPEG_SIZE 0x01000000
  262 +#define CONFIG_SYS_CF_BASE 0xe1000000
  263 +#define CONFIG_SYS_CF_SIZE 0x01000000
  264 +
  265 +/* Use SRAM until RAM will be available */
  266 +#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
  267 +/* End of used area in DPRAM */
  268 +#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
  269 +
  270 +
  271 +
  272 +/* size in bytes reserved for initial data */
  273 +#define CONFIG_SYS_GBL_DATA_SIZE 128
  274 +
  275 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
  276 + CONFIG_SYS_GBL_DATA_SIZE)
  277 +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  278 +
  279 +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
  280 +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  281 +# define CONFIG_SYS_RAMBOOT 1
  282 +#endif
  283 +
  284 +#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
  285 +#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 128 kB for malloc() */
  286 +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  287 +
  288 +/*
  289 + * Ethernet configuration
  290 + */
  291 +#define CONFIG_MPC5xxx_FEC 1
  292 +#define CONFIG_MPC5xxx_FEC_MII100
  293 +#define CONFIG_PHY_ADDR 0x00
  294 +
  295 +/*
  296 + * GPIO configuration
  297 + */
  298 +#define CONFIG_SYS_GPS_PORT_CONFIG 0x1d556624
  299 +
  300 +/*
  301 + * Miscellaneous configurable options
  302 + */
  303 +#define CONFIG_SYS_LONGHELP /* undef to save memory */
  304 +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  305 +#ifdef CONFIG_CMD_KGDB
  306 +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  307 +#else
  308 +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  309 +#endif
  310 +/* Print Buffer Size */
  311 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  312 + sizeof(CONFIG_SYS_PROMPT) + 16)
  313 +/* max number of command args */
  314 +#define CONFIG_SYS_MAXARGS 16
  315 +/* Boot Argument Buffer Size */
  316 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  317 +
  318 +
  319 +#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
  320 +#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1...15 MB in DRAM */
  321 +
  322 +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
  323 +
  324 +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
  325 +#define CONFIG_LOOPW
  326 +
  327 +/*
  328 + * Various low-level settings
  329 + */
  330 +#if defined(CONFIG_MPC5200)
  331 +#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
  332 +#define CONFIG_SYS_HID0_FINAL HID0_ICE
  333 +#else
  334 +#define CONFIG_SYS_HID0_INIT 0
  335 +#define CONFIG_SYS_HID0_FINAL 0
  336 +#endif
  337 +
  338 +#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
  339 +#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
  340 +#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
  341 +#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
  342 +#define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE
  343 +#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_SRAM_SIZE
  344 +#define CONFIG_SYS_CS3_START CONFIG_SYS_LIME_BASE
  345 +#define CONFIG_SYS_CS3_SIZE CONFIG_SYS_LIME_SIZE
  346 +#define CONFIG_SYS_CS6_START CONFIG_SYS_FPGA_BASE
  347 +#define CONFIG_SYS_CS6_SIZE CONFIG_SYS_FPGA_SIZE
  348 +#define CONFIG_SYS_CS5_START CONFIG_SYS_CF_BASE
  349 +#define CONFIG_SYS_CS5_SIZE CONFIG_SYS_CF_SIZE
  350 +#define CONFIG_SYS_CS7_START CONFIG_SYS_MPEG_BASE
  351 +#define CONFIG_SYS_CS7_SIZE CONFIG_SYS_MPEG_SIZE
  352 +
  353 +#ifdef CONFIG_SYS_PCISPEED_66
  354 +#define CONFIG_SYS_BOOTCS_CFG 0x0006F900
  355 +#define CONFIG_SYS_CS1_CFG 0x0004FB00
  356 +#define CONFIG_SYS_CS2_CFG 0x0006F900
  357 +#else
  358 +#define CONFIG_SYS_BOOTCS_CFG 0x0002F900
  359 +#define CONFIG_SYS_CS1_CFG 0x0001FB00
  360 +#define CONFIG_SYS_CS2_CFG 0x0002F90C
  361 +#endif
  362 +
  363 +/*
  364 + * Ack active, Muxed mode, AS=24 bit address, DS=32 bit data, 0
  365 + * waitstates, writeswap and readswap enabled
  366 + */
  367 +#define CONFIG_SYS_CS3_CFG 0x00FFFB0C
  368 +#define CONFIG_SYS_CS6_CFG 0x00FFFB0C
  369 +#define CONFIG_SYS_CS7_CFG 0x4040751C
  370 +
  371 +#define CONFIG_SYS_CS_BURST 0x00000000
  372 +#define CONFIG_SYS_CS_DEADCYCLE 0x33330000
  373 +
  374 +#define CONFIG_SYS_RESET_ADDRESS 0xff000000
  375 +
  376 +/*-----------------------------------------------------------------------
  377 + * USB stuff
  378 + *-----------------------------------------------------------------------
  379 + */
  380 +#define CONFIG_USB_CLOCK 0x0001BBBB
  381 +#define CONFIG_USB_CONFIG 0x00005000
  382 +
  383 +/*-----------------------------------------------------------------------
  384 + * IDE/ATA stuff Supports IDE harddisk
  385 + *-----------------------------------------------------------------------
  386 + */
  387 +#define CONFIG_IDE_PREINIT
  388 +
  389 +#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
  390 +#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
  391 +
  392 +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
  393 +
  394 +#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
  395 +
  396 +/* Offset for data I/O */
  397 +#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
  398 +
  399 +/* Offset for normal register accesses */
  400 +#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
  401 +
  402 +/* Offset for alternate registers */
  403 +#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
  404 +
  405 +/* Interval between registers */
  406 +#define CONFIG_SYS_ATA_STRIDE 4
  407 +
  408 +#endif /* __CONFIG_H */