* Patch by Jian Zhang, 3 Feb 2004:

- Changed the incorrect FAT12BUFSIZE - data_begin in fsdata can be negative. Changed it to be short. * Code cleanup

* Patch by Jian Zhang, 3 Feb 2004:
- Changed the incorrect FAT12BUFSIZE - data_begin in fsdata can be negative. Changed it to be short. * Code cleanup
wdenk
1 parent ec4c544bed
Showing 9 changed files with 45 additions and 49 deletions Side-by-side Diff
CHANGELOG
board/esteem192e/esteem192e.c
board/omap1610inn/flash.c
board/tb0229/flash.c
drivers/cfi_flash.c
drivers/pci_auto.c
include/configs/tb0229.h
include/fat.h
rtc/ds1306.c
@@ -2,6 +2,10 @@
 Changes since U-Boot 1.0.1:
 ======================================================================
  
+* Patch by Jian Zhang, 3 Feb 2004:
+  - Changed the incorrect FAT12BUFSIZE
+  - data_begin in fsdata can be negative. Changed it to be short.
+
 * Patches by Stephan Linz, 30 Jan 2004:
   1: - board/altera/common/flash.c:flash_erase():
        o allow interrupts befor get_timer() call
@@ -113,7 +113,7 @@
  
 	memctl->memc_mptpr = 0x0200;	/* divide by 32 */
  
-	memctl->memc_mamr = 0x18003112;	/*CFG_MAMR_8COL; *//* 0x18005112 TODO: explain here */
+	memctl->memc_mamr = 0x18003112;	/*CFG_MAMR_8COL; */ /* 0x18005112 TODO: explain here */
  
 	upmconfig (UPMA, (uint *) sdram_table,
 		   sizeof (sdram_table) / sizeof (uint));
@@ -19,7 +19,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -32,7 +32,7 @@
 #include <linux/byteorder/swab.h>
  
 #define PHYS_FLASH_SECT_SIZE	0x00020000	/* 256 KB sectors (x2) */
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips	   */
  
 /* Board support for 1 or 2 flash devices */
 #undef FLASH_PORT_WIDTH32
@@ -120,13 +120,13 @@
  */
 flash_unlock(flash_info_t * info)
 {
-        int j;
-        for (j=2;j<CFG_MAX_FLASH_SECT;j++){
-        FPWV *addr = (FPWV *) (info->start[j]);
-        flash_unprotect_sectors (addr);
-        *addr = (FPW) 0x00500050;/* clear status register */
-        *addr = (FPW) 0x00FF00FF;/* resest to read mode */
-        }
+	int j;
+	for (j=2;j<CFG_MAX_FLASH_SECT;j++){
+	FPWV *addr = (FPWV *) (info->start[j]);
+	flash_unprotect_sectors (addr);
+	*addr = (FPW) 0x00500050;/* clear status register */
+	*addr = (FPW) 0x00FF00FF;/* resest to read mode */
+	}
 }
  
 /*-----------------------------------------------------------------------
@@ -192,7 +192,7 @@
 		if ((i % 5) == 0)
 			printf ("\n   ");
 		printf (" %08lX%s",
-			info->start[i], info->protect[i] ? " (RO)" : "     ");
+			info->start[i], info->protect[i] ? " (RO)" : "	   ");
 	}
 	printf ("\n");
 	return;
  
  
@@ -224,18 +224,18 @@
 		info->sector_count = 0;
 		info->size = 0;
 		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
-		return (0);		/* no or unknown flash  */
+		return (0);		/* no or unknown flash	*/
 	}
  
 	mb ();
-	value = addr[1];	/* device ID        */
+	value = addr[1];	/* device ID	    */
 	switch (value) {
  
 	case (FPW) (INTEL_ID_28F256L18T):
 		info->flash_id += FLASH_28F256L18T;
 		info->sector_count = 259;
 		info->size = 0x02000000;
-		break;			/* => 32 MB     */
+		break;			/* => 32 MB	*/
  
 	default:
 		info->flash_id = FLASH_UNKNOWN;
@@ -318,7 +318,7 @@
  
 	/* Start erase on unprotected sectors */
 	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
+		if (info->protect[sect] == 0) { /* not protected */
 			FPWV *addr = (FPWV *) (info->start[sect]);
 			FPW status;
  
@@ -348,7 +348,7 @@
 				}
 			}
  
-			/* clear status register cmd.   */
+			/* clear status register cmd.	*/
 			*addr = (FPW) 0x00500050;
 			*addr = (FPW) 0x00FF00FF;/* resest to read mode */
 			printf (" done\n");
@@ -860,7 +860,7 @@
 	}
  
 	for (info = info_first; info <= info_last; ++info) {
-										ulong b_end = info->start[0] + info->size;*//* bank end addr */
+										ulong b_end = info->start[0] + info->size;*/ /* bank end addr */
 /*		short s_end = info->sector_count - 1;
 		for (i=0; i<info->sector_count; ++i) {
 			ulong e_addr = (i == s_end) ? b_end : info->start[i + 1];
@@ -872,7 +872,7 @@
 		}
 	}
  
-*//* finally write data to flash */
+*/ /* finally write data to flash */
 /*	for (info = info_first; info <= info_last && cnt>0; ++info) {
 		ulong len;
  
@@ -30,11 +30,11 @@
  * Tested Architectures
  * Port Width  Chip Width    # of banks    Flash Chip  Board
  * 32          16            1             23F128J3    seranoa/eagle
- * 
+ *
  */
  
 /* The DEBUG define must be before common to enable debugging */
-#undef  DEBUG 
+#undef  DEBUG
 #include <common.h>
 #include <asm/processor.h>
 #ifdef  CFG_FLASH_CFI_DRIVER
@@ -170,8 +170,8 @@
 	int i;
 	char *cp;
 	cp = (unsigned char *)&data;
-	for(i=0;i<8; i++) 
-		sprintf(&str[i*2], "%2.2x", *cp++);  
+	for(i=0;i<8; i++)
+		sprintf(&str[i*2], "%2.2x", *cp++);
 }
 #endif
  
@@ -501,7 +501,7 @@
 void flash_read_factory_serial(flash_info_t * info, void * buffer, int offset, int len)
 {
 	uchar * src;
-	
+
 	src = flash_make_addr(info, 0, FLASH_OFFSET_INTEL_PROTECTION);
 	flash_write_cmd(info,0, 0, FLASH_CMD_READ_ID);
 	memcpy(buffer,src + offset,len);
@@ -510,7 +510,7 @@
  
 #endif /* CFG_FLASH_PROTECTION */
  
-static int flash_poll_status(flash_info_t * info, flash_sect_t sect) 
+static int flash_poll_status(flash_info_t * info, flash_sect_t sect)
 {
 	int retval;
 	switch(info->vendor) {
  
  
  
  
@@ -626,27 +626,27 @@
 	flash_make_cmd(info, cmd, &cword);
 	switch(info->portwidth) {
 	case FLASH_CFI_8BIT:
-		debug("fwc addr %p cmd %x %x 8bit x %d bit\n",addr.cp, cmd, cword.c, 
+		debug("fwc addr %p cmd %x %x 8bit x %d bit\n",addr.cp, cmd, cword.c,
 		       info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
 		*addr.cp = cword.c;
 		break;
 	case FLASH_CFI_16BIT:
-		debug("fwc addr %p cmd %x %4.4x 16bit x %d bit\n",addr.wp, cmd, cword.w, 
+		debug("fwc addr %p cmd %x %4.4x 16bit x %d bit\n",addr.wp, cmd, cword.w,
 		       info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
 		*addr.wp = cword.w;
 		break;
 	case FLASH_CFI_32BIT:
-		debug("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n",addr.lp, cmd, cword.l, 
+		debug("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n",addr.lp, cmd, cword.l,
 		       info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
 		*addr.lp = cword.l;
 		break;
 	case FLASH_CFI_64BIT:
 #ifdef DEBUG
-	        { 
+	        {
 			char str[20];
 			print_longlong(str, cword.ll);
-	
-			printf("fwc addr %p cmd %x %s 64 bit x %d bit\n",addr.llp, cmd, str, 
+
+			printf("fwc addr %p cmd %x %s 64 bit x %d bit\n",addr.llp, cmd, str,
 			       info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
 		}
 #endif
@@ -685,7 +685,7 @@
 		retval = (cptr.lp[0] == cword.l);
 		break;
 	case FLASH_CFI_64BIT:
-#ifdef DEBUG		
+#ifdef DEBUG
 	        {
 			char str1[20];
 			char str2[20];
  
@@ -776,14 +776,14 @@
 			info->chipwidth >>= 1) { */
 		for(info->chipwidth =FLASH_CFI_BY8;
 		    info->chipwidth <= info->portwidth;
-		    info->chipwidth <<= 1) { 
+		    info->chipwidth <<= 1) {
 			flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
 			flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
 			if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
 			   flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
 			   flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
 				debug("found port %d chip %d ", info->portwidth, info->chipwidth);
-				debug("port %d bits chip %d bits\n", info->portwidth << CFI_FLASH_SHIFT_WIDTH, 
+				debug("port %d bits chip %d bits\n", info->portwidth << CFI_FLASH_SHIFT_WIDTH,
 				       info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
 				return 1;
 			}
  
@@ -823,11 +823,11 @@
 			info->cmd_reset = AMD_CMD_RESET;
 			break;
 		}
-			
+
 		debug("manufacturer is %d\n", info->vendor);
 		size_ratio = info->portwidth / info->chipwidth;
 		num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
-		debug("size_ration %d port %d bits chip %d bits\n", size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH, 
+		debug("size_ration %d port %d bits chip %d bits\n", size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
 			       info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
 		debug("found %d erase regions\n", num_erase_regions);
 		sect_cnt = 0;
@@ -296,11 +296,11 @@
 		pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_io);
  
 		DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
-		
+
 		/* TBS: Passing in current_busno allows for sibling P2P bridges */
 		pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
-		/* 
-		 * TBS: need to figure out if this is a subordinate bridge on the bus 
+		/*
+		 * TBS: need to figure out if this is a subordinate bridge on the bus
 		 * to be able to properly set the pri/sec/sub bridge registers.
 		 */
 		n = pci_hose_scan_bus(hose, hose->current_busno);
@@ -84,7 +84,7 @@
 		"cp.b 80400000 BFC60000 $(filesize)\0"			\
 	"initenv=erase bfc40000 bfc5ffff\0"				\
 	""
-//#define CONFIG_BOOTCOMMAND	"run flash_local"
+/*#define CONFIG_BOOTCOMMAND	"run flash_local" */
 #define CONFIG_BOOTCOMMAND	"run netboot"
  
 #define CONFIG_COMMANDS		(CONFIG_CMD_DFL | \
@@ -43,7 +43,7 @@
  
 #define FATBUFBLOCKS	6
 #define FATBUFSIZE	(FS_BLOCK_SIZE*FATBUFBLOCKS)
-#define FAT12BUFSIZE	((FATBUFSIZE*3)/2)
+#define FAT12BUFSIZE	((FATBUFSIZE*2)/3)
 #define FAT16BUFSIZE	(FATBUFSIZE/2)
 #define FAT32BUFSIZE	(FATBUFSIZE/4)
  
@@ -176,7 +176,7 @@
 	__u16	fat_sect;	/* Starting sector of the FAT */
 	__u16	rootdir_sect;	/* Start sector of root directory */
 	__u16	clust_size;	/* Size of clusters in sectors */
-	__u16	data_begin;	/* The sector of the first cluster */
+	short	data_begin;	/* The sector of the first cluster, can be negative */
 	__u8	fatbuf[FATBUFSIZE]; /* Current FAT buffer */
 	int	fatbufnum;	/* Used by get_fatent, init to -1 */
 } fsdata;
@@ -74,10 +74,6 @@
 static unsigned char rtc_read (unsigned char reg);
 static void rtc_write (unsigned char reg, unsigned char val);
  
-
-
-
-
 /* ************************************************************************* */
 #ifdef CONFIG_SXNI855T		/* !!! SHOULD BE CHANGED TO NEW CODE !!! */
  
@@ -305,10 +301,6 @@
  
 #else  /* not CONFIG_SXNI855T */
 /* ************************************************************************* */
-
-
-
-
  
 /* read clock time from DS1306 and return it in *tmp */
 void rtc_get (struct rtc_time *tmp)
...	...	@@ -2,6 +2,10 @@
2	2	Changes since U-Boot 1.0.1:
3	3	======================================================================
4	4
	5	+* Patch by Jian Zhang, 3 Feb 2004:
	6	+ - Changed the incorrect FAT12BUFSIZE
	7	+ - data_begin in fsdata can be negative. Changed it to be short.
	8	+
5	9	* Patches by Stephan Linz, 30 Jan 2004:
6	10	1: - board/altera/common/flash.c:flash_erase():
7	11	o allow interrupts befor get_timer() call
...	...	@@ -113,7 +113,7 @@
113	113
114	114	memctl->memc_mptpr = 0x0200; /* divide by 32 */
115	115
116		- memctl->memc_mamr = 0x18003112; /CFG_MAMR_8COL; //* 0x18005112 TODO: explain here */
	116	+ memctl->memc_mamr = 0x18003112; /CFG_MAMR_8COL; / /* 0x18005112 TODO: explain here */
117	117
118	118	upmconfig (UPMA, (uint *) sdram_table,
119	119	sizeof (sdram_table) / sizeof (uint));
...	...	@@ -19,7 +19,7 @@
19	19	*
20	20	* This program is distributed in the hope that it will be useful,
21	21	* but WITHOUT ANY WARRANTY; without even the implied warranty of
22		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23	23	* GNU General Public License for more details.
24	24	*
25	25	* You should have received a copy of the GNU General Public License
...	...	@@ -32,7 +32,7 @@
32	32	#include <linux/byteorder/swab.h>
33	33
34	34	#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */
35		-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
	35	+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
36	36
37	37	/* Board support for 1 or 2 flash devices */
38	38	#undef FLASH_PORT_WIDTH32
...	...	@@ -120,13 +120,13 @@
120	120	*/
121	121	flash_unlock(flash_info_t * info)
122	122	{
123		- int j;
124		- for (j=2;j<CFG_MAX_FLASH_SECT;j++){
125		- FPWV addr = (FPWV ) (info->start[j]);
126		- flash_unprotect_sectors (addr);
127		- addr = (FPW) 0x00500050;/ clear status register */
128		- addr = (FPW) 0x00FF00FF;/ resest to read mode */
129		- }
	123	+ int j;
	124	+ for (j=2;j<CFG_MAX_FLASH_SECT;j++){
	125	+ FPWV addr = (FPWV ) (info->start[j]);
	126	+ flash_unprotect_sectors (addr);
	127	+ addr = (FPW) 0x00500050;/ clear status register */
	128	+ addr = (FPW) 0x00FF00FF;/ resest to read mode */
	129	+ }
130	130	}
131	131
132	132	/*-----------------------------------------------------------------------
...	...	@@ -192,7 +192,7 @@
192	192	if ((i % 5) == 0)
193	193	printf ("\n ");
194	194	printf (" %08lX%s",
195		- info->start[i], info->protect[i] ? " (RO)" : " ");
	195	+ info->start[i], info->protect[i] ? " (RO)" : " ");
196	196	}
197	197	printf ("\n");
198	198	return;
199	199
200	200
...	...	@@ -224,18 +224,18 @@
224	224	info->sector_count = 0;
225	225	info->size = 0;
226	226	addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
227		- return (0); /* no or unknown flash */
	227	+ return (0); /* no or unknown flash */
228	228	}
229	229
230	230	mb ();
231		- value = addr[1]; /* device ID */
	231	+ value = addr[1]; /* device ID */
232	232	switch (value) {
233	233
234	234	case (FPW) (INTEL_ID_28F256L18T):
235	235	info->flash_id += FLASH_28F256L18T;
236	236	info->sector_count = 259;
237	237	info->size = 0x02000000;
238		- break; /* => 32 MB */
	238	+ break; /* => 32 MB */
239	239
240	240	default:
241	241	info->flash_id = FLASH_UNKNOWN;
...	...	@@ -318,7 +318,7 @@
318	318
319	319	/* Start erase on unprotected sectors */
320	320	for (sect = s_first; sect <= s_last; sect++) {
321		- if (info->protect[sect] == 0) { /* not protected */
	321	+ if (info->protect[sect] == 0) { /* not protected */
322	322	FPWV addr = (FPWV ) (info->start[sect]);
323	323	FPW status;
324	324
...	...	@@ -348,7 +348,7 @@
348	348	}
349	349	}
350	350
351		- /* clear status register cmd. */
	351	+ /* clear status register cmd. */
352	352	*addr = (FPW) 0x00500050;
353	353	addr = (FPW) 0x00FF00FF;/ resest to read mode */
354	354	printf (" done\n");
...	...	@@ -860,7 +860,7 @@
860	860	}
861	861
862	862	for (info = info_first; info <= info_last; ++info) {
863		- ulong b_end = info->start[0] + info->size;// bank end addr */
	863	+ ulong b_end = info->start[0] + info->size;/ / bank end addr */
864	864	/* short s_end = info->sector_count - 1;
865	865	for (i=0; i<info->sector_count; ++i) {
866	866	ulong e_addr = (i == s_end) ? b_end : info->start[i + 1];
...	...	@@ -872,7 +872,7 @@
872	872	}
873	873	}
874	874
875		-// finally write data to flash */
	875	+/ / finally write data to flash */
876	876	/* for (info = info_first; info <= info_last && cnt>0; ++info) {
877	877	ulong len;
878	878
...	...	@@ -30,11 +30,11 @@
30	30	* Tested Architectures
31	31	* Port Width Chip Width # of banks Flash Chip Board
32	32	* 32 16 1 23F128J3 seranoa/eagle
33		- *
	33	+ *
34	34	*/
35	35
36	36	/* The DEBUG define must be before common to enable debugging */
37		-#undef DEBUG
	37	+#undef DEBUG
38	38	#include <common.h>
39	39	#include <asm/processor.h>
40	40	#ifdef CFG_FLASH_CFI_DRIVER
...	...	@@ -170,8 +170,8 @@
170	170	int i;
171	171	char *cp;
172	172	cp = (unsigned char *)&data;
173		- for(i=0;i<8; i++)
174		- sprintf(&str[i2], "%2.2x", cp++);
	173	+ for(i=0;i<8; i++)
	174	+ sprintf(&str[i2], "%2.2x", cp++);
175	175	}
176	176	#endif
177	177
...	...	@@ -501,7 +501,7 @@
501	501	void flash_read_factory_serial(flash_info_t * info, void * buffer, int offset, int len)
502	502	{
503	503	uchar * src;
504		-
	504	+
505	505	src = flash_make_addr(info, 0, FLASH_OFFSET_INTEL_PROTECTION);
506	506	flash_write_cmd(info,0, 0, FLASH_CMD_READ_ID);
507	507	memcpy(buffer,src + offset,len);
...	...	@@ -510,7 +510,7 @@
510	510
511	511	#endif /* CFG_FLASH_PROTECTION */
512	512
513		-static int flash_poll_status(flash_info_t * info, flash_sect_t sect)
	513	+static int flash_poll_status(flash_info_t * info, flash_sect_t sect)
514	514	{
515	515	int retval;
516	516	switch(info->vendor) {
517	517
518	518
519	519
520	520
...	...	@@ -626,27 +626,27 @@
626	626	flash_make_cmd(info, cmd, &cword);
627	627	switch(info->portwidth) {
628	628	case FLASH_CFI_8BIT:
629		- debug("fwc addr %p cmd %x %x 8bit x %d bit\n",addr.cp, cmd, cword.c,
	629	+ debug("fwc addr %p cmd %x %x 8bit x %d bit\n",addr.cp, cmd, cword.c,
630	630	info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
631	631	*addr.cp = cword.c;
632	632	break;
633	633	case FLASH_CFI_16BIT:
634		- debug("fwc addr %p cmd %x %4.4x 16bit x %d bit\n",addr.wp, cmd, cword.w,
	634	+ debug("fwc addr %p cmd %x %4.4x 16bit x %d bit\n",addr.wp, cmd, cword.w,
635	635	info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
636	636	*addr.wp = cword.w;
637	637	break;
638	638	case FLASH_CFI_32BIT:
639		- debug("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n",addr.lp, cmd, cword.l,
	639	+ debug("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n",addr.lp, cmd, cword.l,
640	640	info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
641	641	*addr.lp = cword.l;
642	642	break;
643	643	case FLASH_CFI_64BIT:
644	644	#ifdef DEBUG
645		- {
	645	+ {
646	646	char str[20];
647	647	print_longlong(str, cword.ll);
648		-
649		- printf("fwc addr %p cmd %x %s 64 bit x %d bit\n",addr.llp, cmd, str,
	648	+
	649	+ printf("fwc addr %p cmd %x %s 64 bit x %d bit\n",addr.llp, cmd, str,
650	650	info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
651	651	}
652	652	#endif
...	...	@@ -685,7 +685,7 @@
685	685	retval = (cptr.lp[0] == cword.l);
686	686	break;
687	687	case FLASH_CFI_64BIT:
688		-#ifdef DEBUG
	688	+#ifdef DEBUG
689	689	{
690	690	char str1[20];
691	691	char str2[20];
692	692
...	...	@@ -776,14 +776,14 @@
776	776	info->chipwidth >>= 1) { */
777	777	for(info->chipwidth =FLASH_CFI_BY8;
778	778	info->chipwidth <= info->portwidth;
779		- info->chipwidth <<= 1) {
	779	+ info->chipwidth <<= 1) {
780	780	flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
781	781	flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
782	782	if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
783	783	flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
784	784	flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
785	785	debug("found port %d chip %d ", info->portwidth, info->chipwidth);
786		- debug("port %d bits chip %d bits\n", info->portwidth << CFI_FLASH_SHIFT_WIDTH,
	786	+ debug("port %d bits chip %d bits\n", info->portwidth << CFI_FLASH_SHIFT_WIDTH,
787	787	info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
788	788	return 1;
789	789	}
790	790
...	...	@@ -823,11 +823,11 @@
823	823	info->cmd_reset = AMD_CMD_RESET;
824	824	break;
825	825	}
826		-
	826	+
827	827	debug("manufacturer is %d\n", info->vendor);
828	828	size_ratio = info->portwidth / info->chipwidth;
829	829	num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
830		- debug("size_ration %d port %d bits chip %d bits\n", size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
	830	+ debug("size_ration %d port %d bits chip %d bits\n", size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
831	831	info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
832	832	debug("found %d erase regions\n", num_erase_regions);
833	833	sect_cnt = 0;
...	...	@@ -296,11 +296,11 @@
296	296	pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_io);
297	297
298	298	DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
299		-
	299	+
300	300	/* TBS: Passing in current_busno allows for sibling P2P bridges */
301	301	pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
302		- /*
303		- * TBS: need to figure out if this is a subordinate bridge on the bus
	302	+ /*
	303	+ * TBS: need to figure out if this is a subordinate bridge on the bus
304	304	* to be able to properly set the pri/sec/sub bridge registers.
305	305	*/
306	306	n = pci_hose_scan_bus(hose, hose->current_busno);
...	...	@@ -84,7 +84,7 @@
84	84	"cp.b 80400000 BFC60000 $(filesize)\0" \
85	85	"initenv=erase bfc40000 bfc5ffff\0" \
86	86	""
87		-//#define CONFIG_BOOTCOMMAND "run flash_local"
	87	+/#define CONFIG_BOOTCOMMAND "run flash_local" /
88	88	#define CONFIG_BOOTCOMMAND "run netboot"
89	89
90	90	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
...	...	@@ -43,7 +43,7 @@
43	43
44	44	#define FATBUFBLOCKS 6
45	45	#define FATBUFSIZE (FS_BLOCK_SIZE*FATBUFBLOCKS)
46		-#define FAT12BUFSIZE ((FATBUFSIZE*3)/2)
	46	+#define FAT12BUFSIZE ((FATBUFSIZE*2)/3)
47	47	#define FAT16BUFSIZE (FATBUFSIZE/2)
48	48	#define FAT32BUFSIZE (FATBUFSIZE/4)
49	49
...	...	@@ -176,7 +176,7 @@
176	176	__u16 fat_sect; /* Starting sector of the FAT */
177	177	__u16 rootdir_sect; /* Start sector of root directory */
178	178	__u16 clust_size; /* Size of clusters in sectors */
179		- __u16 data_begin; /* The sector of the first cluster */
	179	+ short data_begin; /* The sector of the first cluster, can be negative */
180	180	__u8 fatbuf[FATBUFSIZE]; /* Current FAT buffer */
181	181	int fatbufnum; /* Used by get_fatent, init to -1 */
182	182	} fsdata;
...	...	@@ -74,10 +74,6 @@
74	74	static unsigned char rtc_read (unsigned char reg);
75	75	static void rtc_write (unsigned char reg, unsigned char val);
76	76
77		-
78		-
79		-
80		-
81	77	/* ************************************************************************* */
82	78	#ifdef CONFIG_SXNI855T /* !!! SHOULD BE CHANGED TO NEW CODE !!! */
83	79
...	...	@@ -305,10 +301,6 @@
305	301
306	302	#else /* not CONFIG_SXNI855T */
307	303	/* ************************************************************************* */
308		-
309		-
310		-
311		-
312	304
313	305	/* read clock time from DS1306 and return it in tmp /
314	306	void rtc_get (struct rtc_time *tmp)