Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit cd7efc2a947b30a2047b248f66ddfa8b182fda64

Authored by Stephen Warren
Committed by Tom Warren
1 parent cc07294bc7
Exists in v2017.01-smarct4x and in 48 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ARM: tegra: move CONFIG_TEGRAnn 

<asm/arch-tegra/tegra.h> needs to use CONFIG_TEGRA* to conditionalize
some definitions, since some modules moved between generations. Move
the definition of CONFIG_TEGRAnn to a header that's included earlier,
so that it's set by the time tegra.h needs to use it.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

Showing 8 changed files with 8 additions and 20 deletions Inline Diff

arch/arm/include/asm/arch-tegra114/tegra.h
Diff comments   View file @ cd7efc2
1 /* 1 /*
2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation. 6 * version 2, as published by the Free Software Foundation.
7 * 7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT 8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details. 11 * more details.
12 * 12 *
13 * You should have received a copy of the GNU General Public License 13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */ 15 */
16 16
17 #ifndef _TEGRA114_H_ 17 #ifndef _TEGRA114_H_
18 #define _TEGRA114_H_ 18 #define _TEGRA114_H_
19 19
20 #define CONFIG_TEGRA114
21
20 #define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */ 22 #define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */
21 #define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ 23 #define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
22 24
23 #include <asm/arch-tegra/tegra.h> 25 #include <asm/arch-tegra/tegra.h>
24 26
25 #define BCT_ODMDATA_OFFSET 1752 /* offset to ODMDATA word */ 27 #define BCT_ODMDATA_OFFSET 1752 /* offset to ODMDATA word */
26 28
27 #undef NVBOOTINFOTABLE_BCTSIZE 29 #undef NVBOOTINFOTABLE_BCTSIZE
28 #undef NVBOOTINFOTABLE_BCTPTR 30 #undef NVBOOTINFOTABLE_BCTPTR
29 #define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */ 31 #define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */
30 #define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */ 32 #define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */
31 33
32 #define MAX_NUM_CPU 4 34 #define MAX_NUM_CPU 4
33 35
34 #endif /* TEGRA114_H */ 36 #endif /* TEGRA114_H */
35 37
arch/arm/include/asm/arch-tegra124/tegra.h
Diff comments   View file @ cd7efc2
1 /* 1 /*
2 * (C) Copyright 2013 2 * (C) Copyright 2013
3 * NVIDIA Corporation <www.nvidia.com> 3 * NVIDIA Corporation <www.nvidia.com>
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #ifndef _TEGRA124_H_ 8 #ifndef _TEGRA124_H_
9 #define _TEGRA124_H_ 9 #define _TEGRA124_H_
10 10
11 #define CONFIG_TEGRA124
12
11 #define NV_PA_SDRAM_BASE 0x80000000 13 #define NV_PA_SDRAM_BASE 0x80000000
12 #define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ 14 #define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
13 #define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */ 15 #define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */
14 #define NV_PA_AHB_BASE 0x6000C000 /* System regs (AHB, etc.) */ 16 #define NV_PA_AHB_BASE 0x6000C000 /* System regs (AHB, etc.) */
15 17
16 #include <asm/arch-tegra/tegra.h> 18 #include <asm/arch-tegra/tegra.h>
17 19
18 #define BCT_ODMDATA_OFFSET 1704 /* offset to ODMDATA word */ 20 #define BCT_ODMDATA_OFFSET 1704 /* offset to ODMDATA word */
19 21
20 #undef NVBOOTINFOTABLE_BCTSIZE 22 #undef NVBOOTINFOTABLE_BCTSIZE
21 #undef NVBOOTINFOTABLE_BCTPTR 23 #undef NVBOOTINFOTABLE_BCTPTR
22 #define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */ 24 #define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */
23 #define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */ 25 #define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */
24 26
25 #define MAX_NUM_CPU 4 27 #define MAX_NUM_CPU 4
26 #define MCB_EMEM_ARB_OVERRIDE (NV_PA_MC_BASE + 0xE8) 28 #define MCB_EMEM_ARB_OVERRIDE (NV_PA_MC_BASE + 0xE8)
27 29
28 #define TEGRA_USB1_BASE 0x7D000000 30 #define TEGRA_USB1_BASE 0x7D000000
29 31
30 #endif /* _TEGRA124_H_ */ 32 #endif /* _TEGRA124_H_ */
31 33
arch/arm/include/asm/arch-tegra20/tegra.h
Diff comments   View file @ cd7efc2
1 /* 1 /*
2 * (C) Copyright 2010,2011 2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com> 3 * NVIDIA Corporation <www.nvidia.com>
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #ifndef _TEGRA20_H_ 8 #ifndef _TEGRA20_H_
9 #define _TEGRA20_H_ 9 #define _TEGRA20_H_
10 10
11 #define CONFIG_TEGRA20
12
11 #define NV_PA_SDRAM_BASE 0x00000000 13 #define NV_PA_SDRAM_BASE 0x00000000
12 14
13 #include <asm/arch-tegra/tegra.h> 15 #include <asm/arch-tegra/tegra.h>
14 16
15 #define TEGRA_USB1_BASE 0xC5000000 17 #define TEGRA_USB1_BASE 0xC5000000
16 18
17 #define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */ 19 #define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */
18 20
19 #define MAX_NUM_CPU 2 21 #define MAX_NUM_CPU 2
20 22
21 #endif /* TEGRA20_H */ 23 #endif /* TEGRA20_H */
22 24
arch/arm/include/asm/arch-tegra30/tegra.h
Diff comments   View file @ cd7efc2
1 /* 1 /*
2 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation. 6 * version 2, as published by the Free Software Foundation.
7 * 7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT 8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details. 11 * more details.
12 * 12 *
13 * You should have received a copy of the GNU General Public License 13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */ 15 */
16 16
17 #ifndef _TEGRA30_H_ 17 #ifndef _TEGRA30_H_
18 #define _TEGRA30_H_ 18 #define _TEGRA30_H_
19 19
20 #define CONFIG_TEGRA30
21
20 #define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */ 22 #define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */
21 23
22 #include <asm/arch-tegra/tegra.h> 24 #include <asm/arch-tegra/tegra.h>
23 25
24 #define TEGRA_USB1_BASE 0x7D000000 26 #define TEGRA_USB1_BASE 0x7D000000
25 27
26 #define BCT_ODMDATA_OFFSET 6116 /* 12 bytes from end of BCT */ 28 #define BCT_ODMDATA_OFFSET 6116 /* 12 bytes from end of BCT */
27 29
28 #define MAX_NUM_CPU 4 30 #define MAX_NUM_CPU 4
29 31
30 #endif /* TEGRA30_H */ 32 #endif /* TEGRA30_H */
31 33
include/configs/tegra114-common.h
Diff comments   View file @ cd7efc2
1 /* 1 /*
2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation. 6 * version 2, as published by the Free Software Foundation.
7 * 7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT 8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details. 11 * more details.
12 * 12 *
13 * You should have received a copy of the GNU General Public License 13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */ 15 */
16 16
17 #ifndef _TEGRA114_COMMON_H_ 17 #ifndef _TEGRA114_COMMON_H_
18 #define _TEGRA114_COMMON_H_ 18 #define _TEGRA114_COMMON_H_
19 #include "tegra-common.h" 19 #include "tegra-common.h"
20 20
21 /* Cortex-A15 uses a cache line size of 64 bytes */ 21 /* Cortex-A15 uses a cache line size of 64 bytes */
22 #define CONFIG_SYS_CACHELINE_SIZE 64 22 #define CONFIG_SYS_CACHELINE_SIZE 64
23 23
24 /* 24 /*
25 * NS16550 Configuration 25 * NS16550 Configuration
26 */ 26 */
27 #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ 27 #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
28 28
29 /*
30 * High Level Configuration Options
31 */
32 #define CONFIG_TEGRA114 /* in a NVidia Tegra114 core */
33
34 /* Environment information, boards can override if required */ 29 /* Environment information, boards can override if required */
35 #define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */ 30 #define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
36 31
37 /* 32 /*
38 * Miscellaneous configurable options 33 * Miscellaneous configurable options
39 */ 34 */
40 #define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */ 35 #define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */
41 #define CONFIG_STACKBASE 0x82800000 /* 40MB */ 36 #define CONFIG_STACKBASE 0x82800000 /* 40MB */
42 37
43 /*----------------------------------------------------------------------- 38 /*-----------------------------------------------------------------------
44 * Physical Memory Map 39 * Physical Memory Map
45 */ 40 */
46 #define CONFIG_SYS_TEXT_BASE 0x8010E000 41 #define CONFIG_SYS_TEXT_BASE 0x8010E000
47 42
48 /* 43 /*
49 * Memory layout for where various images get loaded by boot scripts: 44 * Memory layout for where various images get loaded by boot scripts:
50 * 45 *
51 * scriptaddr can be pretty much anywhere that doesn't conflict with something 46 * scriptaddr can be pretty much anywhere that doesn't conflict with something
52 * else. Put it above BOOTMAPSZ to eliminate conflicts. 47 * else. Put it above BOOTMAPSZ to eliminate conflicts.
53 * 48 *
54 * kernel_addr_r must be within the first 128M of RAM in order for the 49 * kernel_addr_r must be within the first 128M of RAM in order for the
55 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will 50 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
56 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r 51 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
57 * should not overlap that area, or the kernel will have to copy itself 52 * should not overlap that area, or the kernel will have to copy itself
58 * somewhere else before decompression. Similarly, the address of any other 53 * somewhere else before decompression. Similarly, the address of any other
59 * data passed to the kernel shouldn't overlap the start of RAM. Pushing 54 * data passed to the kernel shouldn't overlap the start of RAM. Pushing
60 * this up to 16M allows for a sizable kernel to be decompressed below the 55 * this up to 16M allows for a sizable kernel to be decompressed below the
61 * compressed load address. 56 * compressed load address.
62 * 57 *
63 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for 58 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
64 * the compressed kernel to be up to 16M too. 59 * the compressed kernel to be up to 16M too.
65 * 60 *
66 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows 61 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
67 * for the FDT/DTB to be up to 1M, which is hopefully plenty. 62 * for the FDT/DTB to be up to 1M, which is hopefully plenty.
68 */ 63 */
69 #define MEM_LAYOUT_ENV_SETTINGS \ 64 #define MEM_LAYOUT_ENV_SETTINGS \
70 "scriptaddr=0x90000000\0" \ 65 "scriptaddr=0x90000000\0" \
71 "kernel_addr_r=0x81000000\0" \ 66 "kernel_addr_r=0x81000000\0" \
72 "fdt_addr_r=0x82000000\0" \ 67 "fdt_addr_r=0x82000000\0" \
73 "ramdisk_addr_r=0x82100000\0" 68 "ramdisk_addr_r=0x82100000\0"
74 69
75 /* Defines for SPL */ 70 /* Defines for SPL */
76 #define CONFIG_SPL_TEXT_BASE 0x80108000 71 #define CONFIG_SPL_TEXT_BASE 0x80108000
77 #define CONFIG_SYS_SPL_MALLOC_START 0x80090000 72 #define CONFIG_SYS_SPL_MALLOC_START 0x80090000
78 #define CONFIG_SPL_STACK 0x800ffffc 73 #define CONFIG_SPL_STACK 0x800ffffc
79 74
80 /* Total I2C ports on Tegra114 */ 75 /* Total I2C ports on Tegra114 */
81 #define TEGRA_I2C_NUM_CONTROLLERS 5 76 #define TEGRA_I2C_NUM_CONTROLLERS 5
82 77
83 /* For USB EHCI controller */ 78 /* For USB EHCI controller */
84 #define CONFIG_EHCI_IS_TDI 79 #define CONFIG_EHCI_IS_TDI
85 #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 80 #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
86 81
87 #endif /* _TEGRA114_COMMON_H_ */ 82 #endif /* _TEGRA114_COMMON_H_ */
88 83
include/configs/tegra124-common.h
Diff comments   View file @ cd7efc2
1 /* 1 /*
2 * (C) Copyright 2013 2 * (C) Copyright 2013
3 * NVIDIA Corporation <www.nvidia.com> 3 * NVIDIA Corporation <www.nvidia.com>
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #ifndef _TEGRA124_COMMON_H_ 8 #ifndef _TEGRA124_COMMON_H_
9 #define _TEGRA124_COMMON_H_ 9 #define _TEGRA124_COMMON_H_
10 10
11 #include "tegra-common.h" 11 #include "tegra-common.h"
12 12
13 /* Cortex-A15 uses a cache line size of 64 bytes */ 13 /* Cortex-A15 uses a cache line size of 64 bytes */
14 #define CONFIG_SYS_CACHELINE_SIZE 64 14 #define CONFIG_SYS_CACHELINE_SIZE 64
15 15
16 /* 16 /*
17 * NS16550 Configuration 17 * NS16550 Configuration
18 */ 18 */
19 #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ 19 #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
20 20
21 /*
22 * High Level Configuration Options
23 */
24 #define CONFIG_TEGRA124 /* is an NVIDIA Tegra124 core */
25
26 /* Environment information, boards can override if required */ 21 /* Environment information, boards can override if required */
27 #define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */ 22 #define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
28 23
29 /* 24 /*
30 * Miscellaneous configurable options 25 * Miscellaneous configurable options
31 */ 26 */
32 #define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */ 27 #define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */
33 #define CONFIG_STACKBASE 0x82800000 /* 40MB */ 28 #define CONFIG_STACKBASE 0x82800000 /* 40MB */
34 29
35 /*----------------------------------------------------------------------- 30 /*-----------------------------------------------------------------------
36 * Physical Memory Map 31 * Physical Memory Map
37 */ 32 */
38 #define CONFIG_SYS_TEXT_BASE 0x8010E000 33 #define CONFIG_SYS_TEXT_BASE 0x8010E000
39 34
40 /* 35 /*
41 * Memory layout for where various images get loaded by boot scripts: 36 * Memory layout for where various images get loaded by boot scripts:
42 * 37 *
43 * scriptaddr can be pretty much anywhere that doesn't conflict with something 38 * scriptaddr can be pretty much anywhere that doesn't conflict with something
44 * else. Put it above BOOTMAPSZ to eliminate conflicts. 39 * else. Put it above BOOTMAPSZ to eliminate conflicts.
45 * 40 *
46 * pxefile_addr_r can be pretty much anywhere that doesn't conflict with 41 * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
47 * something else. Put it above BOOTMAPSZ to eliminate conflicts. 42 * something else. Put it above BOOTMAPSZ to eliminate conflicts.
48 * 43 *
49 * kernel_addr_r must be within the first 128M of RAM in order for the 44 * kernel_addr_r must be within the first 128M of RAM in order for the
50 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will 45 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
51 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r 46 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
52 * should not overlap that area, or the kernel will have to copy itself 47 * should not overlap that area, or the kernel will have to copy itself
53 * somewhere else before decompression. Similarly, the address of any other 48 * somewhere else before decompression. Similarly, the address of any other
54 * data passed to the kernel shouldn't overlap the start of RAM. Pushing 49 * data passed to the kernel shouldn't overlap the start of RAM. Pushing
55 * this up to 16M allows for a sizable kernel to be decompressed below the 50 * this up to 16M allows for a sizable kernel to be decompressed below the
56 * compressed load address. 51 * compressed load address.
57 * 52 *
58 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for 53 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
59 * the compressed kernel to be up to 16M too. 54 * the compressed kernel to be up to 16M too.
60 * 55 *
61 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows 56 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
62 * for the FDT/DTB to be up to 1M, which is hopefully plenty. 57 * for the FDT/DTB to be up to 1M, which is hopefully plenty.
63 */ 58 */
64 #define MEM_LAYOUT_ENV_SETTINGS \ 59 #define MEM_LAYOUT_ENV_SETTINGS \
65 "scriptaddr=0x90000000\0" \ 60 "scriptaddr=0x90000000\0" \
66 "pxefile_addr_r=0x90100000\0" \ 61 "pxefile_addr_r=0x90100000\0" \
67 "kernel_addr_r=0x81000000\0" \ 62 "kernel_addr_r=0x81000000\0" \
68 "fdt_addr_r=0x82000000\0" \ 63 "fdt_addr_r=0x82000000\0" \
69 "ramdisk_addr_r=0x82100000\0" 64 "ramdisk_addr_r=0x82100000\0"
70 65
71 /* Defines for SPL */ 66 /* Defines for SPL */
72 #define CONFIG_SPL_TEXT_BASE 0x80108000 67 #define CONFIG_SPL_TEXT_BASE 0x80108000
73 #define CONFIG_SYS_SPL_MALLOC_START 0x80090000 68 #define CONFIG_SYS_SPL_MALLOC_START 0x80090000
74 #define CONFIG_SPL_STACK 0x800ffffc 69 #define CONFIG_SPL_STACK 0x800ffffc
75 70
76 /* Total I2C ports on Tegra124 */ 71 /* Total I2C ports on Tegra124 */
77 #define TEGRA_I2C_NUM_CONTROLLERS 5 72 #define TEGRA_I2C_NUM_CONTROLLERS 5
78 73
79 /* For USB EHCI controller */ 74 /* For USB EHCI controller */
80 #define CONFIG_EHCI_IS_TDI 75 #define CONFIG_EHCI_IS_TDI
81 #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 76 #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
82 77
83 #endif /* _TEGRA124_COMMON_H_ */ 78 #endif /* _TEGRA124_COMMON_H_ */
84 79
include/configs/tegra20-common.h
Diff comments   View file @ cd7efc2
1 /* 1 /*
2 * (C) Copyright 2010-2012 2 * (C) Copyright 2010-2012
3 * NVIDIA Corporation <www.nvidia.com> 3 * NVIDIA Corporation <www.nvidia.com>
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #ifndef _TEGRA20_COMMON_H_ 8 #ifndef _TEGRA20_COMMON_H_
9 #define _TEGRA20_COMMON_H_ 9 #define _TEGRA20_COMMON_H_
10 #include "tegra-common.h" 10 #include "tegra-common.h"
11 11
12 /* Cortex-A9 uses a cache line size of 32 bytes */ 12 /* Cortex-A9 uses a cache line size of 32 bytes */
13 #define CONFIG_SYS_CACHELINE_SIZE 32 13 #define CONFIG_SYS_CACHELINE_SIZE 32
14 14
15 /* 15 /*
16 * Errata configuration 16 * Errata configuration
17 */ 17 */
18 #define CONFIG_ARM_ERRATA_716044 18 #define CONFIG_ARM_ERRATA_716044
19 #define CONFIG_ARM_ERRATA_742230 19 #define CONFIG_ARM_ERRATA_742230
20 #define CONFIG_ARM_ERRATA_751472 20 #define CONFIG_ARM_ERRATA_751472
21 21
22 /* 22 /*
23 * NS16550 Configuration 23 * NS16550 Configuration
24 */ 24 */
25 #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */ 25 #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
26 26
27 /*
28 * High Level Configuration Options
29 */
30 #define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */
31
32 /* Environment information, boards can override if required */ 27 /* Environment information, boards can override if required */
33 #define CONFIG_LOADADDR 0x00408000 /* def. location for kernel */ 28 #define CONFIG_LOADADDR 0x00408000 /* def. location for kernel */
34 29
35 /* 30 /*
36 * Miscellaneous configurable options 31 * Miscellaneous configurable options
37 */ 32 */
38 #define CONFIG_SYS_LOAD_ADDR 0x00A00800 /* default */ 33 #define CONFIG_SYS_LOAD_ADDR 0x00A00800 /* default */
39 #define CONFIG_STACKBASE 0x02800000 /* 40MB */ 34 #define CONFIG_STACKBASE 0x02800000 /* 40MB */
40 35
41 /*----------------------------------------------------------------------- 36 /*-----------------------------------------------------------------------
42 * Physical Memory Map 37 * Physical Memory Map
43 */ 38 */
44 #define CONFIG_SYS_TEXT_BASE 0x0010E000 39 #define CONFIG_SYS_TEXT_BASE 0x0010E000
45 40
46 /* 41 /*
47 * Memory layout for where various images get loaded by boot scripts: 42 * Memory layout for where various images get loaded by boot scripts:
48 * 43 *
49 * scriptaddr can be pretty much anywhere that doesn't conflict with something 44 * scriptaddr can be pretty much anywhere that doesn't conflict with something
50 * else. Put it above BOOTMAPSZ to eliminate conflicts. 45 * else. Put it above BOOTMAPSZ to eliminate conflicts.
51 * 46 *
52 * kernel_addr_r must be within the first 128M of RAM in order for the 47 * kernel_addr_r must be within the first 128M of RAM in order for the
53 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will 48 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
54 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r 49 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
55 * should not overlap that area, or the kernel will have to copy itself 50 * should not overlap that area, or the kernel will have to copy itself
56 * somewhere else before decompression. Similarly, the address of any other 51 * somewhere else before decompression. Similarly, the address of any other
57 * data passed to the kernel shouldn't overlap the start of RAM. Pushing 52 * data passed to the kernel shouldn't overlap the start of RAM. Pushing
58 * this up to 16M allows for a sizable kernel to be decompressed below the 53 * this up to 16M allows for a sizable kernel to be decompressed below the
59 * compressed load address. 54 * compressed load address.
60 * 55 *
61 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for 56 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
62 * the compressed kernel to be up to 16M too. 57 * the compressed kernel to be up to 16M too.
63 * 58 *
64 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows 59 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
65 * for the FDT/DTB to be up to 1M, which is hopefully plenty. 60 * for the FDT/DTB to be up to 1M, which is hopefully plenty.
66 */ 61 */
67 #define MEM_LAYOUT_ENV_SETTINGS \ 62 #define MEM_LAYOUT_ENV_SETTINGS \
68 "scriptaddr=0x10000000\0" \ 63 "scriptaddr=0x10000000\0" \
69 "kernel_addr_r=0x01000000\0" \ 64 "kernel_addr_r=0x01000000\0" \
70 "fdt_addr_r=0x02000000\0" \ 65 "fdt_addr_r=0x02000000\0" \
71 "ramdisk_addr_r=0x02100000\0" 66 "ramdisk_addr_r=0x02100000\0"
72 67
73 /* Defines for SPL */ 68 /* Defines for SPL */
74 #define CONFIG_SPL_TEXT_BASE 0x00108000 69 #define CONFIG_SPL_TEXT_BASE 0x00108000
75 #define CONFIG_SYS_SPL_MALLOC_START 0x00090000 70 #define CONFIG_SYS_SPL_MALLOC_START 0x00090000
76 #define CONFIG_SPL_STACK 0x000ffffc 71 #define CONFIG_SPL_STACK 0x000ffffc
77 72
78 /* Align LCD to 1MB boundary */ 73 /* Align LCD to 1MB boundary */
79 #define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE 74 #define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
80 75
81 #ifdef CONFIG_TEGRA_LP0 76 #ifdef CONFIG_TEGRA_LP0
82 #define TEGRA_LP0_ADDR 0x1C406000 77 #define TEGRA_LP0_ADDR 0x1C406000
83 #define TEGRA_LP0_SIZE 0x2000 78 #define TEGRA_LP0_SIZE 0x2000
84 #define TEGRA_LP0_VEC \ 79 #define TEGRA_LP0_VEC \
85 "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \ 80 "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \
86 "@" __stringify(TEGRA_LP0_ADDR) " " 81 "@" __stringify(TEGRA_LP0_ADDR) " "
87 #else 82 #else
88 #define TEGRA_LP0_VEC 83 #define TEGRA_LP0_VEC
89 #endif 84 #endif
90 85
91 /* 86 /*
92 * This parameter affects a TXFILLTUNING field that controls how much data is 87 * This parameter affects a TXFILLTUNING field that controls how much data is
93 * sent to the latency fifo before it is sent to the wire. Without this 88 * sent to the latency fifo before it is sent to the wire. Without this
94 * parameter, the default (2) causes occasional Data Buffer Errors in OUT 89 * parameter, the default (2) causes occasional Data Buffer Errors in OUT
95 * packets depending on the buffer address and size. 90 * packets depending on the buffer address and size.
96 */ 91 */
97 #define CONFIG_USB_EHCI_TXFIFO_THRESH 10 92 #define CONFIG_USB_EHCI_TXFIFO_THRESH 10
98 #define CONFIG_EHCI_IS_TDI 93 #define CONFIG_EHCI_IS_TDI
99 94
100 /* Total I2C ports on Tegra20 */ 95 /* Total I2C ports on Tegra20 */
101 #define TEGRA_I2C_NUM_CONTROLLERS 4 96 #define TEGRA_I2C_NUM_CONTROLLERS 4
102 97
103 #define CONFIG_SYS_NAND_SELF_INIT 98 #define CONFIG_SYS_NAND_SELF_INIT
104 #define CONFIG_SYS_NAND_ONFI_DETECTION 99 #define CONFIG_SYS_NAND_ONFI_DETECTION
105 100
106 #endif /* _TEGRA20_COMMON_H_ */ 101 #endif /* _TEGRA20_COMMON_H_ */
107 102
include/configs/tegra30-common.h
Diff comments   View file @ cd7efc2
1 /* 1 /*
2 * (C) Copyright 2010-2012 2 * (C) Copyright 2010-2012
3 * NVIDIA Corporation <www.nvidia.com> 3 * NVIDIA Corporation <www.nvidia.com>
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #ifndef _TEGRA30_COMMON_H_ 8 #ifndef _TEGRA30_COMMON_H_
9 #define _TEGRA30_COMMON_H_ 9 #define _TEGRA30_COMMON_H_
10 #include "tegra-common.h" 10 #include "tegra-common.h"
11 11
12 /* Cortex-A9 uses a cache line size of 32 bytes */ 12 /* Cortex-A9 uses a cache line size of 32 bytes */
13 #define CONFIG_SYS_CACHELINE_SIZE 32 13 #define CONFIG_SYS_CACHELINE_SIZE 32
14 14
15 /* 15 /*
16 * Errata configuration 16 * Errata configuration
17 */ 17 */
18 #define CONFIG_ARM_ERRATA_743622 18 #define CONFIG_ARM_ERRATA_743622
19 #define CONFIG_ARM_ERRATA_751472 19 #define CONFIG_ARM_ERRATA_751472
20 20
21 /* 21 /*
22 * NS16550 Configuration 22 * NS16550 Configuration
23 */ 23 */
24 #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ 24 #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
25 25
26 /*
27 * High Level Configuration Options
28 */
29 #define CONFIG_TEGRA30 /* in a NVidia Tegra30 core */
30
31 /* Environment information, boards can override if required */ 26 /* Environment information, boards can override if required */
32 #define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */ 27 #define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
33 28
34 /* 29 /*
35 * Miscellaneous configurable options 30 * Miscellaneous configurable options
36 */ 31 */
37 #define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */ 32 #define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */
38 #define CONFIG_STACKBASE 0x82800000 /* 40MB */ 33 #define CONFIG_STACKBASE 0x82800000 /* 40MB */
39 34
40 /*----------------------------------------------------------------------- 35 /*-----------------------------------------------------------------------
41 * Physical Memory Map 36 * Physical Memory Map
42 */ 37 */
43 #define CONFIG_SYS_TEXT_BASE 0x8010E000 38 #define CONFIG_SYS_TEXT_BASE 0x8010E000
44 39
45 /* 40 /*
46 * Memory layout for where various images get loaded by boot scripts: 41 * Memory layout for where various images get loaded by boot scripts:
47 * 42 *
48 * scriptaddr can be pretty much anywhere that doesn't conflict with something 43 * scriptaddr can be pretty much anywhere that doesn't conflict with something
49 * else. Put it above BOOTMAPSZ to eliminate conflicts. 44 * else. Put it above BOOTMAPSZ to eliminate conflicts.
50 * 45 *
51 * kernel_addr_r must be within the first 128M of RAM in order for the 46 * kernel_addr_r must be within the first 128M of RAM in order for the
52 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will 47 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
53 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r 48 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
54 * should not overlap that area, or the kernel will have to copy itself 49 * should not overlap that area, or the kernel will have to copy itself
55 * somewhere else before decompression. Similarly, the address of any other 50 * somewhere else before decompression. Similarly, the address of any other
56 * data passed to the kernel shouldn't overlap the start of RAM. Pushing 51 * data passed to the kernel shouldn't overlap the start of RAM. Pushing
57 * this up to 16M allows for a sizable kernel to be decompressed below the 52 * this up to 16M allows for a sizable kernel to be decompressed below the
58 * compressed load address. 53 * compressed load address.
59 * 54 *
60 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for 55 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
61 * the compressed kernel to be up to 16M too. 56 * the compressed kernel to be up to 16M too.
62 * 57 *
63 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows 58 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
64 * for the FDT/DTB to be up to 1M, which is hopefully plenty. 59 * for the FDT/DTB to be up to 1M, which is hopefully plenty.
65 */ 60 */
66 #define MEM_LAYOUT_ENV_SETTINGS \ 61 #define MEM_LAYOUT_ENV_SETTINGS \
67 "scriptaddr=0x90000000\0" \ 62 "scriptaddr=0x90000000\0" \
68 "kernel_addr_r=0x81000000\0" \ 63 "kernel_addr_r=0x81000000\0" \
69 "fdt_addr_r=0x82000000\0" \ 64 "fdt_addr_r=0x82000000\0" \
70 "ramdisk_addr_r=0x82100000\0" 65 "ramdisk_addr_r=0x82100000\0"
71 66
72 /* Defines for SPL */ 67 /* Defines for SPL */
73 #define CONFIG_SPL_TEXT_BASE 0x80108000 68 #define CONFIG_SPL_TEXT_BASE 0x80108000
74 #define CONFIG_SYS_SPL_MALLOC_START 0x80090000 69 #define CONFIG_SYS_SPL_MALLOC_START 0x80090000
75 #define CONFIG_SPL_STACK 0x800ffffc 70 #define CONFIG_SPL_STACK 0x800ffffc
76 71
77 /* Total I2C ports on Tegra30 */ 72 /* Total I2C ports on Tegra30 */
78 #define TEGRA_I2C_NUM_CONTROLLERS 5 73 #define TEGRA_I2C_NUM_CONTROLLERS 5
79 74
80 /* For USB EHCI controller */ 75 /* For USB EHCI controller */
81 #define CONFIG_EHCI_IS_TDI 76 #define CONFIG_EHCI_IS_TDI
82 #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 77 #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
83 78
84 #endif /* _TEGRA30_COMMON_H_ */ 79 #endif /* _TEGRA30_COMMON_H_ */
85 80