ARM: tegra: move CONFIG_TEGRAnn

<asm/arch-tegra/tegra.h> needs to use CONFIG_TEGRA* to conditionalize some definitions, since some modules moved between generations. Move the definition of CONFIG_TEGRAnn to a header that's included earlier, so that it's set by the time tegra.h needs to use it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>

ARM: tegra: move CONFIG_TEGRAnn
<asm/arch-tegra/tegra.h> needs to use CONFIG_TEGRA* to conditionalize some definitions, since some modules moved between generations. Move the definition of CONFIG_TEGRAnn to a header that's included earlier, so that it's set by the time tegra.h needs to use it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren · Tom Warren
1 parent cc07294bc7
Showing 8 changed files with 8 additions and 20 deletions Side-by-side Diff
arch/arm/include/asm/arch-tegra114/tegra.h
arch/arm/include/asm/arch-tegra124/tegra.h
arch/arm/include/asm/arch-tegra20/tegra.h
arch/arm/include/asm/arch-tegra30/tegra.h
include/configs/tegra114-common.h
include/configs/tegra124-common.h
include/configs/tegra20-common.h
include/configs/tegra30-common.h
@@ -17,6 +17,8 @@
 #ifndef _TEGRA114_H_
 #define _TEGRA114_H_
  
+#define CONFIG_TEGRA114
+
 #define NV_PA_SDRAM_BASE	0x80000000	/* 0x80000000 for real T114 */
 #define NV_PA_TSC_BASE		0x700F0000	/* System Counter TSC regs */
  
@@ -8,6 +8,8 @@
 #ifndef _TEGRA124_H_
 #define _TEGRA124_H_
  
+#define CONFIG_TEGRA124
+
 #define NV_PA_SDRAM_BASE	0x80000000
 #define NV_PA_TSC_BASE		0x700F0000	/* System Counter TSC regs */
 #define NV_PA_MC_BASE		0x70019000	/* Mem Ctlr regs (MCB, etc.) */
@@ -8,6 +8,8 @@
 #ifndef _TEGRA20_H_
 #define _TEGRA20_H_
  
+#define CONFIG_TEGRA20
+
 #define NV_PA_SDRAM_BASE	0x00000000
  
 #include <asm/arch-tegra/tegra.h>
@@ -17,6 +17,8 @@
 #ifndef _TEGRA30_H_
 #define _TEGRA30_H_
  
+#define CONFIG_TEGRA30
+
 #define NV_PA_SDRAM_BASE	0x80000000	/* 0x80000000 for real T30 */
  
 #include <asm/arch-tegra/tegra.h>
@@ -26,11 +26,6 @@
  */
 #define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
  
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA114			/* in a NVidia Tegra114 core */
-
 /* Environment information, boards can override if required */
 #define CONFIG_LOADADDR		0x80408000	/* def. location for kernel */
  
@@ -18,11 +18,6 @@
  */
 #define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
  
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA124			/* is an NVIDIA Tegra124 core */
-
 /* Environment information, boards can override if required */
 #define CONFIG_LOADADDR		0x80408000	/* def. location for kernel */
  
@@ -24,11 +24,6 @@
  */
 #define V_NS16550_CLK		216000000	/* 216MHz (pllp_out0) */
  
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA20				/* in a NVidia Tegra20 core */
-
 /* Environment information, boards can override if required */
 #define CONFIG_LOADADDR		0x00408000	/* def. location for kernel */
  
@@ -23,11 +23,6 @@
  */
 #define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
  
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA30			/* in a NVidia Tegra30 core */
-
 /* Environment information, boards can override if required */
 #define CONFIG_LOADADDR		0x80408000	/* def. location for kernel */
...	...	@@ -17,6 +17,8 @@
17	17	#ifndef _TEGRA114_H_
18	18	#define _TEGRA114_H_
19	19
	20	+#define CONFIG_TEGRA114
	21	+
20	22	#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */
21	23	#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
22	24
...	...	@@ -8,6 +8,8 @@
8	8	#ifndef _TEGRA124_H_
9	9	#define _TEGRA124_H_
10	10
	11	+#define CONFIG_TEGRA124
	12	+
11	13	#define NV_PA_SDRAM_BASE 0x80000000
12	14	#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
13	15	#define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */
...	...	@@ -8,6 +8,8 @@
8	8	#ifndef _TEGRA20_H_
9	9	#define _TEGRA20_H_
10	10
	11	+#define CONFIG_TEGRA20
	12	+
11	13	#define NV_PA_SDRAM_BASE 0x00000000
12	14
13	15	#include <asm/arch-tegra/tegra.h>
...	...	@@ -17,6 +17,8 @@
17	17	#ifndef _TEGRA30_H_
18	18	#define _TEGRA30_H_
19	19
	20	+#define CONFIG_TEGRA30
	21	+
20	22	#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */
21	23
22	24	#include <asm/arch-tegra/tegra.h>
...	...	@@ -26,11 +26,6 @@
26	26	*/
27	27	#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
28	28
29		-/*
30		- * High Level Configuration Options
31		- */
32		-#define CONFIG_TEGRA114 /* in a NVidia Tegra114 core */
33		-
34	29	/* Environment information, boards can override if required */
35	30	#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
36	31
...	...	@@ -18,11 +18,6 @@
18	18	*/
19	19	#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
20	20
21		-/*
22		- * High Level Configuration Options
23		- */
24		-#define CONFIG_TEGRA124 /* is an NVIDIA Tegra124 core */
25		-
26	21	/* Environment information, boards can override if required */
27	22	#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
28	23
...	...	@@ -24,11 +24,6 @@
24	24	*/
25	25	#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
26	26
27		-/*
28		- * High Level Configuration Options
29		- */
30		-#define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */
31		-
32	27	/* Environment information, boards can override if required */
33	28	#define CONFIG_LOADADDR 0x00408000 /* def. location for kernel */
34	29
...	...	@@ -23,11 +23,6 @@
23	23	*/
24	24	#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
25	25
26		-/*
27		- * High Level Configuration Options
28		- */
29		-#define CONFIG_TEGRA30 /* in a NVidia Tegra30 core */
30		-
31	26	/* Environment information, boards can override if required */
32	27	#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
33	28