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Commit cd818a381ddcdc2440a167757394298f28b70240

Authored by Nobuhiro Iwamatsu
Committed by Heiko Schocher
1 parent 6dd38cc352
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

i2c: rcar_i2c: Fix order of restart and clear status 

In case of repeated START condition, the restart has to be kicked
before clear status (MSR register). If it is kicked after clear status,
R-Car I2C may transfer data (TXD register) or receive data (RXD register)
instead of transferring slave address (MAR register).

Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>

Showing 1 changed file with 2 additions and 2 deletions Inline Diff

drivers/i2c/rcar_i2c.c
Diff comments   View file @ cd818a3
1 /* 1 /*
2 * drivers/i2c/rcar_i2c.c 2 * drivers/i2c/rcar_i2c.c
3 * 3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation 4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 5 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
6 * 6 *
7 * SPDX-License-Identifier: GPL-2.0 7 * SPDX-License-Identifier: GPL-2.0
8 */ 8 */
9 9
10 #include <common.h> 10 #include <common.h>
11 #include <i2c.h> 11 #include <i2c.h>
12 #include <asm/io.h> 12 #include <asm/io.h>
13 13
14 DECLARE_GLOBAL_DATA_PTR; 14 DECLARE_GLOBAL_DATA_PTR;
15 15
16 struct rcar_i2c { 16 struct rcar_i2c {
17 u32 icscr; 17 u32 icscr;
18 u32 icmcr; 18 u32 icmcr;
19 u32 icssr; 19 u32 icssr;
20 u32 icmsr; 20 u32 icmsr;
21 u32 icsier; 21 u32 icsier;
22 u32 icmier; 22 u32 icmier;
23 u32 icccr; 23 u32 icccr;
24 u32 icsar; 24 u32 icsar;
25 u32 icmar; 25 u32 icmar;
26 u32 icrxdtxd; 26 u32 icrxdtxd;
27 u32 icccr2; 27 u32 icccr2;
28 u32 icmpr; 28 u32 icmpr;
29 u32 ichpr; 29 u32 ichpr;
30 u32 iclpr; 30 u32 iclpr;
31 }; 31 };
32 32
33 #define MCR_MDBS 0x80 /* non-fifo mode switch */ 33 #define MCR_MDBS 0x80 /* non-fifo mode switch */
34 #define MCR_FSCL 0x40 /* override SCL pin */ 34 #define MCR_FSCL 0x40 /* override SCL pin */
35 #define MCR_FSDA 0x20 /* override SDA pin */ 35 #define MCR_FSDA 0x20 /* override SDA pin */
36 #define MCR_OBPC 0x10 /* override pins */ 36 #define MCR_OBPC 0x10 /* override pins */
37 #define MCR_MIE 0x08 /* master if enable */ 37 #define MCR_MIE 0x08 /* master if enable */
38 #define MCR_TSBE 0x04 38 #define MCR_TSBE 0x04
39 #define MCR_FSB 0x02 /* force stop bit */ 39 #define MCR_FSB 0x02 /* force stop bit */
40 #define MCR_ESG 0x01 /* en startbit gen. */ 40 #define MCR_ESG 0x01 /* en startbit gen. */
41 41
42 #define MSR_MASK 0x7f 42 #define MSR_MASK 0x7f
43 #define MSR_MNR 0x40 /* nack received */ 43 #define MSR_MNR 0x40 /* nack received */
44 #define MSR_MAL 0x20 /* arbitration lost */ 44 #define MSR_MAL 0x20 /* arbitration lost */
45 #define MSR_MST 0x10 /* sent a stop */ 45 #define MSR_MST 0x10 /* sent a stop */
46 #define MSR_MDE 0x08 46 #define MSR_MDE 0x08
47 #define MSR_MDT 0x04 47 #define MSR_MDT 0x04
48 #define MSR_MDR 0x02 48 #define MSR_MDR 0x02
49 #define MSR_MAT 0x01 /* slave addr xfer done */ 49 #define MSR_MAT 0x01 /* slave addr xfer done */
50 50
51 static const struct rcar_i2c *i2c_dev[CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS] = { 51 static const struct rcar_i2c *i2c_dev[CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS] = {
52 (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C0_BASE, 52 (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C0_BASE,
53 (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C1_BASE, 53 (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C1_BASE,
54 (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C2_BASE, 54 (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C2_BASE,
55 (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C3_BASE, 55 (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C3_BASE,
56 }; 56 };
57 57
58 static void rcar_i2c_raw_rw_common(struct rcar_i2c *dev, u8 chip, uint addr) 58 static void rcar_i2c_raw_rw_common(struct rcar_i2c *dev, u8 chip, uint addr)
59 { 59 {
60 /* set slave address */ 60 /* set slave address */
61 writel(chip << 1, &dev->icmar); 61 writel(chip << 1, &dev->icmar);
62 /* set register address */ 62 /* set register address */
63 writel(addr, &dev->icrxdtxd); 63 writel(addr, &dev->icrxdtxd);
64 /* clear status */ 64 /* clear status */
65 writel(0, &dev->icmsr); 65 writel(0, &dev->icmsr);
66 /* start master send */ 66 /* start master send */
67 writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr); 67 writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr);
68 68
69 while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDE)) 69 while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDE))
70 != (MSR_MAT | MSR_MDE)) 70 != (MSR_MAT | MSR_MDE))
71 udelay(10); 71 udelay(10);
72 72
73 /* clear ESG */ 73 /* clear ESG */
74 writel(MCR_MDBS | MCR_MIE, &dev->icmcr); 74 writel(MCR_MDBS | MCR_MIE, &dev->icmcr);
75 /* start SCLclk */ 75 /* start SCLclk */
76 writel(~(MSR_MAT | MSR_MDE), &dev->icmsr); 76 writel(~(MSR_MAT | MSR_MDE), &dev->icmsr);
77 77
78 while (!(readl(&dev->icmsr) & MSR_MDE)) 78 while (!(readl(&dev->icmsr) & MSR_MDE))
79 udelay(10); 79 udelay(10);
80 } 80 }
81 81
82 static void rcar_i2c_raw_rw_finish(struct rcar_i2c *dev) 82 static void rcar_i2c_raw_rw_finish(struct rcar_i2c *dev)
83 { 83 {
84 while (!(readl(&dev->icmsr) & MSR_MST)) 84 while (!(readl(&dev->icmsr) & MSR_MST))
85 udelay(10); 85 udelay(10);
86 86
87 writel(0, &dev->icmcr); 87 writel(0, &dev->icmcr);
88 } 88 }
89 89
90 static int 90 static int
91 rcar_i2c_raw_write(struct rcar_i2c *dev, u8 chip, uint addr, u8 *val, int size) 91 rcar_i2c_raw_write(struct rcar_i2c *dev, u8 chip, uint addr, u8 *val, int size)
92 { 92 {
93 rcar_i2c_raw_rw_common(dev, chip, addr); 93 rcar_i2c_raw_rw_common(dev, chip, addr);
94 94
95 /* set send date */ 95 /* set send date */
96 writel(*val, &dev->icrxdtxd); 96 writel(*val, &dev->icrxdtxd);
97 /* start SCLclk */ 97 /* start SCLclk */
98 writel(~MSR_MDE, &dev->icmsr); 98 writel(~MSR_MDE, &dev->icmsr);
99 99
100 while (!(readl(&dev->icmsr) & MSR_MDE)) 100 while (!(readl(&dev->icmsr) & MSR_MDE))
101 udelay(10); 101 udelay(10);
102 102
103 /* set stop condition */ 103 /* set stop condition */
104 writel(MCR_MDBS | MCR_MIE | MCR_FSB, &dev->icmcr); 104 writel(MCR_MDBS | MCR_MIE | MCR_FSB, &dev->icmcr);
105 /* start SCLclk */ 105 /* start SCLclk */
106 writel(~MSR_MDE, &dev->icmsr); 106 writel(~MSR_MDE, &dev->icmsr);
107 107
108 rcar_i2c_raw_rw_finish(dev); 108 rcar_i2c_raw_rw_finish(dev);
109 109
110 return 0; 110 return 0;
111 } 111 }
112 112
113 static u8 113 static u8
114 rcar_i2c_raw_read(struct rcar_i2c *dev, u8 chip, uint addr) 114 rcar_i2c_raw_read(struct rcar_i2c *dev, u8 chip, uint addr)
115 { 115 {
116 u8 ret; 116 u8 ret;
117 117
118 rcar_i2c_raw_rw_common(dev, chip, addr); 118 rcar_i2c_raw_rw_common(dev, chip, addr);
119 119
120 /* set slave address, receive */ 120 /* set slave address, receive */
121 writel((chip << 1) | 1, &dev->icmar); 121 writel((chip << 1) | 1, &dev->icmar);
122 /* clear status */
123 writel(0, &dev->icmsr);
124 /* start master receive */ 122 /* start master receive */
125 writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr); 123 writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr);
124 /* clear status */
125 writel(0, &dev->icmsr);
126 126
127 while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDR)) 127 while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDR))
128 != (MSR_MAT | MSR_MDR)) 128 != (MSR_MAT | MSR_MDR))
129 udelay(10); 129 udelay(10);
130 130
131 /* clear ESG */ 131 /* clear ESG */
132 writel(MCR_MDBS | MCR_MIE, &dev->icmcr); 132 writel(MCR_MDBS | MCR_MIE, &dev->icmcr);
133 /* prepare stop condition */ 133 /* prepare stop condition */
134 writel(MCR_MDBS | MCR_MIE | MCR_FSB, &dev->icmcr); 134 writel(MCR_MDBS | MCR_MIE | MCR_FSB, &dev->icmcr);
135 /* start SCLclk */ 135 /* start SCLclk */
136 writel(~(MSR_MAT | MSR_MDR), &dev->icmsr); 136 writel(~(MSR_MAT | MSR_MDR), &dev->icmsr);
137 137
138 while (!(readl(&dev->icmsr) & MSR_MDR)) 138 while (!(readl(&dev->icmsr) & MSR_MDR))
139 udelay(10); 139 udelay(10);
140 140
141 /* get receive data */ 141 /* get receive data */
142 ret = (u8)readl(&dev->icrxdtxd); 142 ret = (u8)readl(&dev->icrxdtxd);
143 /* start SCLclk */ 143 /* start SCLclk */
144 writel(~MSR_MDR, &dev->icmsr); 144 writel(~MSR_MDR, &dev->icmsr);
145 145
146 rcar_i2c_raw_rw_finish(dev); 146 rcar_i2c_raw_rw_finish(dev);
147 147
148 return ret; 148 return ret;
149 } 149 }
150 150
151 /* 151 /*
152 * SCL = iicck / (20 + SCGD * 8 + F[(ticf + tr + intd) * iicck]) 152 * SCL = iicck / (20 + SCGD * 8 + F[(ticf + tr + intd) * iicck])
153 * iicck : I2C internal clock < 20 MHz 153 * iicck : I2C internal clock < 20 MHz
154 * ticf : I2C SCL falling time: 35 ns 154 * ticf : I2C SCL falling time: 35 ns
155 * tr : I2C SCL rising time: 200 ns 155 * tr : I2C SCL rising time: 200 ns
156 * intd : LSI internal delay: I2C0: 50 ns I2C1-3: 5 156 * intd : LSI internal delay: I2C0: 50 ns I2C1-3: 5
157 * F[n] : n rounded up to an integer 157 * F[n] : n rounded up to an integer
158 */ 158 */
159 static u32 rcar_clock_gen(int i2c_no, u32 bus_speed) 159 static u32 rcar_clock_gen(int i2c_no, u32 bus_speed)
160 { 160 {
161 u32 iicck, f, scl, scgd; 161 u32 iicck, f, scl, scgd;
162 u32 intd = 5; 162 u32 intd = 5;
163 163
164 int bit = 0, cdf_width = 3; 164 int bit = 0, cdf_width = 3;
165 for (bit = 0; bit < (1 << cdf_width); bit++) { 165 for (bit = 0; bit < (1 << cdf_width); bit++) {
166 iicck = CONFIG_HP_CLK_FREQ / (1 + bit); 166 iicck = CONFIG_HP_CLK_FREQ / (1 + bit);
167 if (iicck < 20000000) 167 if (iicck < 20000000)
168 break; 168 break;
169 } 169 }
170 170
171 if (bit > (1 << cdf_width)) { 171 if (bit > (1 << cdf_width)) {
172 puts("rcar-i2c: Can not get CDF\n"); 172 puts("rcar-i2c: Can not get CDF\n");
173 return 0; 173 return 0;
174 } 174 }
175 175
176 if (i2c_no == 0) 176 if (i2c_no == 0)
177 intd = 50; 177 intd = 50;
178 178
179 f = (35 + 200 + intd) * (iicck / 1000000000); 179 f = (35 + 200 + intd) * (iicck / 1000000000);
180 180
181 for (scgd = 0; scgd < 0x40; scgd++) { 181 for (scgd = 0; scgd < 0x40; scgd++) {
182 scl = iicck / (20 + (scgd * 8) + f); 182 scl = iicck / (20 + (scgd * 8) + f);
183 if (scl <= bus_speed) 183 if (scl <= bus_speed)
184 break; 184 break;
185 } 185 }
186 186
187 if (scgd > 0x40) { 187 if (scgd > 0x40) {
188 puts("rcar-i2c: Can not get SDGB\n"); 188 puts("rcar-i2c: Can not get SDGB\n");
189 return 0; 189 return 0;
190 } 190 }
191 191
192 debug("%s: scl: %d\n", __func__, scl); 192 debug("%s: scl: %d\n", __func__, scl);
193 debug("%s: bit %x\n", __func__, bit); 193 debug("%s: bit %x\n", __func__, bit);
194 debug("%s: scgd %x\n", __func__, scgd); 194 debug("%s: scgd %x\n", __func__, scgd);
195 debug("%s: iccr %x\n", __func__, (scgd << (cdf_width) | bit)); 195 debug("%s: iccr %x\n", __func__, (scgd << (cdf_width) | bit));
196 196
197 return scgd << (cdf_width) | bit; 197 return scgd << (cdf_width) | bit;
198 } 198 }
199 199
200 static void 200 static void
201 rcar_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) 201 rcar_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
202 { 202 {
203 struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr]; 203 struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
204 u32 icccr = 0; 204 u32 icccr = 0;
205 205
206 /* No i2c support prior to relocation */ 206 /* No i2c support prior to relocation */
207 if (!(gd->flags & GD_FLG_RELOC)) 207 if (!(gd->flags & GD_FLG_RELOC))
208 return; 208 return;
209 209
210 /* 210 /*
211 * reset slave mode. 211 * reset slave mode.
212 * slave mode is not used on this driver 212 * slave mode is not used on this driver
213 */ 213 */
214 writel(0, &dev->icsier); 214 writel(0, &dev->icsier);
215 writel(0, &dev->icsar); 215 writel(0, &dev->icsar);
216 writel(0, &dev->icscr); 216 writel(0, &dev->icscr);
217 writel(0, &dev->icssr); 217 writel(0, &dev->icssr);
218 218
219 /* reset master mode */ 219 /* reset master mode */
220 writel(0, &dev->icmier); 220 writel(0, &dev->icmier);
221 writel(0, &dev->icmcr); 221 writel(0, &dev->icmcr);
222 writel(0, &dev->icmsr); 222 writel(0, &dev->icmsr);
223 writel(0, &dev->icmar); 223 writel(0, &dev->icmar);
224 224
225 icccr = rcar_clock_gen(adap->hwadapnr, adap->speed); 225 icccr = rcar_clock_gen(adap->hwadapnr, adap->speed);
226 if (icccr == 0) 226 if (icccr == 0)
227 puts("I2C: Init failed\n"); 227 puts("I2C: Init failed\n");
228 else 228 else
229 writel(icccr, &dev->icccr); 229 writel(icccr, &dev->icccr);
230 } 230 }
231 231
232 static int rcar_i2c_read(struct i2c_adapter *adap, uint8_t chip, 232 static int rcar_i2c_read(struct i2c_adapter *adap, uint8_t chip,
233 uint addr, int alen, u8 *data, int len) 233 uint addr, int alen, u8 *data, int len)
234 { 234 {
235 struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr]; 235 struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
236 int i; 236 int i;
237 237
238 for (i = 0; i < len; i++) 238 for (i = 0; i < len; i++)
239 data[i] = rcar_i2c_raw_read(dev, chip, addr + i); 239 data[i] = rcar_i2c_raw_read(dev, chip, addr + i);
240 240
241 return 0; 241 return 0;
242 } 242 }
243 243
244 static int rcar_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr, 244 static int rcar_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr,
245 int alen, u8 *data, int len) 245 int alen, u8 *data, int len)
246 { 246 {
247 struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr]; 247 struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
248 return rcar_i2c_raw_write(dev, chip, addr, data, len); 248 return rcar_i2c_raw_write(dev, chip, addr, data, len);
249 } 249 }
250 250
251 static int 251 static int
252 rcar_i2c_probe(struct i2c_adapter *adap, u8 dev) 252 rcar_i2c_probe(struct i2c_adapter *adap, u8 dev)
253 { 253 {
254 return rcar_i2c_read(adap, dev, 0, 0, NULL, 0); 254 return rcar_i2c_read(adap, dev, 0, 0, NULL, 0);
255 } 255 }
256 256
257 static unsigned int rcar_i2c_set_bus_speed(struct i2c_adapter *adap, 257 static unsigned int rcar_i2c_set_bus_speed(struct i2c_adapter *adap,
258 unsigned int speed) 258 unsigned int speed)
259 { 259 {
260 struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr]; 260 struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
261 u32 icccr; 261 u32 icccr;
262 int ret = 0; 262 int ret = 0;
263 263
264 rcar_i2c_raw_rw_finish(dev); 264 rcar_i2c_raw_rw_finish(dev);
265 265
266 icccr = rcar_clock_gen(adap->hwadapnr, speed); 266 icccr = rcar_clock_gen(adap->hwadapnr, speed);
267 if (icccr == 0) { 267 if (icccr == 0) {
268 puts("I2C: Init failed\n"); 268 puts("I2C: Init failed\n");
269 ret = -1; 269 ret = -1;
270 } else { 270 } else {
271 writel(icccr, &dev->icccr); 271 writel(icccr, &dev->icccr);
272 } 272 }
273 return ret; 273 return ret;
274 } 274 }
275 275
276 /* 276 /*
277 * Register RCAR i2c adapters 277 * Register RCAR i2c adapters
278 */ 278 */
279 U_BOOT_I2C_ADAP_COMPLETE(rcar_0, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read, 279 U_BOOT_I2C_ADAP_COMPLETE(rcar_0, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
280 rcar_i2c_write, rcar_i2c_set_bus_speed, 280 rcar_i2c_write, rcar_i2c_set_bus_speed,
281 CONFIG_SYS_RCAR_I2C0_SPEED, 0, 0) 281 CONFIG_SYS_RCAR_I2C0_SPEED, 0, 0)
282 U_BOOT_I2C_ADAP_COMPLETE(rcar_1, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read, 282 U_BOOT_I2C_ADAP_COMPLETE(rcar_1, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
283 rcar_i2c_write, rcar_i2c_set_bus_speed, 283 rcar_i2c_write, rcar_i2c_set_bus_speed,
284 CONFIG_SYS_RCAR_I2C1_SPEED, 0, 1) 284 CONFIG_SYS_RCAR_I2C1_SPEED, 0, 1)
285 U_BOOT_I2C_ADAP_COMPLETE(rcar_2, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read, 285 U_BOOT_I2C_ADAP_COMPLETE(rcar_2, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
286 rcar_i2c_write, rcar_i2c_set_bus_speed, 286 rcar_i2c_write, rcar_i2c_set_bus_speed,
287 CONFIG_SYS_RCAR_I2C2_SPEED, 0, 2) 287 CONFIG_SYS_RCAR_I2C2_SPEED, 0, 2)
288 U_BOOT_I2C_ADAP_COMPLETE(rcar_3, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read, 288 U_BOOT_I2C_ADAP_COMPLETE(rcar_3, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
289 rcar_i2c_write, rcar_i2c_set_bus_speed, 289 rcar_i2c_write, rcar_i2c_set_bus_speed,