Makefile: prepare for using Kbuild-style Makefile

Every makefile in sub directories has common lines at the top and the bottom. This commit pushes the common parts into script/Makefile.build. Going forward sub-makefiles only need to describe this part: COBJS := ... COBJS += ... SOBJS := ... But using obj-y is preferable to prepare for switching to Kbuild. The conventional (non-Kbuild) Makefile style is still supported. This is achieved by greping the Makefile before entering into it. U-Boot conventional sub makefiles always include some other makefiles. So the build system searches a line beginning with "include" keyword in the makefile in order to distinguish which style it is. If the Makefile include a "include" line, we assume it is a conventional U-Boot style. Otherwise, it is treated as a Kbuild-style makefile. With this tweak, we can switch sub-makefiles from U-Boot style to Kbuild style little by little. obj-y := foo/ syntax (descending into the sub directory) is not supportd yet. It will be implemented in the upcomming commit. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@ti.com>

Makefile: prepare for using Kbuild-style Makefile
Every makefile in sub directories has common lines at the top and the bottom. This commit pushes the common parts into script/Makefile.build. Going forward sub-makefiles only need to describe this part: COBJS := ... COBJS += ... SOBJS := ... But using obj-y is preferable to prepare for switching to Kbuild. The conventional (non-Kbuild) Makefile style is still supported. This is achieved by greping the Makefile before entering into it. U-Boot conventional sub makefiles always include some other makefiles. So the build system searches a line beginning with "include" keyword in the makefile in order to distinguish which style it is. If the Makefile include a "include" line, we assume it is a conventional U-Boot style. Otherwise, it is treated as a Kbuild-style makefile. With this tweak, we can switch sub-makefiles from U-Boot style to Kbuild style little by little. obj-y := foo/ syntax (descending into the sub directory) is not supportd yet. It will be implemented in the upcomming commit. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@ti.com>
Masahiro Yamada · Tom Rini
1 parent 9d33fb4a5c
Showing 3 changed files with 99 additions and 7 deletions Side-by-side Diff
Makefile
scripts/Makefile.build
spl/Makefile
@@ -595,14 +595,32 @@
 		$(GEN_UBOOT) $(obj)common/system_map.o
 endif
  
+# Tentative step for Kbuild-style makefiles coexist with conventional U-Boot style makefiles
+#  U-Boot conventional sub makefiles always include some other makefiles.
+#  So, the build system searches a line beginning with "include" before entering into the sub makefile
+#  in order to distinguish which style it is.
+#  If the Makefile include a "include" line, we assume it is an U-Boot style makefile.
+#  Otherwise, it is treated as a Kbuild-style makefile.
+select_makefile = \
+	+if grep -q "^include" $1/Makefile; then				\
+		$(MAKE) -C $1;						\
+	else								\
+		$(MAKE) -C $1 -f $(TOPDIR)/scripts/Makefile.build;	\
+		mv $(dir $@)built-in.o $@;				\
+	fi
+
+# We do not need to build $(OBJS) explicitly.
+# It is built while we are at $(CPUDIR)/lib$(CPU).o build.
 $(OBJS):	depend
-		$(MAKE) -C $(CPUDIR) $(if $(REMOTE_BUILD),$@,$(notdir $@))
+		if grep -q "^include" $(CPUDIR)/Makefile; then \
+			$(MAKE) -C $(CPUDIR) $(if $(REMOTE_BUILD),$@,$(notdir $@)); \
+		fi
  
 $(LIBS):	depend $(SUBDIR_TOOLS)
-		$(MAKE) -C $(dir $(subst $(obj),,$@))
+		+$(call select_makefile, $(dir $(subst $(obj),,$@)))
  
 $(LIBBOARD):	depend $(LIBS)
-		$(MAKE) -C $(dir $(subst $(obj),,$@))
+		+$(call select_makefile, $(dir $(subst $(obj),,$@)))
  
 $(SUBDIRS):	depend
 		$(MAKE) -C $@ all
@@ -630,6 +648,13 @@
 updater:
 		$(MAKE) -C tools/updater all
  
+select_makefile2 = \
+	if grep -q "^include" $1/Makefile; then					\
+		$(MAKE) -C $1 _depend;						\
+	else									\
+		$(MAKE) -C $1 -f $(TOPDIR)/scripts/Makefile.build _depend;	\
+	fi
+
 # Explicitly make _depend in subdirs containing multiple targets to prevent
 # parallel sub-makes creating .depend files simultaneously.
 depend dep:	$(TIMESTAMP_FILE) $(VERSION_FILE) \
@@ -638,8 +663,9 @@
 		$(obj)include/autoconf.mk \
 		$(obj)include/generated/generic-asm-offsets.h \
 		$(obj)include/generated/asm-offsets.h
-		for dir in $(SUBDIRS) $(CPUDIR) $(LDSCRIPT_MAKEFILE_DIR) ; do \
-			$(MAKE) -C $$dir _depend ; done
+		+for dir in $(SUBDIRS) $(CPUDIR) $(LDSCRIPT_MAKEFILE_DIR) ; do \
+			$(call select_makefile2, $$dir); \
+		done
  
 TAG_SUBDIRS = $(SUBDIRS)
 TAG_SUBDIRS += $(dir $(__LIBS))
+# our default target
+.PHONY: all
+all:
+
+include $(TOPDIR)/config.mk
+
+LIB := $(obj)built-in.o
+LIBGCC = $(obj)libgcc.o
+SRCS :=
+
+include Makefile
+
+# Backward compatible: obj-y is preferable
+COBJS := $(sort $(COBJS) $(COBJS-y))
+SOBJS := $(sort $(SOBJS) $(SOBJS-y))
+
+# Going forward use the following
+obj-y := $(sort $(obj-y))
+extra-y := $(sort $(extra-y))
+lib-y := $(sort $(lib-y))
+
+SRCS	+= $(COBJS:.o=.c) $(SOBJS:.o=.S) \
+ $(wildcard $(obj-y:.o=.c) $(obj-y:.o=.S) $(lib-y:.o=.c) $(lib-y:.o=.S) $(extra-y:.o=.c) $(extra-y:.o=.S))
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS) $(obj-y))
+
+LGOBJS := $(addprefix $(obj),$(sort $(GLSOBJS) $(GLCOBJS)) $(lib-y))
+
+all: $(LIB) $(addprefix $(obj),$(extra-y))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+ifneq ($(strip $(lib-y)),)
+all: $(LIBGCC)
+
+$(LIBGCC): $(obj).depend $(LGOBJS)
+	$(call cmd_link_o_target, $(LGOBJS))
+endif
+
+#########################################################################
+
+# defines $(obj).depend target
+
+include $(TOPDIR)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
@@ -200,11 +200,29 @@
 $(obj)$(SPL_BIN):	depend $(START) $(LIBS) $(obj)u-boot-spl.lds
 	$(GEN_UBOOT)
  
+# Tentative step for Kbuild-style makefiles coexist with conventional U-Boot style makefiles
+#  U-Boot conventional sub makefiles always include some other makefiles.
+#  So, the build system searches a line beginning with "include" before entering into the sub makefile
+#  in order to distinguish which style it is.
+#  If the Makefile include a "include" line, we assume it is an U-Boot style makefile.
+#  Otherwise, it is treated as a Kbuild-style makefile.
+select_makefile = \
+	if grep -q "^include" $1/Makefile; then				\
+		$(MAKE) -C $1;						\
+	else								\
+		$(MAKE) -C $1 -f $(TOPDIR)/scripts/Makefile.build;	\
+		mv $(dir $@)built-in.o $@;				\
+	fi
+
+# We do not need to build $(START) explicitly.
+# It is built while we are at $(CPUDIR)/lib$(CPU).o build.
 $(START):	depend
-	$(MAKE) -C $(SRCTREE)/$(START_PATH) $@
+	if grep -q "^include" $(SRCTREE)$(dir $(subst $(SPLTREE),,$@))Makefile; then \
+		$(MAKE) -C $(SRCTREE)/$(START_PATH) $@; \
+	fi
  
 $(LIBS):	depend
-	$(MAKE) -C $(SRCTREE)$(dir $(subst $(SPLTREE),,$@))
+	+$(call select_makefile, $(SRCTREE)$(dir $(subst $(SPLTREE),,$@)))
  
 $(obj)u-boot-spl.lds: $(LDSCRIPT) depend
 	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj). -ansi -D__ASSEMBLY__ -P - < $< > $@
...	...	@@ -595,14 +595,32 @@
595	595	$(GEN_UBOOT) $(obj)common/system_map.o
596	596	endif
597	597
	598	+# Tentative step for Kbuild-style makefiles coexist with conventional U-Boot style makefiles
	599	+# U-Boot conventional sub makefiles always include some other makefiles.
	600	+# So, the build system searches a line beginning with "include" before entering into the sub makefile
	601	+# in order to distinguish which style it is.
	602	+# If the Makefile include a "include" line, we assume it is an U-Boot style makefile.
	603	+# Otherwise, it is treated as a Kbuild-style makefile.
	604	+select_makefile = \
	605	+ +if grep -q "^include" $1/Makefile; then \
	606	+ $(MAKE) -C $1; \
	607	+ else \
	608	+ $(MAKE) -C $1 -f $(TOPDIR)/scripts/Makefile.build; \
	609	+ mv $(dir $@)built-in.o $@; \
	610	+ fi
	611	+
	612	+# We do not need to build $(OBJS) explicitly.
	613	+# It is built while we are at $(CPUDIR)/lib$(CPU).o build.
598	614	$(OBJS): depend
599		- $(MAKE) -C $(CPUDIR) $(if $(REMOTE_BUILD),$@,$(notdir $@))
	615	+ if grep -q "^include" $(CPUDIR)/Makefile; then \
	616	+ $(MAKE) -C $(CPUDIR) $(if $(REMOTE_BUILD),$@,$(notdir $@)); \
	617	+ fi
600	618
601	619	$(LIBS): depend $(SUBDIR_TOOLS)
602		- $(MAKE) -C $(dir $(subst $(obj),,$@))
	620	+ +$(call select_makefile, $(dir $(subst $(obj),,$@)))
603	621
604	622	$(LIBBOARD): depend $(LIBS)
605		- $(MAKE) -C $(dir $(subst $(obj),,$@))
	623	+ +$(call select_makefile, $(dir $(subst $(obj),,$@)))
606	624
607	625	$(SUBDIRS): depend
608	626	$(MAKE) -C $@ all
...	...	@@ -630,6 +648,13 @@
630	648	updater:
631	649	$(MAKE) -C tools/updater all
632	650
	651	+select_makefile2 = \
	652	+ if grep -q "^include" $1/Makefile; then \
	653	+ $(MAKE) -C $1 _depend; \
	654	+ else \
	655	+ $(MAKE) -C $1 -f $(TOPDIR)/scripts/Makefile.build _depend; \
	656	+ fi
	657	+
633	658	# Explicitly make _depend in subdirs containing multiple targets to prevent
634	659	# parallel sub-makes creating .depend files simultaneously.
635	660	depend dep: $(TIMESTAMP_FILE) $(VERSION_FILE) \
...	...	@@ -638,8 +663,9 @@
638	663	$(obj)include/autoconf.mk \
639	664	$(obj)include/generated/generic-asm-offsets.h \
640	665	$(obj)include/generated/asm-offsets.h
641		- for dir in $(SUBDIRS) $(CPUDIR) $(LDSCRIPT_MAKEFILE_DIR) ; do \
642		- $(MAKE) -C $$dir _depend ; done
	666	+ +for dir in $(SUBDIRS) $(CPUDIR) $(LDSCRIPT_MAKEFILE_DIR) ; do \
	667	+ $(call select_makefile2, $$dir); \
	668	+ done
643	669
644	670	TAG_SUBDIRS = $(SUBDIRS)
645	671	TAG_SUBDIRS += $(dir $(__LIBS))
	1	+# our default target
	2	+.PHONY: all
	3	+all:
	4	+
	5	+include $(TOPDIR)/config.mk
	6	+
	7	+LIB := $(obj)built-in.o
	8	+LIBGCC = $(obj)libgcc.o
	9	+SRCS :=
	10	+
	11	+include Makefile
	12	+
	13	+# Backward compatible: obj-y is preferable
	14	+COBJS := $(sort $(COBJS) $(COBJS-y))
	15	+SOBJS := $(sort $(SOBJS) $(SOBJS-y))
	16	+
	17	+# Going forward use the following
	18	+obj-y := $(sort $(obj-y))
	19	+extra-y := $(sort $(extra-y))
	20	+lib-y := $(sort $(lib-y))
	21	+
	22	+SRCS += $(COBJS:.o=.c) $(SOBJS:.o=.S) \
	23	+ $(wildcard $(obj-y:.o=.c) $(obj-y:.o=.S) $(lib-y:.o=.c) $(lib-y:.o=.S) $(extra-y:.o=.c) $(extra-y:.o=.S))
	24	+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS) $(obj-y))
	25	+
	26	+LGOBJS := $(addprefix $(obj),$(sort $(GLSOBJS) $(GLCOBJS)) $(lib-y))
	27	+
	28	+all: $(LIB) $(addprefix $(obj),$(extra-y))
	29	+
	30	+$(LIB): $(obj).depend $(OBJS)
	31	+ $(call cmd_link_o_target, $(OBJS))
	32	+
	33	+ifneq ($(strip $(lib-y)),)
	34	+all: $(LIBGCC)
	35	+
	36	+$(LIBGCC): $(obj).depend $(LGOBJS)
	37	+ $(call cmd_link_o_target, $(LGOBJS))
	38	+endif
	39	+
	40	+#########################################################################
	41	+
	42	+# defines $(obj).depend target
	43	+
	44	+include $(TOPDIR)/rules.mk
	45	+
	46	+sinclude $(obj).depend
	47	+
	48	+#########################################################################
...	...	@@ -200,11 +200,29 @@
200	200	$(obj)$(SPL_BIN): depend $(START) $(LIBS) $(obj)u-boot-spl.lds
201	201	$(GEN_UBOOT)
202	202
	203	+# Tentative step for Kbuild-style makefiles coexist with conventional U-Boot style makefiles
	204	+# U-Boot conventional sub makefiles always include some other makefiles.
	205	+# So, the build system searches a line beginning with "include" before entering into the sub makefile
	206	+# in order to distinguish which style it is.
	207	+# If the Makefile include a "include" line, we assume it is an U-Boot style makefile.
	208	+# Otherwise, it is treated as a Kbuild-style makefile.
	209	+select_makefile = \
	210	+ if grep -q "^include" $1/Makefile; then \
	211	+ $(MAKE) -C $1; \
	212	+ else \
	213	+ $(MAKE) -C $1 -f $(TOPDIR)/scripts/Makefile.build; \
	214	+ mv $(dir $@)built-in.o $@; \
	215	+ fi
	216	+
	217	+# We do not need to build $(START) explicitly.
	218	+# It is built while we are at $(CPUDIR)/lib$(CPU).o build.
203	219	$(START): depend
204		- $(MAKE) -C $(SRCTREE)/$(START_PATH) $@
	220	+ if grep -q "^include" $(SRCTREE)$(dir $(subst $(SPLTREE),,$@))Makefile; then \
	221	+ $(MAKE) -C $(SRCTREE)/$(START_PATH) $@; \
	222	+ fi
205	223
206	224	$(LIBS): depend
207		- $(MAKE) -C $(SRCTREE)$(dir $(subst $(SPLTREE),,$@))
	225	+ +$(call select_makefile, $(SRCTREE)$(dir $(subst $(SPLTREE),,$@)))
208	226
209	227	$(obj)u-boot-spl.lds: $(LDSCRIPT) depend
210	228	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj). -ansi -D__ASSEMBLY__ -P - < $< > $@