mx6: clock: Add thermal clock enable function

Add api to check and enable pll3 as required for thermal sensor driver. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>

mx6: clock: Add thermal clock enable function
Add api to check and enable pll3 as required for thermal sensor driver. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Nitin Garg · Stefano Babic
1 parent 02a32a92d4
Showing 2 changed files with 31 additions and 0 deletions Side-by-side Diff
arch/arm/cpu/armv7/mx6/clock.c
arch/arm/include/asm/arch-mx6/clock.h
@@ -673,6 +673,36 @@
 }
 #endif
  
+static void enable_pll3(void)
+{
+	struct anatop_regs __iomem *anatop =
+		(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
+
+	/* make sure pll3 is enabled */
+	if ((readl(&anatop->usb1_pll_480_ctrl) &
+			BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
+		/* enable pll's power */
+		writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
+		       &anatop->usb1_pll_480_ctrl_set);
+		writel(0x80, &anatop->ana_misc2_clr);
+		/* wait for pll lock */
+		while ((readl(&anatop->usb1_pll_480_ctrl) &
+			BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
+			;
+		/* disable bypass */
+		writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
+		       &anatop->usb1_pll_480_ctrl_clr);
+		/* enable pll output */
+		writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
+		       &anatop->usb1_pll_480_ctrl_set);
+	}
+}
+
+void enable_thermal_clk(void)
+{
+	enable_pll3();
+}
+
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
 	switch (clk) {
@@ -66,5 +66,6 @@
 void enable_ipu_clock(void);
 int enable_fec_anatop_clock(enum enet_freq freq);
 void enable_enet_clk(unsigned char enable);
+void enable_thermal_clk(void);
 #endif /* __ASM_ARCH_CLOCK_H */
...	...	@@ -673,6 +673,36 @@
673	673	}
674	674	#endif
675	675
	676	+static void enable_pll3(void)
	677	+{
	678	+ struct anatop_regs __iomem *anatop =
	679	+ (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
	680	+
	681	+ /* make sure pll3 is enabled */
	682	+ if ((readl(&anatop->usb1_pll_480_ctrl) &
	683	+ BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
	684	+ /* enable pll's power */
	685	+ writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
	686	+ &anatop->usb1_pll_480_ctrl_set);
	687	+ writel(0x80, &anatop->ana_misc2_clr);
	688	+ /* wait for pll lock */
	689	+ while ((readl(&anatop->usb1_pll_480_ctrl) &
	690	+ BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
	691	+ ;
	692	+ /* disable bypass */
	693	+ writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
	694	+ &anatop->usb1_pll_480_ctrl_clr);
	695	+ /* enable pll output */
	696	+ writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
	697	+ &anatop->usb1_pll_480_ctrl_set);
	698	+ }
	699	+}
	700	+
	701	+void enable_thermal_clk(void)
	702	+{
	703	+ enable_pll3();
	704	+}
	705	+
676	706	unsigned int mxc_get_clock(enum mxc_clock clk)
677	707	{
678	708	switch (clk) {
...	...	@@ -66,5 +66,6 @@
66	66	void enable_ipu_clock(void);
67	67	int enable_fec_anatop_clock(enum enet_freq freq);
68	68	void enable_enet_clk(unsigned char enable);
	69	+void enable_thermal_clk(void);
69	70	#endif /* __ASM_ARCH_CLOCK_H */