ppc4xx: Add NAND booting support for AMCC Bamboo (440EP) eval board

This patch adds NAND booting support for the AMCC Bamboo eval board. Since the NAND-SPL boot image is limited to 4kbytes, this version only supports the onboard 64MBytes of DDR. The DIMM modules can't be supported, since the setup code for I2C DIMM autodetection and configuration is too big for this NAND bootloader. Signed-off-by: Stefan Roese <sr@denx.de>

ppc4xx: Add NAND booting support for AMCC Bamboo (440EP) eval board
This patch adds NAND booting support for the AMCC Bamboo eval board. Since the NAND-SPL boot image is limited to 4kbytes, this version only supports the onboard 64MBytes of DDR. The DIMM modules can't be supported, since the setup code for I2C DIMM autodetection and configuration is too big for this NAND bootloader. Signed-off-by: Stefan Roese <sr@denx.de>
Stefan Roese
1 parent 42be56f53c
Showing 8 changed files with 536 additions and 119 deletions Side-by-side Diff
MAKEALL
Makefile
cpu/ppc4xx/start.S
include/configs/bamboo.h
nand_spl/board/amcc/bamboo/Makefile
nand_spl/board/amcc/bamboo/config.mk
nand_spl/board/amcc/bamboo/sdram.c
nand_spl/board/amcc/bamboo/u-boot.lds
@@ -76,21 +76,21 @@
  
 LIST_4xx="	\
 	acadia		ADCIOP		alpr		AP1000		\
-	AR405		ASH405		bamboo		bubinga		\
-	CANBT		CMS700		CPCI2DP		CPCI405		\
-	CPCI4052	CPCI405AB	CPCI405DT	CPCI440		\
-	CPCIISER4	CRAYL1		csb272		csb472		\
-	DASA_SIM	DP405		DU405		ebony		\
-	ERIC		EXBITGEN	G2000		HH405		\
-	HUB405		JSE		KAREF		katmai		\
-	luan		METROBOX	MIP405		MIP405T		\
-	ML2		ml300		ocotea		OCRTC		\
-	ORSG		p3p440		PCI405		pcs440ep	\
-	PIP405		PLU405		PMC405		PPChameleonEVB	\
-	sbc405		sc3		sequoia		sequoia_nand	\
-	taishan		VOH405		VOM405		W7OLMC		\
-	W7OLMG		walnut		WUH405		XPEDITE1K	\
-	yellowstone	yosemite	yucca				\
+	AR405		ASH405		bamboo		bamboo_nand	\
+	bubinga		CANBT		CMS700		CPCI2DP		\
+	CPCI405		CPCI4052	CPCI405AB	CPCI405DT	\
+	CPCI440		CPCIISER4	CRAYL1		csb272		\
+	csb472		DASA_SIM	DP405		DU405		\
+	ebony		ERIC		EXBITGEN	G2000		\
+	HH405		HUB405		JSE		KAREF		\
+	katmai		luan		METROBOX	MIP405		\
+	MIP405T		ML2		ml300		ocotea		\
+	OCRTC		ORSG		p3p440		PCI405		\
+	pcs440ep	PIP405		PLU405		PMC405		\
+	PPChameleonEVB	sbc405		sc3		sequoia		\
+	sequoia_nand	taishan		VOH405		VOM405		\
+	W7OLMC		W7OLMG		walnut		WUH405		\
+	XPEDITE1K	yellowstone	yosemite	yucca		\
 "
  
 #########################################################################
@@ -1035,6 +1035,16 @@
 bamboo_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx bamboo amcc
  
+bamboo_nand_config:	unconfig
+	@mkdir -p $(obj)include
+	@mkdir -p $(obj)nand_spl
+	@mkdir -p $(obj)board/amcc/bamboo
+	@echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
+	@echo "Compile NAND boot image for bamboo"
+	@$(MKCONFIG) -a bamboo ppc ppc4xx bamboo amcc
+	@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/bamboo/config.tmp
+	@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
+
 bubinga_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx bubinga amcc
  
@@ -110,6 +110,13 @@
 # endif
 #endif /* CFG_INIT_DCACHE_CS */
  
+#define function_prolog(func_name)      .text; \
+					.align 2; \
+					.globl func_name; \
+					func_name:
+#define function_epilog(func_name)      .type func_name,@function; \
+					.size func_name,.-func_name
+
 /* We don't want the  MMU yet.
 */
 #undef	MSR_KERNEL
  
@@ -388,8 +395,9 @@
 2:
  
 #if defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	/*
-	 * Enable internal SRAM
+	 * Enable internal SRAM (only on 440EPx/GRx, 440EP/GR have no OCM)
 	 */
 	lis	r2,0x7fff
 	ori	r2,r2,0xffff
  
@@ -399,7 +407,46 @@
 	mfdcr	r1,isram0_pmeg
 	and	r1,r1,r2		/* Disable pwr mgmt */
 	mtdcr	isram0_pmeg,r1
+#endif
+#if defined(CONFIG_440EP)
+	/*
+	 * On 440EP with no internal SRAM, we setup SDRAM very early
+	 * and copy the NAND_SPL to SDRAM and jump to it
+	 */
+	/* Clear Dcache to use as RAM */
+	addis	r3,r0,CFG_INIT_RAM_ADDR@h
+	ori	r3,r3,CFG_INIT_RAM_ADDR@l
+	addis	r4,r0,CFG_INIT_RAM_END@h
+	ori	r4,r4,CFG_INIT_RAM_END@l
+	rlwinm. r5,r4,0,27,31
+	rlwinm	r5,r4,27,5,31
+	beq	..d_ran3
+	addi	r5,r5,0x0001
+..d_ran3:
+	mtctr	r5
+..d_ag3:
+	dcbz	r0,r3
+	addi	r3,r3,32
+	bdnz	..d_ag3
+	/*----------------------------------------------------------------*/
+	/* Setup the stack in internal SRAM */
+	/*----------------------------------------------------------------*/
+	lis	r1,CFG_INIT_RAM_ADDR@h
+	ori	r1,r1,CFG_INIT_SP_OFFSET@l
+	li	r0,0
+	stwu	r0,-4(r1)
+	stwu	r0,-4(r1)		/* Terminate call chain */
  
+	stwu	r1,-8(r1)		/* Save back chain and move SP */
+	lis	r0,RESET_VECTOR@h	/* Address of reset vector */
+	ori	r0,r0, RESET_VECTOR@l
+	stwu	r1,-8(r1)		/* Save back chain and move SP */
+	stw	r0,+12(r1)		/* Save return addr (underflow vect) */
+	sync
+	bl	early_sdram_init
+	sync
+#endif /* CONFIG_440EP */
+
 	/*
 	 * Copy SPL from cache into internal SRAM
 	 */
@@ -429,7 +476,7 @@
 start_ram:
 	sync
 	isync
-#endif
+#endif /* CONFIG_NAND_SPL */
  
 	bl	3f
 	b	_start
@@ -1137,7 +1184,6 @@
 	lwz	r1,GPR1(r1)
 	SYNC
 	rfci
-#endif /* CONFIG_NAND_SPL */
  
 /* Cache functions.
 */
@@ -1255,24 +1301,6 @@
 	blr
  
 /*------------------------------------------------------------------------------- */
-/* Function:	 in8 */
-/* Description:	 Input 8 bits */
-/*------------------------------------------------------------------------------- */
-	.globl	in8
-in8:
-	lbz	r3,0x0000(r3)
-	blr
-
-/*------------------------------------------------------------------------------- */
-/* Function:	 out8 */
-/* Description:	 Output 8 bits */
-/*------------------------------------------------------------------------------- */
-	.globl	out8
-out8:
-	stb	r4,0x0000(r3)
-	blr
-
-/*------------------------------------------------------------------------------- */
 /* Function:	 out16 */
 /* Description:	 Output 16 bits */
 /*------------------------------------------------------------------------------- */
@@ -1291,15 +1319,6 @@
 	blr
  
 /*------------------------------------------------------------------------------- */
-/* Function:	 out32 */
-/* Description:	 Output 32 bits */
-/*------------------------------------------------------------------------------- */
-	.globl	out32
-out32:
-	stw	r4,0x0000(r3)
-	blr
-
-/*------------------------------------------------------------------------------- */
 /* Function:	 out32r */
 /* Description:	 Byte reverse and output 32 bits */
 /*------------------------------------------------------------------------------- */
@@ -1327,15 +1346,6 @@
 	blr
  
 /*------------------------------------------------------------------------------- */
-/* Function:	 in32 */
-/* Description:	 Input 32 bits */
-/*------------------------------------------------------------------------------- */
-	.globl	in32
-in32:
-	lwz	3,0x0000(3)
-	blr
-
-/*------------------------------------------------------------------------------- */
 /* Function:	 in32r */
 /* Description:	 Input 32 bits and byte reverse */
 /*------------------------------------------------------------------------------- */
@@ -1377,9 +1387,6 @@
 	sync
 	blr
  
-/*------------------------------------------------------------------------------*/
-
-#ifndef CONFIG_NAND_SPL
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
  *
  
  
@@ -1644,9 +1651,89 @@
 	stw	r0, 4(r7)
  
 	blr
+
+#if defined(CONFIG_440)
+/*----------------------------------------------------------------------------+
+| dcbz_area.
++----------------------------------------------------------------------------*/
+	function_prolog(dcbz_area)
+	rlwinm. r5,r4,0,27,31
+	rlwinm  r5,r4,27,5,31
+	beq     ..d_ra2
+	addi    r5,r5,0x0001
+..d_ra2:mtctr   r5
+..d_ag2:dcbz    r0,r3
+	addi    r3,r3,32
+	bdnz    ..d_ag2
+	sync
+	blr
+	function_epilog(dcbz_area)
+
+/*----------------------------------------------------------------------------+
+| dflush.  Assume 32K at vector address is cachable.
++----------------------------------------------------------------------------*/
+	function_prolog(dflush)
+	mfmsr   r9
+	rlwinm  r8,r9,0,15,13
+	rlwinm  r8,r8,0,17,15
+	mtmsr   r8
+	addi    r3,r0,0x0000
+	mtspr   dvlim,r3
+	mfspr   r3,ivpr
+	addi    r4,r0,1024
+	mtctr   r4
+..dflush_loop:
+	lwz     r6,0x0(r3)
+	addi    r3,r3,32
+	bdnz    ..dflush_loop
+	addi    r3,r3,-32
+	mtctr   r4
+..ag:   dcbf    r0,r3
+	addi    r3,r3,-32
+	bdnz    ..ag
+	sync
+	mtmsr   r9
+	blr
+	function_epilog(dflush)
+#endif /* CONFIG_440 */
 #endif /* CONFIG_NAND_SPL */
  
+/*------------------------------------------------------------------------------- */
+/* Function:	 in8 */
+/* Description:	 Input 8 bits */
+/*------------------------------------------------------------------------------- */
+	.globl	in8
+in8:
+	lbz	r3,0x0000(r3)
+	blr
  
+/*------------------------------------------------------------------------------- */
+/* Function:	 out8 */
+/* Description:	 Output 8 bits */
+/*------------------------------------------------------------------------------- */
+	.globl	out8
+out8:
+	stb	r4,0x0000(r3)
+	blr
+
+/*------------------------------------------------------------------------------- */
+/* Function:	 out32 */
+/* Description:	 Output 32 bits */
+/*------------------------------------------------------------------------------- */
+	.globl	out32
+out32:
+	stw	r4,0x0000(r3)
+	blr
+
+/*------------------------------------------------------------------------------- */
+/* Function:	 in32 */
+/* Description:	 Input 32 bits */
+/*------------------------------------------------------------------------------- */
+	.globl	in32
+in32:
+	lwz	3,0x0000(3)
+	blr
+
 /**************************************************************************/
 /* PPC405EP specific stuff						  */
 /**************************************************************************/
@@ -1892,13 +1979,6 @@
 #endif /* CONFIG_405EP */
  
 #if defined(CONFIG_440)
-#define function_prolog(func_name)      .text; \
-					.align 2; \
-					.globl func_name; \
-					func_name:
-#define function_epilog(func_name)      .type func_name,@function; \
-					.size func_name,.-func_name
-
 /*----------------------------------------------------------------------------+
 | mttlb3.
 +----------------------------------------------------------------------------*/
@@ -1946,48 +2026,5 @@
 	TLBRE(3,3,0)
 	blr
 	function_epilog(mftlb1)
-
-/*----------------------------------------------------------------------------+
-| dcbz_area.
-+----------------------------------------------------------------------------*/
-	function_prolog(dcbz_area)
-	rlwinm. r5,r4,0,27,31
-	rlwinm  r5,r4,27,5,31
-	beq     ..d_ra2
-	addi    r5,r5,0x0001
-..d_ra2:mtctr   r5
-..d_ag2:dcbz    r0,r3
-	addi    r3,r3,32
-	bdnz    ..d_ag2
-	sync
-	blr
-	function_epilog(dcbz_area)
-
-/*----------------------------------------------------------------------------+
-| dflush.  Assume 32K at vector address is cachable.
-+----------------------------------------------------------------------------*/
-	function_prolog(dflush)
-	mfmsr   r9
-	rlwinm  r8,r9,0,15,13
-	rlwinm  r8,r8,0,17,15
-	mtmsr   r8
-	addi    r3,r0,0x0000
-	mtspr   dvlim,r3
-	mfspr   r3,ivpr
-	addi    r4,r0,1024
-	mtctr   r4
-..dflush_loop:
-	lwz     r6,0x0(r3)
-	addi    r3,r3,32
-	bdnz    ..dflush_loop
-	addi    r3,r3,-32
-	mtctr   r4
-..ag:   dcbf    r0,r3
-	addi    r3,r3,-32
-	bdnz    ..ag
-	sync
-	mtmsr   r9
-	blr
-	function_epilog(dflush)
 #endif /* CONFIG_440 */
@@ -50,7 +50,7 @@
  *----------------------------------------------------------------------*/
 #define CFG_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Monitor	*/
 #define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
-#define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)
+#define CFG_MONITOR_BASE	TEXT_BASE
 #define CFG_SDRAM_BASE	        0x00000000	    /* _must_ be 0	*/
 #define CFG_FLASH_BASE	        0xfff00000	    /* start of FLASH	*/
 #define CFG_PCI_MEMBASE	        0xa0000000	    /* mapped pci memory*/
  
@@ -104,14 +104,11 @@
 /*-----------------------------------------------------------------------
  * Environment
  *----------------------------------------------------------------------*/
-/*
- * Define here the location of the environment variables (FLASH or EEPROM).
- * Note: DENX encourages to use redundant environment in FLASH.
- */
-#if 1
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
 #else
-#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars	*/
+#define CFG_ENV_IS_IN_NAND	1	/* use NAND for environment vars	*/
+#define CFG_ENV_IS_EMBEDDED	1	/* use embedded environment */
 #endif
  
 /*-----------------------------------------------------------------------
@@ -133,7 +130,7 @@
  
 #ifdef CFG_ENV_IS_IN_FLASH
 #define CFG_ENV_SECT_SIZE	0x10000 	/* size of one complete sector	*/
-#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR		((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
 #define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
  
 /* Address and size of Redundant Environment Sector	*/
  
  
  
  
@@ -141,22 +138,89 @@
 #define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
 #endif /* CFG_ENV_IS_IN_FLASH */
  
+/*
+ * IPL (Initial Program Loader, integrated inside CPU)
+ * Will load first 4k from NAND (SPL) into cache and execute it from there.
+ *
+ * SPL (Secondary Program Loader)
+ * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
+ * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
+ * controller and the NAND controller so that the special U-Boot image can be
+ * loaded from NAND to SDRAM.
+ *
+ * NUB (NAND U-Boot)
+ * This NAND U-Boot (NUB) is a special U-Boot version which can be started
+ * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
+ *
+ * On 440EPx the SPL is copied to SDRAM before the NAND controller is
+ * set up. While still running from cache, I experienced problems accessing
+ * the NAND controller.	sr - 2006-08-25
+ */
+#define CFG_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location			*/
+#define CFG_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size			*/
+#define CFG_NAND_BOOT_SPL_DST	0x00800000	/* Copy SPL here		*/
+#define CFG_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr	*/
+#define CFG_NAND_U_BOOT_START	CFG_NAND_U_BOOT_DST /* Start NUB from this addr	*/
+#define CFG_NAND_BOOT_SPL_DELTA	(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
+
+/*
+ * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
+ */
+#define CFG_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image	*/
+#define CFG_NAND_U_BOOT_SIZE	(384 << 10)	/* Size of RAM U-Boot image	*/
+
+/*
+ * Now the NAND chip has to be defined (no autodetection used!)
+ */
+#define CFG_NAND_PAGE_SIZE	512		/* NAND chip page size		*/
+#define CFG_NAND_BLOCK_SIZE	(16 << 10)	/* NAND chip block size		*/
+#define CFG_NAND_PAGE_COUNT	32		/* NAND chip page count		*/
+#define CFG_NAND_BAD_BLOCK_POS	5		/* Location of bad block marker	*/
+#define CFG_NAND_4_ADDR_CYCLE	1		/* Fourth addr used (>32MB)	*/
+
+#define CFG_NAND_ECCSIZE	256
+#define CFG_NAND_ECCBYTES	3
+#define CFG_NAND_ECCSTEPS	(CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
+#define CFG_NAND_OOBSIZE	16
+#define CFG_NAND_ECCTOTAL	(CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
+#define CFG_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}
+
+#ifdef CFG_ENV_IS_IN_NAND
+/*
+ * For NAND booting the environment is embedded in the U-Boot image. Please take
+ * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
+ */
+#define CFG_ENV_SIZE		CFG_NAND_BLOCK_SIZE
+#define CFG_ENV_OFFSET		(CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET + CFG_ENV_SIZE)
+#endif
+
 /*-----------------------------------------------------------------------
  * NAND FLASH
  *----------------------------------------------------------------------*/
-#define CFG_MAX_NAND_DEVICE	1
-#define NAND_MAX_CHIPS		1
-#define CFG_NAND_CS		1
+#define CFG_MAX_NAND_DEVICE	2
+#define NAND_MAX_CHIPS		CFG_MAX_NAND_DEVICE
 #define CFG_NAND_BASE		(CFG_NAND_ADDR + CFG_NAND_CS)
+#define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE, CFG_NAND_ADDR + 2 }
 #define CFG_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips	*/
  
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define CFG_NAND_CS		1
+#else
+#define CFG_NAND_CS		0		/* NAND chip connected to CSx	*/
+/* Memory Bank 0 (NAND-FLASH) initialization					*/
+#define CFG_EBC_PB0AP		0x018003c0
+#define CFG_EBC_PB0CR		(CFG_NAND_ADDR | 0x1c000)
+#endif
+
 /*-----------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------------- */
 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup             */
 #undef CONFIG_DDR_ECC			/* don't use ECC			*/
 #define CFG_SIMULATE_SPD_EEPROM	0xff	/* simulate spd eeprom on this address	*/
-#define SPD_EEPROM_ADDRESS      {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51}
+#define SPD_EEPROM_ADDRESS	{CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51}
+#define CFG_MBYTES_SDRAM	(64)	/* 64MB fixed size for early-sdram-init */
  
 /*-----------------------------------------------------------------------
  * I2C
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDFLAGS	= -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+AFLAGS	+= -DCONFIG_NAND_SPL
+CFLAGS	+= -DCONFIG_NAND_SPL
+
+SOBJS	= start.o init.o resetvec.o
+COBJS	= nand_boot.o nand_ecc.o ndfc.o sdram.o
+
+SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS	:= $(SOBJS) $(COBJS)
+LNDIR	:= $(OBJTREE)/nand_spl/board/$(BOARDDIR)
+
+nandobj	:= $(OBJTREE)/nand_spl/
+
+ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+
+all:	$(obj).depend $(ALL)
+
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
+	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+
+$(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
+	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl:	$(OBJS)
+	cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
+		-Map $(nandobj)u-boot-spl.map \
+		-o $(nandobj)u-boot-spl
+
+# create symbolic links for common files
+
+# from cpu directory
+$(obj)ndfc.c:
+	@rm -f $(obj)ndfc.c
+	ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c
+
+$(obj)resetvec.S:
+	@rm -f $(obj)resetvec.S
+	ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
+
+$(obj)start.S:
+	@rm -f $(obj)start.S
+	ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S
+
+# from board directory
+$(obj)init.S:
+	@rm -f $(obj)init.S
+	ln -s $(SRCTREE)/board/amcc/bamboo/init.S $(obj)init.S
+
+# from nand_spl directory
+$(obj)nand_boot.c:
+	@rm -f $(obj)nand_boot.c
+	ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
+
+# from drivers/nand directory
+$(obj)nand_ecc.c:
+	@rm -f $(obj)nand_ecc.c
+	ln -s $(SRCTREE)/drivers/nand/nand_ecc.c $(obj)nand_ecc.c
+
+#########################################################################
+
+$(obj)%.o:	$(obj)%.S
+	$(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o:	$(obj)%.c
+	$(CC) $(CFLAGS) -c -o $@ $<
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# AMCC 440EP Reference Platform (Bamboo) board
+#
+
+#
+# TEXT_BASE for SPL:
+#
+# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff,
+# in the last 4kBytes of memory space in cache.
+# We will copy this SPL into instruction-cache in start.S. So we set
+# TEXT_BASE to starting address in i-cache here.
+#
+TEXT_BASE = 0x00800000
+
+# PAD_TO used to generate a 16kByte binary needed for the combined image
+# -> PAD_TO = TEXT_BASE + 0x4000
+PAD_TO	= 0x00804000
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+static void wait_init_complete(void)
+{
+	u32 val;
+
+	do {
+		mfsdram(mem_mcsts, val);
+	} while (!(val & 0x80000000));
+}
+
+/*
+ * early_sdram_init()
+ *
+ * As the name already indicates, this function is called very early
+ * from start.S and configures the SDRAM with fixed values. This is needed,
+ * since the 440EP has no internal SRAM and the 4kB NAND_SPL loader has
+ * not enough free space to implement the complete I2C SPD DDR autodetection
+ * routines. Therefore the Bamboo only supports the onboard 64MBytes of SDRAM
+ * when booting from NAND flash.
+ */
+void early_sdram_init(void)
+{
+	/*
+	 * Soft-reset SDRAM controller.
+	 */
+	mtsdr(sdr_srst, SDR0_SRST_DMC);
+	mtsdr(sdr_srst, 0x00000000);
+
+	/*
+	 * Disable memory controller.
+	 */
+	mtsdram(mem_cfg0, 0x00000000);
+
+	/*
+	 * Setup some default
+	 */
+	mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default)		*/
+	mtsdram(mem_slio, 0x00000000);	/* rdre=0 wrre=0 rarw=0		*/
+	mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal)		*/
+	mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0		*/
+	mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0	*/
+
+	/*
+	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
+	 */
+	mtsdram(mem_b0cr, 0x00082001);
+	mtsdram(mem_tr0, 0x41094012);
+	mtsdram(mem_tr1, 0x8080083d);	/* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
+	mtsdram(mem_rtr, 0x04100000);	/* Interval 7.8µs @ 133MHz PLB	*/
+	mtsdram(mem_cfg1, 0x00000000);	/* Self-refresh exit, disable PM*/
+
+	/*
+	 * Enable the controller, then wait for DCEN to complete
+	 */
+	mtsdram(mem_cfg0, 0x80000000); /* DCEN=1, PMUD=0*/
+	wait_init_complete();
+}
+
+long int initdram(int board_type)
+{
+	/*
+	 * Nothing to do here, just return size of fixed SDRAM setup
+	 */
+	return CFG_MBYTES_SDRAM << 20;
+}
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc:common)
+SECTIONS
+{
+  .resetvec 0x00800FFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .text      :
+  {
+    start.o	(.text)
+    init.o	(.text)
+    nand_boot.o	(.text)
+    sdram.o	(.text)
+    ndfc.o	(.text)
+
+    *(.text)
+    *(.fixup)
+  }
+  _etext = .;
+
+  .data    :
+  {
+    *(.rodata*)
+    *(.data*)
+    *(.sdata*)
+    __got2_start = .;
+    *(.got2)
+    __got2_end = .;
+  }
+
+  _edata  =  .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss)
+   *(.bss)
+  }
+
+  _end = . ;
+}
...	...	@@ -76,21 +76,21 @@
76	76
77	77	LIST_4xx=" \
78	78	acadia ADCIOP alpr AP1000 \
79		- AR405 ASH405 bamboo bubinga \
80		- CANBT CMS700 CPCI2DP CPCI405 \
81		- CPCI4052 CPCI405AB CPCI405DT CPCI440 \
82		- CPCIISER4 CRAYL1 csb272 csb472 \
83		- DASA_SIM DP405 DU405 ebony \
84		- ERIC EXBITGEN G2000 HH405 \
85		- HUB405 JSE KAREF katmai \
86		- luan METROBOX MIP405 MIP405T \
87		- ML2 ml300 ocotea OCRTC \
88		- ORSG p3p440 PCI405 pcs440ep \
89		- PIP405 PLU405 PMC405 PPChameleonEVB \
90		- sbc405 sc3 sequoia sequoia_nand \
91		- taishan VOH405 VOM405 W7OLMC \
92		- W7OLMG walnut WUH405 XPEDITE1K \
93		- yellowstone yosemite yucca \
	79	+ AR405 ASH405 bamboo bamboo_nand \
	80	+ bubinga CANBT CMS700 CPCI2DP \
	81	+ CPCI405 CPCI4052 CPCI405AB CPCI405DT \
	82	+ CPCI440 CPCIISER4 CRAYL1 csb272 \
	83	+ csb472 DASA_SIM DP405 DU405 \
	84	+ ebony ERIC EXBITGEN G2000 \
	85	+ HH405 HUB405 JSE KAREF \
	86	+ katmai luan METROBOX MIP405 \
	87	+ MIP405T ML2 ml300 ocotea \
	88	+ OCRTC ORSG p3p440 PCI405 \
	89	+ pcs440ep PIP405 PLU405 PMC405 \
	90	+ PPChameleonEVB sbc405 sc3 sequoia \
	91	+ sequoia_nand taishan VOH405 VOM405 \
	92	+ W7OLMC W7OLMG walnut WUH405 \
	93	+ XPEDITE1K yellowstone yosemite yucca \
94	94	"
95	95
96	96	#########################################################################
...	...	@@ -1035,6 +1035,16 @@
1035	1035	bamboo_config: unconfig
1036	1036	@$(MKCONFIG) $(@:_config=) ppc ppc4xx bamboo amcc
1037	1037
	1038	+bamboo_nand_config: unconfig
	1039	+ @mkdir -p $(obj)include
	1040	+ @mkdir -p $(obj)nand_spl
	1041	+ @mkdir -p $(obj)board/amcc/bamboo
	1042	+ @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
	1043	+ @echo "Compile NAND boot image for bamboo"
	1044	+ @$(MKCONFIG) -a bamboo ppc ppc4xx bamboo amcc
	1045	+ @echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/bamboo/config.tmp
	1046	+ @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
	1047	+
1038	1048	bubinga_config: unconfig
1039	1049	@$(MKCONFIG) $(@:_config=) ppc ppc4xx bubinga amcc
1040	1050
...	...	@@ -110,6 +110,13 @@
110	110	# endif
111	111	#endif /* CFG_INIT_DCACHE_CS */
112	112
	113	+#define function_prolog(func_name) .text; \
	114	+ .align 2; \
	115	+ .globl func_name; \
	116	+ func_name:
	117	+#define function_epilog(func_name) .type func_name,@function; \
	118	+ .size func_name,.-func_name
	119	+
113	120	/* We don't want the MMU yet.
114	121	*/
115	122	#undef MSR_KERNEL
116	123
...	...	@@ -388,8 +395,9 @@
388	395	2:
389	396
390	397	#if defined(CONFIG_NAND_SPL)
	398	+#if defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX)
391	399	/*
392		- * Enable internal SRAM
	400	+ * Enable internal SRAM (only on 440EPx/GRx, 440EP/GR have no OCM)
393	401	*/
394	402	lis r2,0x7fff
395	403	ori r2,r2,0xffff
396	404
...	...	@@ -399,7 +407,46 @@
399	407	mfdcr r1,isram0_pmeg
400	408	and r1,r1,r2 /* Disable pwr mgmt */
401	409	mtdcr isram0_pmeg,r1
	410	+#endif
	411	+#if defined(CONFIG_440EP)
	412	+ /*
	413	+ * On 440EP with no internal SRAM, we setup SDRAM very early
	414	+ * and copy the NAND_SPL to SDRAM and jump to it
	415	+ */
	416	+ /* Clear Dcache to use as RAM */
	417	+ addis r3,r0,CFG_INIT_RAM_ADDR@h
	418	+ ori r3,r3,CFG_INIT_RAM_ADDR@l
	419	+ addis r4,r0,CFG_INIT_RAM_END@h
	420	+ ori r4,r4,CFG_INIT_RAM_END@l
	421	+ rlwinm. r5,r4,0,27,31
	422	+ rlwinm r5,r4,27,5,31
	423	+ beq ..d_ran3
	424	+ addi r5,r5,0x0001
	425	+..d_ran3:
	426	+ mtctr r5
	427	+..d_ag3:
	428	+ dcbz r0,r3
	429	+ addi r3,r3,32
	430	+ bdnz ..d_ag3
	431	+ /----------------------------------------------------------------/
	432	+ /* Setup the stack in internal SRAM */
	433	+ /----------------------------------------------------------------/
	434	+ lis r1,CFG_INIT_RAM_ADDR@h
	435	+ ori r1,r1,CFG_INIT_SP_OFFSET@l
	436	+ li r0,0
	437	+ stwu r0,-4(r1)
	438	+ stwu r0,-4(r1) /* Terminate call chain */
402	439
	440	+ stwu r1,-8(r1) /* Save back chain and move SP */
	441	+ lis r0,RESET_VECTOR@h /* Address of reset vector */
	442	+ ori r0,r0, RESET_VECTOR@l
	443	+ stwu r1,-8(r1) /* Save back chain and move SP */
	444	+ stw r0,+12(r1) /* Save return addr (underflow vect) */
	445	+ sync
	446	+ bl early_sdram_init
	447	+ sync
	448	+#endif /* CONFIG_440EP */
	449	+
403	450	/*
404	451	* Copy SPL from cache into internal SRAM
405	452	*/
...	...	@@ -429,7 +476,7 @@
429	476	start_ram:
430	477	sync
431	478	isync
432		-#endif
	479	+#endif /* CONFIG_NAND_SPL */
433	480
434	481	bl 3f
435	482	b _start
...	...	@@ -1137,7 +1184,6 @@
1137	1184	lwz r1,GPR1(r1)
1138	1185	SYNC
1139	1186	rfci
1140		-#endif /* CONFIG_NAND_SPL */
1141	1187
1142	1188	/* Cache functions.
1143	1189	*/
...	...	@@ -1255,24 +1301,6 @@
1255	1301	blr
1256	1302
1257	1303	/------------------------------------------------------------------------------- /
1258		-/* Function: in8 */
1259		-/* Description: Input 8 bits */
1260		-/------------------------------------------------------------------------------- /
1261		- .globl in8
1262		-in8:
1263		- lbz r3,0x0000(r3)
1264		- blr
1265		-
1266		-/------------------------------------------------------------------------------- /
1267		-/* Function: out8 */
1268		-/* Description: Output 8 bits */
1269		-/------------------------------------------------------------------------------- /
1270		- .globl out8
1271		-out8:
1272		- stb r4,0x0000(r3)
1273		- blr
1274		-
1275		-/------------------------------------------------------------------------------- /
1276	1304	/* Function: out16 */
1277	1305	/* Description: Output 16 bits */
1278	1306	/------------------------------------------------------------------------------- /
...	...	@@ -1291,15 +1319,6 @@
1291	1319	blr
1292	1320
1293	1321	/------------------------------------------------------------------------------- /
1294		-/* Function: out32 */
1295		-/* Description: Output 32 bits */
1296		-/------------------------------------------------------------------------------- /
1297		- .globl out32
1298		-out32:
1299		- stw r4,0x0000(r3)
1300		- blr
1301		-
1302		-/------------------------------------------------------------------------------- /
1303	1322	/* Function: out32r */
1304	1323	/* Description: Byte reverse and output 32 bits */
1305	1324	/------------------------------------------------------------------------------- /
...	...	@@ -1327,15 +1346,6 @@
1327	1346	blr
1328	1347
1329	1348	/------------------------------------------------------------------------------- /
1330		-/* Function: in32 */
1331		-/* Description: Input 32 bits */
1332		-/------------------------------------------------------------------------------- /
1333		- .globl in32
1334		-in32:
1335		- lwz 3,0x0000(3)
1336		- blr
1337		-
1338		-/------------------------------------------------------------------------------- /
1339	1349	/* Function: in32r */
1340	1350	/* Description: Input 32 bits and byte reverse */
1341	1351	/------------------------------------------------------------------------------- /
...	...	@@ -1377,9 +1387,6 @@
1377	1387	sync
1378	1388	blr
1379	1389
1380		-/------------------------------------------------------------------------------/
1381		-
1382		-#ifndef CONFIG_NAND_SPL
1383	1390	/*
1384	1391	* void relocate_code (addr_sp, gd, addr_moni)
1385	1392	*
1386	1393
1387	1394
...	...	@@ -1644,9 +1651,89 @@
1644	1651	stw r0, 4(r7)
1645	1652
1646	1653	blr
	1654	+
	1655	+#if defined(CONFIG_440)
	1656	+/*----------------------------------------------------------------------------+
	1657	+\| dcbz_area.
	1658	++----------------------------------------------------------------------------*/
	1659	+ function_prolog(dcbz_area)
	1660	+ rlwinm. r5,r4,0,27,31
	1661	+ rlwinm r5,r4,27,5,31
	1662	+ beq ..d_ra2
	1663	+ addi r5,r5,0x0001
	1664	+..d_ra2:mtctr r5
	1665	+..d_ag2:dcbz r0,r3
	1666	+ addi r3,r3,32
	1667	+ bdnz ..d_ag2
	1668	+ sync
	1669	+ blr
	1670	+ function_epilog(dcbz_area)
	1671	+
	1672	+/*----------------------------------------------------------------------------+
	1673	+\| dflush. Assume 32K at vector address is cachable.
	1674	++----------------------------------------------------------------------------*/
	1675	+ function_prolog(dflush)
	1676	+ mfmsr r9
	1677	+ rlwinm r8,r9,0,15,13
	1678	+ rlwinm r8,r8,0,17,15
	1679	+ mtmsr r8
	1680	+ addi r3,r0,0x0000
	1681	+ mtspr dvlim,r3
	1682	+ mfspr r3,ivpr
	1683	+ addi r4,r0,1024
	1684	+ mtctr r4
	1685	+..dflush_loop:
	1686	+ lwz r6,0x0(r3)
	1687	+ addi r3,r3,32
	1688	+ bdnz ..dflush_loop
	1689	+ addi r3,r3,-32
	1690	+ mtctr r4
	1691	+..ag: dcbf r0,r3
	1692	+ addi r3,r3,-32
	1693	+ bdnz ..ag
	1694	+ sync
	1695	+ mtmsr r9
	1696	+ blr
	1697	+ function_epilog(dflush)
	1698	+#endif /* CONFIG_440 */
1647	1699	#endif /* CONFIG_NAND_SPL */
1648	1700
	1701	+/------------------------------------------------------------------------------- /
	1702	+/* Function: in8 */
	1703	+/* Description: Input 8 bits */
	1704	+/------------------------------------------------------------------------------- /
	1705	+ .globl in8
	1706	+in8:
	1707	+ lbz r3,0x0000(r3)
	1708	+ blr
1649	1709
	1710	+/------------------------------------------------------------------------------- /
	1711	+/* Function: out8 */
	1712	+/* Description: Output 8 bits */
	1713	+/------------------------------------------------------------------------------- /
	1714	+ .globl out8
	1715	+out8:
	1716	+ stb r4,0x0000(r3)
	1717	+ blr
	1718	+
	1719	+/------------------------------------------------------------------------------- /
	1720	+/* Function: out32 */
	1721	+/* Description: Output 32 bits */
	1722	+/------------------------------------------------------------------------------- /
	1723	+ .globl out32
	1724	+out32:
	1725	+ stw r4,0x0000(r3)
	1726	+ blr
	1727	+
	1728	+/------------------------------------------------------------------------------- /
	1729	+/* Function: in32 */
	1730	+/* Description: Input 32 bits */
	1731	+/------------------------------------------------------------------------------- /
	1732	+ .globl in32
	1733	+in32:
	1734	+ lwz 3,0x0000(3)
	1735	+ blr
	1736	+
1650	1737	/**************************************************************************/
1651	1738	/* PPC405EP specific stuff */
1652	1739	/**************************************************************************/
...	...	@@ -1892,13 +1979,6 @@
1892	1979	#endif /* CONFIG_405EP */
1893	1980
1894	1981	#if defined(CONFIG_440)
1895		-#define function_prolog(func_name) .text; \
1896		- .align 2; \
1897		- .globl func_name; \
1898		- func_name:
1899		-#define function_epilog(func_name) .type func_name,@function; \
1900		- .size func_name,.-func_name
1901		-
1902	1982	/*----------------------------------------------------------------------------+
1903	1983	\| mttlb3.
1904	1984	+----------------------------------------------------------------------------*/
...	...	@@ -1946,48 +2026,5 @@
1946	2026	TLBRE(3,3,0)
1947	2027	blr
1948	2028	function_epilog(mftlb1)
1949		-
1950		-/*----------------------------------------------------------------------------+
1951		-\| dcbz_area.
1952		-+----------------------------------------------------------------------------*/
1953		- function_prolog(dcbz_area)
1954		- rlwinm. r5,r4,0,27,31
1955		- rlwinm r5,r4,27,5,31
1956		- beq ..d_ra2
1957		- addi r5,r5,0x0001
1958		-..d_ra2:mtctr r5
1959		-..d_ag2:dcbz r0,r3
1960		- addi r3,r3,32
1961		- bdnz ..d_ag2
1962		- sync
1963		- blr
1964		- function_epilog(dcbz_area)
1965		-
1966		-/*----------------------------------------------------------------------------+
1967		-\| dflush. Assume 32K at vector address is cachable.
1968		-+----------------------------------------------------------------------------*/
1969		- function_prolog(dflush)
1970		- mfmsr r9
1971		- rlwinm r8,r9,0,15,13
1972		- rlwinm r8,r8,0,17,15
1973		- mtmsr r8
1974		- addi r3,r0,0x0000
1975		- mtspr dvlim,r3
1976		- mfspr r3,ivpr
1977		- addi r4,r0,1024
1978		- mtctr r4
1979		-..dflush_loop:
1980		- lwz r6,0x0(r3)
1981		- addi r3,r3,32
1982		- bdnz ..dflush_loop
1983		- addi r3,r3,-32
1984		- mtctr r4
1985		-..ag: dcbf r0,r3
1986		- addi r3,r3,-32
1987		- bdnz ..ag
1988		- sync
1989		- mtmsr r9
1990		- blr
1991		- function_epilog(dflush)
1992	2029	#endif /* CONFIG_440 */
...	...	@@ -50,7 +50,7 @@
50	50	----------------------------------------------------------------------/
51	51	#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
52	52	#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
53		-#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
	53	+#define CFG_MONITOR_BASE TEXT_BASE
54	54	#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
55	55	#define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */
56	56	#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
57	57
...	...	@@ -104,14 +104,11 @@
104	104	/*-----------------------------------------------------------------------
105	105	* Environment
106	106	----------------------------------------------------------------------/
107		-/*
108		- * Define here the location of the environment variables (FLASH or EEPROM).
109		- * Note: DENX encourages to use redundant environment in FLASH.
110		- */
111		-#if 1
	107	+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
112	108	#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
113	109	#else
114		-#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
	110	+#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
	111	+#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */
115	112	#endif
116	113
117	114	/*-----------------------------------------------------------------------
...	...	@@ -133,7 +130,7 @@
133	130
134	131	#ifdef CFG_ENV_IS_IN_FLASH
135	132	#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
136		-#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
	133	+#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
137	134	#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
138	135
139	136	/* Address and size of Redundant Environment Sector */
140	137
141	138
142	139
143	140
...	...	@@ -141,22 +138,89 @@
141	138	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
142	139	#endif /* CFG_ENV_IS_IN_FLASH */
143	140
	141	+/*
	142	+ * IPL (Initial Program Loader, integrated inside CPU)
	143	+ * Will load first 4k from NAND (SPL) into cache and execute it from there.
	144	+ *
	145	+ * SPL (Secondary Program Loader)
	146	+ * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
	147	+ * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
	148	+ * controller and the NAND controller so that the special U-Boot image can be
	149	+ * loaded from NAND to SDRAM.
	150	+ *
	151	+ * NUB (NAND U-Boot)
	152	+ * This NAND U-Boot (NUB) is a special U-Boot version which can be started
	153	+ * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
	154	+ *
	155	+ * On 440EPx the SPL is copied to SDRAM before the NAND controller is
	156	+ * set up. While still running from cache, I experienced problems accessing
	157	+ * the NAND controller. sr - 2006-08-25
	158	+ */
	159	+#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
	160	+#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
	161	+#define CFG_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */
	162	+#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
	163	+#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
	164	+#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
	165	+
	166	+/*
	167	+ * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
	168	+ */
	169	+#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
	170	+#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
	171	+
	172	+/*
	173	+ * Now the NAND chip has to be defined (no autodetection used!)
	174	+ */
	175	+#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
	176	+#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
	177	+#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
	178	+#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
	179	+#define CFG_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */
	180	+
	181	+#define CFG_NAND_ECCSIZE 256
	182	+#define CFG_NAND_ECCBYTES 3
	183	+#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
	184	+#define CFG_NAND_OOBSIZE 16
	185	+#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
	186	+#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
	187	+
	188	+#ifdef CFG_ENV_IS_IN_NAND
	189	+/*
	190	+ * For NAND booting the environment is embedded in the U-Boot image. Please take
	191	+ * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
	192	+ */
	193	+#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE
	194	+#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
	195	+#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
	196	+#endif
	197	+
144	198	/*-----------------------------------------------------------------------
145	199	* NAND FLASH
146	200	----------------------------------------------------------------------/
147		-#define CFG_MAX_NAND_DEVICE 1
148		-#define NAND_MAX_CHIPS 1
149		-#define CFG_NAND_CS 1
	201	+#define CFG_MAX_NAND_DEVICE 2
	202	+#define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE
150	203	#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
	204	+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE, CFG_NAND_ADDR + 2 }
151	205	#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
152	206
	207	+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
	208	+#define CFG_NAND_CS 1
	209	+#else
	210	+#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
	211	+/* Memory Bank 0 (NAND-FLASH) initialization */
	212	+#define CFG_EBC_PB0AP 0x018003c0
	213	+#define CFG_EBC_PB0CR (CFG_NAND_ADDR \| 0x1c000)
	214	+#endif
	215	+
153	216	/*-----------------------------------------------------------------------
154	217	* DDR SDRAM
155	218	----------------------------------------------------------------------------- /
156	219	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
157	220	#undef CONFIG_DDR_ECC /* don't use ECC */
158	221	#define CFG_SIMULATE_SPD_EEPROM 0xff /* simulate spd eeprom on this address */
159		-#define SPD_EEPROM_ADDRESS {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51}
	222	+#define SPD_EEPROM_ADDRESS {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51}
	223	+#define CFG_MBYTES_SDRAM (64) /* 64MB fixed size for early-sdram-init */
160	224
161	225	/*-----------------------------------------------------------------------
162	226	* I2C
	1	+#
	2	+# (C) Copyright 2007
	3	+# Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	+#
	5	+# See file CREDITS for list of people who contributed to this
	6	+# project.
	7	+#
	8	+# This program is free software; you can redistribute it and/or
	9	+# modify it under the terms of the GNU General Public License as
	10	+# published by the Free Software Foundation; either version 2 of
	11	+# the License, or (at your option) any later version.
	12	+#
	13	+# This program is distributed in the hope that it will be useful,
	14	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+# GNU General Public License for more details.
	17	+#
	18	+# You should have received a copy of the GNU General Public License
	19	+# along with this program; if not, write to the Free Software
	20	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+# MA 02111-1307 USA
	22	+#
	23	+
	24	+include $(TOPDIR)/config.mk
	25	+include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
	26	+
	27	+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
	28	+LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
	29	+AFLAGS += -DCONFIG_NAND_SPL
	30	+CFLAGS += -DCONFIG_NAND_SPL
	31	+
	32	+SOBJS = start.o init.o resetvec.o
	33	+COBJS = nand_boot.o nand_ecc.o ndfc.o sdram.o
	34	+
	35	+SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
	36	+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
	37	+__OBJS := $(SOBJS) $(COBJS)
	38	+LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
	39	+
	40	+nandobj := $(OBJTREE)/nand_spl/
	41	+
	42	+ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
	43	+
	44	+all: $(obj).depend $(ALL)
	45	+
	46	+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
	47	+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
	48	+
	49	+$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
	50	+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
	51	+
	52	+$(nandobj)u-boot-spl: $(OBJS)
	53	+ cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
	54	+ -Map $(nandobj)u-boot-spl.map \
	55	+ -o $(nandobj)u-boot-spl
	56	+
	57	+# create symbolic links for common files
	58	+
	59	+# from cpu directory
	60	+$(obj)ndfc.c:
	61	+ @rm -f $(obj)ndfc.c
	62	+ ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c
	63	+
	64	+$(obj)resetvec.S:
	65	+ @rm -f $(obj)resetvec.S
	66	+ ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
	67	+
	68	+$(obj)start.S:
	69	+ @rm -f $(obj)start.S
	70	+ ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S
	71	+
	72	+# from board directory
	73	+$(obj)init.S:
	74	+ @rm -f $(obj)init.S
	75	+ ln -s $(SRCTREE)/board/amcc/bamboo/init.S $(obj)init.S
	76	+
	77	+# from nand_spl directory
	78	+$(obj)nand_boot.c:
	79	+ @rm -f $(obj)nand_boot.c
	80	+ ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
	81	+
	82	+# from drivers/nand directory
	83	+$(obj)nand_ecc.c:
	84	+ @rm -f $(obj)nand_ecc.c
	85	+ ln -s $(SRCTREE)/drivers/nand/nand_ecc.c $(obj)nand_ecc.c
	86	+
	87	+#########################################################################
	88	+
	89	+$(obj)%.o: $(obj)%.S
	90	+ $(CC) $(AFLAGS) -c -o $@ $<
	91	+
	92	+$(obj)%.o: $(obj)%.c
	93	+ $(CC) $(CFLAGS) -c -o $@ $<
	94	+
	95	+# defines $(obj).depend target
	96	+include $(SRCTREE)/rules.mk
	97	+
	98	+sinclude $(obj).depend
	99	+
	100	+#########################################################################
	1	+/*
	2	+ * (C) Copyright 2007
	3	+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+#include <common.h>
	25	+#include <ppc4xx.h>
	26	+#include <asm/processor.h>
	27	+#include <asm/io.h>
	28	+
	29	+static void wait_init_complete(void)
	30	+{
	31	+ u32 val;
	32	+
	33	+ do {
	34	+ mfsdram(mem_mcsts, val);
	35	+ } while (!(val & 0x80000000));
	36	+}
	37	+
	38	+/*
	39	+ * early_sdram_init()
	40	+ *
	41	+ * As the name already indicates, this function is called very early
	42	+ * from start.S and configures the SDRAM with fixed values. This is needed,
	43	+ * since the 440EP has no internal SRAM and the 4kB NAND_SPL loader has
	44	+ * not enough free space to implement the complete I2C SPD DDR autodetection
	45	+ * routines. Therefore the Bamboo only supports the onboard 64MBytes of SDRAM
	46	+ * when booting from NAND flash.
	47	+ */
	48	+void early_sdram_init(void)
	49	+{
	50	+ /*
	51	+ * Soft-reset SDRAM controller.
	52	+ */
	53	+ mtsdr(sdr_srst, SDR0_SRST_DMC);
	54	+ mtsdr(sdr_srst, 0x00000000);
	55	+
	56	+ /*
	57	+ * Disable memory controller.
	58	+ */
	59	+ mtsdram(mem_cfg0, 0x00000000);
	60	+
	61	+ /*
	62	+ * Setup some default
	63	+ */
	64	+ mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
	65	+ mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
	66	+ mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
	67	+ mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
	68	+ mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
	69	+
	70	+ /*
	71	+ * Following for CAS Latency = 2.5 @ 133 MHz PLB
	72	+ */
	73	+ mtsdram(mem_b0cr, 0x00082001);
	74	+ mtsdram(mem_tr0, 0x41094012);
	75	+ mtsdram(mem_tr1, 0x8080083d); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
	76	+ mtsdram(mem_rtr, 0x04100000); /* Interval 7.8µs @ 133MHz PLB */
	77	+ mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/
	78	+
	79	+ /*
	80	+ * Enable the controller, then wait for DCEN to complete
	81	+ */
	82	+ mtsdram(mem_cfg0, 0x80000000); /* DCEN=1, PMUD=0*/
	83	+ wait_init_complete();
	84	+}
	85	+
	86	+long int initdram(int board_type)
	87	+{
	88	+ /*
	89	+ * Nothing to do here, just return size of fixed SDRAM setup
	90	+ */
	91	+ return CFG_MBYTES_SDRAM << 20;
	92	+}