Eric Lee / smarc-uboot

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Commit cfa1bd0774eafcba4791bad4d66f01b8f0dc6f94

Authored by Tom Rini
2 parents 11ada9225a 40bbd52a79
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

Merge git://git.denx.de/u-boot-ti

Showing 41 changed files Side-by-side Diff

arch/arm/cpu/armv7/am33xx/sys_info.c
Diff comments   View file @ cfa1bd0
... ... @@ -18,6 +18,7 @@
18 18 #include <asm/arch/cpu.h>
19 19 #include <asm/arch/clock.h>
20 20 #include <power/tps65910.h>
  21 +#include <linux/compiler.h>
21 22  
22 23 struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
23 24  
24 25  
25 26  
... ... @@ -51,11 +52,11 @@
51 52  
52 53 /**
53 54 * get_board_rev() - setup to pass kernel board revision information
54   - * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
  55 + * returns: 0 for the ATAG REVISION tag value.
55 56 */
56   -u32 get_board_rev(void)
  57 +u32 __weak get_board_rev(void)
57 58 {
58   - return BOARD_REV_ID;
  59 + return 0;
59 60 }
60 61  
61 62 /**
arch/arm/cpu/armv7/omap3/Kconfig
Diff comments   View file @ cfa1bd0
... ... @@ -22,6 +22,9 @@
22 22 bool "CompuLab CM-T3530 and CM-T3730 boards"
23 23 select SUPPORT_SPL
24 24  
  25 +config TARGET_CM_T3517
  26 + bool "CompuLab CM-T3517 boards"
  27 +
25 28 config TARGET_DEVKIT8000
26 29 bool "TimLL OMAP3 Devkit8000"
27 30 select SUPPORT_SPL
... ... @@ -98,6 +101,7 @@
98 101 source "board/ti/sdp3430/Kconfig"
99 102 source "board/ti/beagle/Kconfig"
100 103 source "board/compulab/cm_t35/Kconfig"
  104 +source "board/compulab/cm_t3517/Kconfig"
101 105 source "board/timll/devkit8000/Kconfig"
102 106 source "board/ti/evm/Kconfig"
103 107 source "board/isee/igep00x0/Kconfig"
arch/arm/include/asm/arch-am33xx/sys_proto.h
Diff comments   View file @ cfa1bd0
... ... @@ -14,8 +14,6 @@
14 14 #include <asm/ti-common/sys_proto.h>
15 15 #include <asm/arch/cpu.h>
16 16  
17   -#define BOARD_REV_ID 0x0
18   -
19 17 u32 get_cpu_rev(void);
20 18 u32 get_sysboot_value(void);
21 19  
arch/arm/include/asm/arch-keystone/hardware-k2e.h
Diff comments   View file @ cfa1bd0
... ... @@ -57,8 +57,6 @@
57 57 #define KS2_NETCP_PDMA_SCHED_BASE 0x24186100
58 58 #define KS2_NETCP_PDMA_RX_FLOW_BASE 0x24189000
59 59 #define KS2_NETCP_PDMA_RX_FLOW_NUM 96
60   -#define KS2_NETCP_PDMA_RX_FREE_QUEUE 4001
61   -#define KS2_NETCP_PDMA_RX_RCV_QUEUE 4002
62 60 #define KS2_NETCP_PDMA_TX_SND_QUEUE 896
63 61  
64 62 /* NETCP */
arch/arm/include/asm/arch-keystone/hardware-k2hk.h
Diff comments   View file @ cfa1bd0
... ... @@ -98,8 +98,6 @@
98 98 #define KS2_NETCP_PDMA_SCHED_BASE 0x02004c00
99 99 #define KS2_NETCP_PDMA_RX_FLOW_BASE 0x02005000
100 100 #define KS2_NETCP_PDMA_RX_FLOW_NUM 32
101   -#define KS2_NETCP_PDMA_RX_FREE_QUEUE 4001
102   -#define KS2_NETCP_PDMA_RX_RCV_QUEUE 4002
103 101 #define KS2_NETCP_PDMA_TX_SND_QUEUE 648
104 102  
105 103 /* NETCP */
arch/arm/include/asm/arch-keystone/hardware-k2l.h
Diff comments   View file @ cfa1bd0
... ... @@ -84,6 +84,10 @@
84 84 /* OSR memory size */
85 85 #define KS2_OSR_SIZE 0x100000
86 86  
  87 +/* SGMII SerDes */
  88 +#define KS2_SGMII_SERDES2_BASE 0x02320000
  89 +#define KS2_LANES_PER_SGMII_SERDES 2
  90 +
87 91 /* Number of DSP cores */
88 92 #define KS2_NUM_DSPS 4
89 93  
... ... @@ -97,6 +101,9 @@
97 101 #define KS2_NETCP_PDMA_RX_FLOW_BASE 0x26189000
98 102 #define KS2_NETCP_PDMA_RX_FLOW_NUM 96
99 103 #define KS2_NETCP_PDMA_TX_SND_QUEUE 896
  104 +
  105 +/* NETCP */
  106 +#define KS2_NETCP_BASE 0x26000000
100 107  
101 108 #endif /* __ASM_ARCH_HARDWARE_K2L_H */
arch/arm/include/asm/arch-keystone/hardware.h
Diff comments   View file @ cfa1bd0
... ... @@ -122,6 +122,10 @@
122 122 #define KS2_EDMA_QEESR 0x108c
123 123 #define KS2_EDMA_PARAM_1(x) (0x4020 + (4 * x))
124 124  
  125 +/* NETCP pktdma */
  126 +#define KS2_NETCP_PDMA_RX_FREE_QUEUE 4001
  127 +#define KS2_NETCP_PDMA_RX_RCV_QUEUE 4002
  128 +
125 129 /* Chip Interrupt Controller */
126 130 #define KS2_CIC2_BASE 0x02608000
127 131  
board/compulab/cm_t35/cm_t35.c
Diff comments   View file @ cfa1bd0
... ... @@ -19,12 +19,11 @@
19 19 #include <i2c.h>
20 20 #include <usb.h>
21 21 #include <mmc.h>
22   -#include <nand.h>
23 22 #include <twl4030.h>
24   -#include <bmp_layout.h>
25 23 #include <linux/compiler.h>
26 24  
27 25 #include <asm/io.h>
  26 +#include <asm/errno.h>
28 27 #include <asm/arch/mem.h>
29 28 #include <asm/arch/mux.h>
30 29 #include <asm/arch/mmc_host_def.h>
... ... @@ -33,6 +32,7 @@
33 32 #include <asm/ehci-omap.h>
34 33 #include <asm/gpio.h>
35 34  
  35 +#include "../common/common.h"
36 36 #include "../common/eeprom.h"
37 37  
38 38 DECLARE_GLOBAL_DATA_PTR;
... ... @@ -43,58 +43,6 @@
43 43 "NAND",
44 44 };
45 45  
46   -static u32 gpmc_net_config[GPMC_MAX_REG] = {
47   - NET_GPMC_CONFIG1,
48   - NET_GPMC_CONFIG2,
49   - NET_GPMC_CONFIG3,
50   - NET_GPMC_CONFIG4,
51   - NET_GPMC_CONFIG5,
52   - NET_GPMC_CONFIG6,
53   - 0
54   -};
55   -
56   -#ifdef CONFIG_LCD
57   -#ifdef CONFIG_CMD_NAND
58   -static int splash_load_from_nand(u32 bmp_load_addr)
59   -{
60   - struct bmp_header *bmp_hdr;
61   - int res, splash_screen_nand_offset = 0x100000;
62   - size_t bmp_size, bmp_header_size = sizeof(struct bmp_header);
63   -
64   - if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp)
65   - goto splash_address_too_high;
66   -
67   - res = nand_read_skip_bad(&nand_info[nand_curr_device],
68   - splash_screen_nand_offset, &bmp_header_size,
69   - NULL, nand_info[nand_curr_device].size,
70   - (u_char *)bmp_load_addr);
71   - if (res < 0)
72   - return res;
73   -
74   - bmp_hdr = (struct bmp_header *)bmp_load_addr;
75   - bmp_size = le32_to_cpu(bmp_hdr->file_size);
76   -
77   - if (bmp_load_addr + bmp_size >= gd->start_addr_sp)
78   - goto splash_address_too_high;
79   -
80   - return nand_read_skip_bad(&nand_info[nand_curr_device],
81   - splash_screen_nand_offset, &bmp_size,
82   - NULL, nand_info[nand_curr_device].size,
83   - (u_char *)bmp_load_addr);
84   -
85   -splash_address_too_high:
86   - printf("Error: splashimage address too high. Data overwrites U-Boot "
87   - "and/or placed beyond DRAM boundaries.\n");
88   -
89   - return -1;
90   -}
91   -#else
92   -static inline int splash_load_from_nand(void)
93   -{
94   - return -1;
95   -}
96   -#endif /* CONFIG_CMD_NAND */
97   -
98 46 #ifdef CONFIG_SPL_BUILD
99 47 /*
100 48 * Routine: get_board_mem_timings
101 49  
102 50  
... ... @@ -111,24 +59,12 @@
111 59 }
112 60 #endif
113 61  
  62 +#define CM_T35_SPLASH_NAND_OFFSET 0x100000
  63 +
114 64 int splash_screen_prepare(void)
115 65 {
116   - char *env_splashimage_value;
117   - u32 bmp_load_addr;
118   -
119   - env_splashimage_value = getenv("splashimage");
120   - if (env_splashimage_value == NULL)
121   - return -1;
122   -
123   - bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16);
124   - if (bmp_load_addr == 0) {
125   - printf("Error: bad splashimage address specified\n");
126   - return -1;
127   - }
128   -
129   - return splash_load_from_nand(bmp_load_addr);
  66 + return cl_splash_screen_prepare(CM_T35_SPLASH_NAND_OFFSET);
130 67 }
131   -#endif /* CONFIG_LCD */
132 68  
133 69 /*
134 70 * Routine: board_init
135 71  
136 72  
137 73  
... ... @@ -154,34 +90,18 @@
154 90 return 0;
155 91 }
156 92  
157   -static u32 cm_t3x_rev;
158   -
159 93 /*
160 94 * Routine: get_board_rev
161 95 * Description: read system revision
162 96 */
163 97 u32 get_board_rev(void)
164 98 {
165   - if (!cm_t3x_rev)
166   - cm_t3x_rev = cl_eeprom_get_board_rev();
167   -
168   - return cm_t3x_rev;
  99 + return cl_eeprom_get_board_rev();
169 100 };
170 101  
171   -/*
172   - * Routine: misc_init_r
173   - * Description: display die ID
174   - */
175 102 int misc_init_r(void)
176 103 {
177   - u32 board_rev = get_board_rev();
178   - u32 rev_major = board_rev / 100;
179   - u32 rev_minor = board_rev - (rev_major * 100);
180   -
181   - if ((rev_minor / 10) * 10 == rev_minor)
182   - rev_minor = rev_minor / 10;
183   -
184   - printf("PCB: %u.%u\n", rev_major, rev_minor);
  104 + cl_print_pcb_info();
185 105 dieid_num_r();
186 106  
187 107 return 0;
188 108  
... ... @@ -462,37 +382,12 @@
462 382 }
463 383 #endif
464 384  
465   -/*
466   - * Routine: setup_net_chip_gmpc
467   - * Description: Setting up the configuration GPMC registers specific to the
468   - * Ethernet hardware.
469   - */
470   -static void setup_net_chip_gmpc(void)
471   -{
472   - struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
473   -
474   - enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5],
475   - CM_T3X_SMC911X_BASE, GPMC_SIZE_16M);
476   - enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4],
477   - SB_T35_SMC911X_BASE, GPMC_SIZE_16M);
478   -
479   - /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
480   - writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
481   -
482   - /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
483   - writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
484   -
485   - /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
486   - writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
487   - &ctrl_base->gpmc_nadv_ale);
488   -}
489   -
490 385 #ifdef CONFIG_SYS_I2C_OMAP34XX
491 386 /*
492 387 * Routine: reset_net_chip
493 388 * Description: reset the Ethernet controller via TPS65930 GPIO
494 389 */
495   -static void reset_net_chip(void)
  390 +static int cm_t3x_reset_net_chip(int gpio)
496 391 {
497 392 /* Set GPIO1 of TPS65930 as output */
498 393 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x03,
499 394  
... ... @@ -507,9 +402,10 @@
507 402 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C,
508 403 0x02);
509 404 mdelay(1);
  405 + return 0;
510 406 }
511 407 #else
512   -static inline void reset_net_chip(void) {}
  408 +static inline int cm_t3x_reset_net_chip(int gpio) { return 0; }
513 409 #endif
514 410  
515 411 #ifdef CONFIG_SMC911X
... ... @@ -536,7 +432,6 @@
536 432 return eth_setenv_enetaddr("ethaddr", enetaddr);
537 433 }
538 434  
539   -
540 435 /*
541 436 * Routine: board_eth_init
542 437 * Description: initialize module and base-board Ethernet chips
543 438  
544 439  
... ... @@ -545,18 +440,16 @@
545 440 {
546 441 int rc = 0, rc1 = 0;
547 442  
548   - setup_net_chip_gmpc();
549   - reset_net_chip();
550   -
551 443 rc1 = handle_mac_address();
552 444 if (rc1)
553 445 printf("No MAC address found! ");
554 446  
555   - rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE);
  447 + rc1 = cl_omap3_smc911x_init(0, 5, CM_T3X_SMC911X_BASE,
  448 + cm_t3x_reset_net_chip, -EINVAL);
556 449 if (rc1 > 0)
557 450 rc++;
558 451  
559   - rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE);
  452 + rc1 = cl_omap3_smc911x_init(1, 4, SB_T35_SMC911X_BASE, NULL, -EINVAL);
560 453 if (rc1 > 0)
561 454 rc++;
562 455  
... ... @@ -564,16 +457,6 @@
564 457 }
565 458 #endif
566 459  
567   -void __weak get_board_serial(struct tag_serialnr *serialnr)
568   -{
569   - /*
570   - * This corresponds to what happens when we can communicate with the
571   - * eeprom but don't get a valid board serial value.
572   - */
573   - serialnr->low = 0;
574   - serialnr->high = 0;
575   -};
576   -
577 460 #ifdef CONFIG_USB_EHCI_OMAP
578 461 struct omap_usbhs_board_data usbhs_bdata = {
579 462 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
580 463  
581 464  
... ... @@ -583,22 +466,13 @@
583 466  
584 467 #define SB_T35_USB_HUB_RESET_GPIO 167
585 468 int ehci_hcd_init(int index, enum usb_init_type init,
586   - struct ehci_hccr **hccr, struct ehci_hcor **hcor)
  469 + struct ehci_hccr **hccr, struct ehci_hcor **hcor)
587 470 {
588 471 u8 val;
589 472 int offset;
590 473  
591   - if (gpio_request(SB_T35_USB_HUB_RESET_GPIO, "SB-T35 usb hub reset")) {
592   - printf("Error: can't obtain GPIO %d for SB-T35 usb hub reset",
593   - SB_T35_USB_HUB_RESET_GPIO);
594   - return -1;
595   - }
  474 + cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst");
596 475  
597   - gpio_direction_output(SB_T35_USB_HUB_RESET_GPIO, 0);
598   - udelay(10);
599   - gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1);
600   - udelay(1000);
601   -
602 476 offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1;
603 477 twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, offset, &val);
604 478 /* Set GPIO6 and GPIO7 of TPS65930 as output */
... ... @@ -614,6 +488,7 @@
614 488  
615 489 int ehci_hcd_stop(void)
616 490 {
  491 + cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO);
617 492 return omap_ehci_hcd_stop();
618 493 }
619 494 #endif /* CONFIG_USB_EHCI_OMAP */
board/compulab/cm_t3517/Kconfig
Diff comments   View file @ cfa1bd0
  1 +if TARGET_CM_T3517
  2 +
  3 +config SYS_BOARD
  4 + default "cm_t3517"
  5 +
  6 +config SYS_VENDOR
  7 + default "compulab"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "cm_t3517"
  11 +
  12 +endif
board/compulab/cm_t3517/MAINTAINERS
Diff comments   View file @ cfa1bd0
  1 +CM_T3517 BOARD
  2 +M: Igor Grinberg <grinberg@compulab.co.il>
  3 +S: Maintained
  4 +F: board/compulab/cm_t3517/
  5 +F: include/configs/cm_t3517.h
  6 +F: configs/cm_t3517_defconfig
board/compulab/cm_t3517/Makefile
Diff comments   View file @ cfa1bd0
  1 +#
  2 +# (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
  3 +#
  4 +# Authors: Igor Grinberg <grinberg@compulab.co.il>
  5 +#
  6 +# SPDX-License-Identifier: GPL-2.0+
  7 +#
  8 +
  9 +obj-y += cm_t3517.o mux.o
board/compulab/cm_t3517/cm_t3517.c
Diff comments   View file @ cfa1bd0
  1 +/*
  2 + * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
  3 + *
  4 + * Authors: Igor Grinberg <grinberg@compulab.co.il>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <status_led.h>
  11 +#include <net.h>
  12 +#include <netdev.h>
  13 +#include <usb.h>
  14 +#include <mmc.h>
  15 +#include <linux/compiler.h>
  16 +#include <linux/usb/musb.h>
  17 +
  18 +#include <asm/io.h>
  19 +#include <asm/arch/mem.h>
  20 +#include <asm/arch/am35x_def.h>
  21 +#include <asm/arch/mmc_host_def.h>
  22 +#include <asm/arch/sys_proto.h>
  23 +#include <asm/arch/musb.h>
  24 +#include <asm/omap_musb.h>
  25 +#include <asm/ehci-omap.h>
  26 +
  27 +#include "../common/common.h"
  28 +#include "../common/eeprom.h"
  29 +
  30 +DECLARE_GLOBAL_DATA_PTR;
  31 +
  32 +const omap3_sysinfo sysinfo = {
  33 + DDR_DISCRETE,
  34 + "CM-T3517 board",
  35 + "NAND 128/512M",
  36 +};
  37 +
  38 +#ifdef CONFIG_USB_MUSB_AM35X
  39 +static struct musb_hdrc_config cm_t3517_musb_config = {
  40 + .multipoint = 1,
  41 + .dyn_fifo = 1,
  42 + .num_eps = 16,
  43 + .ram_bits = 12,
  44 +};
  45 +
  46 +static struct omap_musb_board_data cm_t3517_musb_board_data = {
  47 + .set_phy_power = am35x_musb_phy_power,
  48 + .clear_irq = am35x_musb_clear_irq,
  49 + .reset = am35x_musb_reset,
  50 +};
  51 +
  52 +static struct musb_hdrc_platform_data cm_t3517_musb_pdata = {
  53 +#if defined(CONFIG_MUSB_HOST)
  54 + .mode = MUSB_HOST,
  55 +#elif defined(CONFIG_MUSB_GADGET)
  56 + .mode = MUSB_PERIPHERAL,
  57 +#else
  58 +#error "Please define either CONFIG_MUSB_HOST or CONFIG_MUSB_GADGET"
  59 +#endif
  60 + .config = &cm_t3517_musb_config,
  61 + .power = 250,
  62 + .platform_ops = &am35x_ops,
  63 + .board_data = &cm_t3517_musb_board_data,
  64 +};
  65 +
  66 +static void cm_t3517_musb_init(void)
  67 +{
  68 + /*
  69 + * Set up USB clock/mode in the DEVCONF2 register.
  70 + * USB2.0 PHY reference clock is 13 MHz
  71 + */
  72 + clrsetbits_le32(&am35x_scm_general_regs->devconf2,
  73 + CONF2_REFFREQ | CONF2_OTGMODE | CONF2_PHY_GPIOMODE,
  74 + CONF2_REFFREQ_13MHZ | CONF2_SESENDEN |
  75 + CONF2_VBDTCTEN | CONF2_DATPOL);
  76 +
  77 + if (musb_register(&cm_t3517_musb_pdata, &cm_t3517_musb_board_data,
  78 + (void *)AM35XX_IPSS_USBOTGSS_BASE))
  79 + printf("Failed initializing AM35x MUSB!\n");
  80 +}
  81 +#else
  82 +static inline void am3517_evm_musb_init(void) {}
  83 +#endif
  84 +
  85 +int board_init(void)
  86 +{
  87 + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
  88 +
  89 + /* boot param addr */
  90 + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
  91 +
  92 +#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
  93 + status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
  94 +#endif
  95 +
  96 + cm_t3517_musb_init();
  97 +
  98 + return 0;
  99 +}
  100 +
  101 +int misc_init_r(void)
  102 +{
  103 + cl_print_pcb_info();
  104 + dieid_num_r();
  105 +
  106 + return 0;
  107 +}
  108 +
  109 +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
  110 +#define SB_T35_CD_GPIO 144
  111 +#define SB_T35_WP_GPIO 59
  112 +
  113 +int board_mmc_init(bd_t *bis)
  114 +{
  115 + return omap_mmc_init(0, 0, 0, SB_T35_CD_GPIO, SB_T35_WP_GPIO);
  116 +}
  117 +#endif
  118 +
  119 +#ifdef CONFIG_DRIVER_TI_EMAC
  120 +#define CONTROL_EFUSE_EMAC_LSB 0x48002380
  121 +#define CONTROL_EFUSE_EMAC_MSB 0x48002384
  122 +
  123 +static int am3517_get_efuse_enetaddr(u8 *enetaddr)
  124 +{
  125 + u32 lsb = __raw_readl(CONTROL_EFUSE_EMAC_LSB);
  126 + u32 msb = __raw_readl(CONTROL_EFUSE_EMAC_MSB);
  127 +
  128 + enetaddr[0] = (u8)((msb >> 16) & 0xff);
  129 + enetaddr[1] = (u8)((msb >> 8) & 0xff);
  130 + enetaddr[2] = (u8)(msb & 0xff);
  131 + enetaddr[3] = (u8)((lsb >> 16) & 0xff);
  132 + enetaddr[4] = (u8)((lsb >> 8) & 0xff);
  133 + enetaddr[5] = (u8)(lsb & 0xff);
  134 +
  135 + return is_valid_ether_addr(enetaddr);
  136 +}
  137 +
  138 +static inline int cm_t3517_init_emac(bd_t *bis)
  139 +{
  140 + int ret = cpu_eth_init(bis);
  141 +
  142 + if (ret > 0)
  143 + return ret;
  144 +
  145 + printf("Failed initializing EMAC! ");
  146 + return 0;
  147 +}
  148 +#else /* !CONFIG_DRIVER_TI_EMAC */
  149 +static inline int am3517_get_efuse_enetaddr(u8 *enetaddr) { return 1; }
  150 +static inline int cm_t3517_init_emac(bd_t *bis) { return 0; }
  151 +#endif /* CONFIG_DRIVER_TI_EMAC */
  152 +
  153 +/*
  154 + * Routine: handle_mac_address
  155 + * Description: prepare MAC address for on-board Ethernet.
  156 + */
  157 +static int cm_t3517_handle_mac_address(void)
  158 +{
  159 + unsigned char enetaddr[6];
  160 + int ret;
  161 +
  162 + ret = eth_getenv_enetaddr("ethaddr", enetaddr);
  163 + if (ret)
  164 + return 0;
  165 +
  166 + ret = cl_eeprom_read_mac_addr(enetaddr);
  167 + if (ret) {
  168 + ret = am3517_get_efuse_enetaddr(enetaddr);
  169 + if (ret)
  170 + return ret;
  171 + }
  172 +
  173 + if (!is_valid_ether_addr(enetaddr))
  174 + return -1;
  175 +
  176 + return eth_setenv_enetaddr("ethaddr", enetaddr);
  177 +}
  178 +
  179 +#define SB_T35_ETH_RST_GPIO 164
  180 +
  181 +/*
  182 + * Routine: board_eth_init
  183 + * Description: initialize module and base-board Ethernet chips
  184 + */
  185 +int board_eth_init(bd_t *bis)
  186 +{
  187 + int rc = 0, rc1 = 0;
  188 +
  189 + rc1 = cm_t3517_handle_mac_address();
  190 + if (rc1)
  191 + printf("No MAC address found! ");
  192 +
  193 + rc1 = cm_t3517_init_emac(bis);
  194 + if (rc1 > 0)
  195 + rc++;
  196 +
  197 + rc1 = cl_omap3_smc911x_init(0, 4, CONFIG_SMC911X_BASE,
  198 + NULL, SB_T35_ETH_RST_GPIO);
  199 + if (rc1 > 0)
  200 + rc++;
  201 +
  202 + return rc;
  203 +}
  204 +
  205 +#ifdef CONFIG_USB_EHCI_OMAP
  206 +static struct omap_usbhs_board_data cm_t3517_usbhs_bdata = {
  207 + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
  208 + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
  209 + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
  210 +};
  211 +
  212 +#define CM_T3517_USB_HUB_RESET_GPIO 152
  213 +#define SB_T35_USB_HUB_RESET_GPIO 98
  214 +
  215 +int ehci_hcd_init(int index, enum usb_init_type init,
  216 + struct ehci_hccr **hccr, struct ehci_hcor **hcor)
  217 +{
  218 + cl_usb_hub_init(CM_T3517_USB_HUB_RESET_GPIO, "cm-t3517 hub rst");
  219 + cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst");
  220 +
  221 + return omap_ehci_hcd_init(index, &cm_t3517_usbhs_bdata, hccr, hcor);
  222 +}
  223 +
  224 +int ehci_hcd_stop(void)
  225 +{
  226 + cl_usb_hub_deinit(CM_T3517_USB_HUB_RESET_GPIO);
  227 + cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO);
  228 +
  229 + return omap_ehci_hcd_stop();
  230 +}
  231 +#endif /* CONFIG_USB_EHCI_OMAP */
board/compulab/cm_t3517/mux.c
Diff comments   View file @ cfa1bd0
  1 +/*
  2 + * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
  3 + *
  4 + * Authors: Igor Grinberg <grinberg@compulab.co.il>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <asm/arch/sys_proto.h>
  11 +#include <asm/arch/mux.h>
  12 +#include <asm/io.h>
  13 +
  14 +void set_muxconf_regs(void)
  15 +{
  16 + /* SDRC */
  17 + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0));
  18 + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0));
  19 + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0));
  20 + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0));
  21 + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0));
  22 + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0));
  23 + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0));
  24 + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0));
  25 + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0));
  26 + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0));
  27 + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0));
  28 + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0));
  29 + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0));
  30 + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0));
  31 + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0));
  32 + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0));
  33 + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0));
  34 + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0));
  35 + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0));
  36 + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0));
  37 + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0));
  38 + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0));
  39 + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0));
  40 + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0));
  41 + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0));
  42 + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0));
  43 + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0));
  44 + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0));
  45 + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0));
  46 + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0));
  47 + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0));
  48 + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0));
  49 + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0));
  50 + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0));
  51 + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0));
  52 + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0));
  53 + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0));
  54 + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0));
  55 + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7));
  56 +
  57 + /* GPMC */
  58 + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0));
  59 + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0));
  60 + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0));
  61 + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0));
  62 + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0));
  63 + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0));
  64 + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0));
  65 + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0));
  66 + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0));
  67 + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0));
  68 + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0));
  69 + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0));
  70 + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0));
  71 + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0));
  72 + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0));
  73 + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0));
  74 + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0));
  75 + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0));
  76 + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0));
  77 + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0));
  78 + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0));
  79 + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0));
  80 + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0));
  81 + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0));
  82 + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0));
  83 + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0));
  84 + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0));
  85 +
  86 + /* SB-T35 Ethernet */
  87 + MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0));
  88 + /* DVI enable */
  89 + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPIO_54*/
  90 + /* DataImage backlight */
  91 + MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/
  92 +
  93 + /* SB-T35 SD/MMC WP GPIO59 */
  94 + MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)); /*GPIO_59*/
  95 + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0));
  96 + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0));
  97 + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0));
  98 + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0));
  99 + /* SB-T35 Audio Enable GPIO61 */
  100 + MUX_VAL(CP(GPMC_NBE1), (IDIS | PTU | EN | M4)); /*GPIO_61*/
  101 + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
  102 + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0));
  103 + /* SB-T35 Ethernet IRQ GPIO65 */
  104 + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); /*GPIO_65*/
  105 +
  106 + /* UART3 Console */
  107 + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
  108 + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
  109 + /* RTC V3020 nCS GPIO163 */
  110 + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | EN | M4)); /*GPIO_163*/
  111 + /* SB-T35 Ethernet nRESET GPIO164 */
  112 + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)); /*GPIO_164*/
  113 +
  114 + /* SB-T35 SD/MMC CD GPIO144 */
  115 + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M4)); /*GPIO_144*/
  116 + /* WIFI nRESET GPIO145 */
  117 + MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M4)); /*GPIO_145*/
  118 + /* USB1 PHY Reset GPIO 146 */
  119 + MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M4)); /*GPIO_146*/
  120 + /* USB2 PHY Reset GPIO 147 */
  121 + MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M4)); /*GPIO_147*/
  122 +
  123 + /* MMC1 */
  124 + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0));
  125 + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0));
  126 + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0));
  127 + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0));
  128 + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0));
  129 + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0));
  130 +
  131 + /* DSS */
  132 + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0));
  133 + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0));
  134 + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0));
  135 + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0));
  136 + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0));
  137 + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0));
  138 + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0));
  139 + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0));
  140 + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0));
  141 + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0));
  142 + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0));
  143 + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0));
  144 + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0));
  145 + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0));
  146 + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0));
  147 + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0));
  148 + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0));
  149 + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0));
  150 + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0));
  151 + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0));
  152 + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0));
  153 + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0));
  154 + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0));
  155 + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0));
  156 + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0));
  157 + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0));
  158 + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0));
  159 + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0));
  160 +
  161 + /* I2C */
  162 + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0));
  163 + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0));
  164 + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0));
  165 + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0));
  166 +
  167 + /* SB-T35 USB HUB Reset GPIO98 */
  168 + MUX_VAL(CP(CCDC_WEN), (IDIS | PTU | EN | M4)); /*GPIO_98*/
  169 + /* CM-T3517 USB HUB Reset GPIO152 */
  170 + MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)); /*GPIO_152*/
  171 +
  172 + /* RMII */
  173 + MUX_VAL(CP(RMII_MDIO_DATA), (IEN | PTU | EN | M0));
  174 + MUX_VAL(CP(RMII_MDIO_CLK), (M0));
  175 + MUX_VAL(CP(RMII_RXD0), (IEN | PTD | DIS | M0));
  176 + MUX_VAL(CP(RMII_RXD1), (IEN | PTD | DIS | M0));
  177 + MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | DIS | M0));
  178 + MUX_VAL(CP(RMII_RXER), (IEN | PTD | DIS | M0));
  179 + MUX_VAL(CP(RMII_TXD0), (IDIS | M0));
  180 + MUX_VAL(CP(RMII_TXD1), (IDIS | M0));
  181 + MUX_VAL(CP(RMII_TXEN), (IDIS | M0));
  182 + MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTU | DIS | M0));
  183 +
  184 + /* Green LED GPIO186 */
  185 + MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*GPIO_186*/
  186 +
  187 + /* SPI */
  188 + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/
  189 + MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/
  190 + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/
  191 + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/
  192 + /* LCD reset GPIO157 */
  193 + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/
  194 +
  195 + /* RTC V3020 CS Enable GPIO160 */
  196 + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | EN | M4)); /*GPIO_160*/
  197 + /* SB-T35 LVDS Transmitter SHDN GPIO162 */
  198 + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | DIS | M4)); /*GPIO_162*/
  199 +
  200 + /* USB0 - mUSB */
  201 + MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0));
  202 + /* USB1 EHCI */
  203 + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/
  204 + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/
  205 + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/
  206 + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/
  207 + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/
  208 + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/
  209 + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/
  210 + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/
  211 + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/
  212 + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/
  213 + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/
  214 + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/
  215 + /* USB2 EHCI */
  216 + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/
  217 + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/
  218 + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/
  219 + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/
  220 + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/
  221 + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/
  222 + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/
  223 + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/
  224 + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/
  225 + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/
  226 + MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/
  227 + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/
  228 +
  229 + /* SYS_BOOT */
  230 + MUX_VAL(CP(SYS_BOOT0), (IEN | PTU | DIS | M4)); /*GPIO_2*/
  231 + MUX_VAL(CP(SYS_BOOT1), (IEN | PTU | DIS | M4)); /*GPIO_3*/
  232 + MUX_VAL(CP(SYS_BOOT2), (IEN | PTU | DIS | M4)); /*GPIO_4*/
  233 + MUX_VAL(CP(SYS_BOOT3), (IEN | PTU | DIS | M4)); /*GPIO_5*/
  234 + MUX_VAL(CP(SYS_BOOT4), (IEN | PTU | DIS | M4)); /*GPIO_6*/
  235 + MUX_VAL(CP(SYS_BOOT5), (IEN | PTU | DIS | M4)); /*GPIO_7*/
  236 +}
board/compulab/cm_t54/cm_t54.c
Diff comments   View file @ cfa1bd0
... ... @@ -100,16 +100,11 @@
100 100 #define SB_T54_CD_GPIO 228
101 101 #define SB_T54_WP_GPIO 229
102 102  
103   -int board_mmc_getcd(struct mmc *mmc)
104   -{
105   - return !gpio_get_value(SB_T54_CD_GPIO);
106   -}
107   -
108 103 int board_mmc_init(bd_t *bis)
109 104 {
110 105 int ret0, ret1;
111 106  
112   - ret0 = omap_mmc_init(0, 0, 0, -1, SB_T54_WP_GPIO);
  107 + ret0 = omap_mmc_init(0, 0, 0, SB_T54_CD_GPIO, SB_T54_WP_GPIO);
113 108 if (ret0)
114 109 printf("cm_t54: failed to initialize mmc0\n");
115 110  
board/compulab/common/Makefile
Diff comments   View file @ cfa1bd0
... ... @@ -6,6 +6,9 @@
6 6 # SPDX-License-Identifier: GPL-2.0+
7 7 #
8 8  
9   -obj-$(CONFIG_SYS_I2C) += eeprom.o
10   -obj-$(CONFIG_LCD) += omap3_display.o
  9 +obj-y += common.o
  10 +obj-$(CONFIG_SYS_I2C) += eeprom.o
  11 +obj-$(CONFIG_LCD) += omap3_display.o
  12 +obj-$(CONFIG_SPLASH_SCREEN) += splash.o
  13 +obj-$(CONFIG_SMC911X) += omap3_smc911x.o
board/compulab/common/common.c
Diff comments   View file @ cfa1bd0
  1 +/*
  2 + * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
  3 + *
  4 + * Authors: Igor Grinberg <grinberg@compulab.co.il>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <asm/bootm.h>
  11 +#include <asm/gpio.h>
  12 +
  13 +#include "common.h"
  14 +#include "eeprom.h"
  15 +
  16 +void cl_print_pcb_info(void)
  17 +{
  18 + u32 board_rev = get_board_rev();
  19 + u32 rev_major = board_rev / 100;
  20 + u32 rev_minor = board_rev - (rev_major * 100);
  21 +
  22 + if ((rev_minor / 10) * 10 == rev_minor)
  23 + rev_minor = rev_minor / 10;
  24 +
  25 + printf("PCB: %u.%u\n", rev_major, rev_minor);
  26 +}
  27 +
  28 +#ifdef CONFIG_SERIAL_TAG
  29 +void __weak get_board_serial(struct tag_serialnr *serialnr)
  30 +{
  31 + /*
  32 + * This corresponds to what happens when we can communicate with the
  33 + * eeprom but don't get a valid board serial value.
  34 + */
  35 + serialnr->low = 0;
  36 + serialnr->high = 0;
  37 +};
  38 +#endif
  39 +
  40 +#ifdef CONFIG_CMD_USB
  41 +int cl_usb_hub_init(int gpio, const char *label)
  42 +{
  43 + if (gpio_request(gpio, label)) {
  44 + printf("Error: can't obtain GPIO%d for %s", gpio, label);
  45 + return -1;
  46 + }
  47 +
  48 + gpio_direction_output(gpio, 0);
  49 + udelay(10);
  50 + gpio_set_value(gpio, 1);
  51 + udelay(1000);
  52 + return 0;
  53 +}
  54 +
  55 +void cl_usb_hub_deinit(int gpio)
  56 +{
  57 + gpio_free(gpio);
  58 +}
  59 +#endif
board/compulab/common/common.h
Diff comments   View file @ cfa1bd0
  1 +/*
  2 + * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
  3 + *
  4 + * Authors: Igor Grinberg <grinberg@compulab.co.il>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef _CL_COMMON_
  10 +#define _CL_COMMON_
  11 +
  12 +#include <asm/errno.h>
  13 +
  14 +void cl_print_pcb_info(void);
  15 +
  16 +#ifdef CONFIG_CMD_USB
  17 +int cl_usb_hub_init(int gpio, const char *label);
  18 +void cl_usb_hub_deinit(int gpio);
  19 +#else /* !CONFIG_CMD_USB */
  20 +static inline int cl_usb_hub_init(int gpio, const char *label)
  21 +{
  22 + return -ENOSYS;
  23 +}
  24 +static inline void cl_usb_hub_deinit(int gpio) {}
  25 +#endif /* CONFIG_CMD_USB */
  26 +
  27 +#ifdef CONFIG_SPLASH_SCREEN
  28 +int cl_splash_screen_prepare(int nand_offset);
  29 +#else /* !CONFIG_SPLASH_SCREEN */
  30 +static inline int cl_splash_screen_prepare(int nand_offset)
  31 +{
  32 + return -ENOSYS;
  33 +}
  34 +#endif /* CONFIG_SPLASH_SCREEN */
  35 +
  36 +#ifdef CONFIG_SMC911X
  37 +int cl_omap3_smc911x_init(int id, int cs, u32 base_addr,
  38 + int (*reset)(int), int rst_gpio);
  39 +#else /* !CONFIG_SMC911X */
  40 +static inline int cl_omap3_smc911x_init(int id, int cs, u32 base_addr,
  41 + int (*reset)(int), int rst_gpio)
  42 +{
  43 + return -ENOSYS;
  44 +}
  45 +#endif /* CONFIG_SMC911X */
  46 +
  47 +#endif /* _CL_COMMON_ */
board/compulab/common/eeprom.c
Diff comments   View file @ cfa1bd0
... ... @@ -109,23 +109,27 @@
109 109 return cl_eeprom_read(offset, buf, 6);
110 110 }
111 111  
  112 +static u32 board_rev;
  113 +
112 114 /*
113 115 * Routine: cl_eeprom_get_board_rev
114 116 * Description: read system revision from eeprom
115 117 */
116 118 u32 cl_eeprom_get_board_rev(void)
117 119 {
118   - u32 rev = 0;
119 120 char str[5]; /* Legacy representation can contain at most 4 digits */
120 121 uint offset = BOARD_REV_OFFSET_LEGACY;
121 122  
  123 + if (board_rev)
  124 + return board_rev;
  125 +
122 126 if (cl_eeprom_setup_layout())
123 127 return 0;
124 128  
125 129 if (cl_eeprom_layout != LAYOUT_LEGACY)
126 130 offset = BOARD_REV_OFFSET;
127 131  
128   - if (cl_eeprom_read(offset, (uchar *)&rev, BOARD_REV_SIZE))
  132 + if (cl_eeprom_read(offset, (uchar *)&board_rev, BOARD_REV_SIZE))
129 133 return 0;
130 134  
131 135 /*
132 136  
... ... @@ -133,10 +137,10 @@
133 137 * representation. i.e. for rev 1.00: 0x100 --> 0x64
134 138 */
135 139 if (cl_eeprom_layout == LAYOUT_LEGACY) {
136   - sprintf(str, "%x", rev);
137   - rev = simple_strtoul(str, NULL, 10);
  140 + sprintf(str, "%x", board_rev);
  141 + board_rev = simple_strtoul(str, NULL, 10);
138 142 }
139 143  
140   - return rev;
  144 + return board_rev;
141 145 };
board/compulab/common/omap3_smc911x.c
Diff comments   View file @ cfa1bd0
  1 +/*
  2 + * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
  3 + *
  4 + * Authors: Igor Grinberg <grinberg@compulab.co.il>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <netdev.h>
  11 +
  12 +#include <asm/io.h>
  13 +#include <asm/errno.h>
  14 +#include <asm/arch/cpu.h>
  15 +#include <asm/arch/mem.h>
  16 +#include <asm/arch/sys_proto.h>
  17 +#include <asm/gpio.h>
  18 +
  19 +#include "common.h"
  20 +
  21 +static u32 cl_omap3_smc911x_gpmc_net_config[GPMC_MAX_REG] = {
  22 + NET_GPMC_CONFIG1,
  23 + NET_GPMC_CONFIG2,
  24 + NET_GPMC_CONFIG3,
  25 + NET_GPMC_CONFIG4,
  26 + NET_GPMC_CONFIG5,
  27 + NET_GPMC_CONFIG6,
  28 + 0
  29 +};
  30 +
  31 +static void cl_omap3_smc911x_setup_net_chip_gmpc(int cs, u32 base_addr)
  32 +{
  33 + struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
  34 +
  35 + enable_gpmc_cs_config(cl_omap3_smc911x_gpmc_net_config,
  36 + &gpmc_cfg->cs[cs], base_addr, GPMC_SIZE_16M);
  37 +
  38 + /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
  39 + writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
  40 +
  41 + /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
  42 + writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
  43 +
  44 + /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
  45 + writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
  46 + &ctrl_base->gpmc_nadv_ale);
  47 +}
  48 +
  49 +#ifdef CONFIG_OMAP_GPIO
  50 +static int cl_omap3_smc911x_reset_net_chip(int gpio)
  51 +{
  52 + int err;
  53 +
  54 + if (!gpio_is_valid(gpio))
  55 + return -EINVAL;
  56 +
  57 + err = gpio_request(gpio, "eth rst");
  58 + if (err)
  59 + return err;
  60 +
  61 + /* Set gpio as output and send a pulse */
  62 + gpio_direction_output(gpio, 1);
  63 + udelay(1);
  64 + gpio_set_value(gpio, 0);
  65 + mdelay(40);
  66 + gpio_set_value(gpio, 1);
  67 + mdelay(1);
  68 +
  69 + return 0;
  70 +}
  71 +#else /* !CONFIG_OMAP_GPIO */
  72 +static inline int cl_omap3_smc911x_reset_net_chip(int gpio) { return 0; }
  73 +#endif /* CONFIG_OMAP_GPIO */
  74 +
  75 +int cl_omap3_smc911x_init(int id, int cs, u32 base_addr,
  76 + int (*reset)(int), int rst_gpio)
  77 +{
  78 + int ret;
  79 +
  80 + cl_omap3_smc911x_setup_net_chip_gmpc(cs, base_addr);
  81 +
  82 + if (reset)
  83 + reset(rst_gpio);
  84 + else
  85 + cl_omap3_smc911x_reset_net_chip(rst_gpio);
  86 +
  87 + ret = smc911x_initialize(id, base_addr);
  88 + if (ret > 0)
  89 + return ret;
  90 +
  91 + printf("Failed initializing SMC911x! ");
  92 + return 0;
  93 +}
board/compulab/common/splash.c
Diff comments   View file @ cfa1bd0
  1 +/*
  2 + * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
  3 + *
  4 + * Authors: Igor Grinberg <grinberg@compulab.co.il>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <nand.h>
  11 +#include <bmp_layout.h>
  12 +
  13 +DECLARE_GLOBAL_DATA_PTR;
  14 +
  15 +#ifdef CONFIG_CMD_NAND
  16 +static int splash_load_from_nand(u32 bmp_load_addr, int nand_offset)
  17 +{
  18 + struct bmp_header *bmp_hdr;
  19 + int res;
  20 + size_t bmp_size, bmp_header_size = sizeof(struct bmp_header);
  21 +
  22 + if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp)
  23 + goto splash_address_too_high;
  24 +
  25 + res = nand_read_skip_bad(&nand_info[nand_curr_device],
  26 + nand_offset, &bmp_header_size,
  27 + NULL, nand_info[nand_curr_device].size,
  28 + (u_char *)bmp_load_addr);
  29 + if (res < 0)
  30 + return res;
  31 +
  32 + bmp_hdr = (struct bmp_header *)bmp_load_addr;
  33 + bmp_size = le32_to_cpu(bmp_hdr->file_size);
  34 +
  35 + if (bmp_load_addr + bmp_size >= gd->start_addr_sp)
  36 + goto splash_address_too_high;
  37 +
  38 + return nand_read_skip_bad(&nand_info[nand_curr_device],
  39 + nand_offset, &bmp_size,
  40 + NULL, nand_info[nand_curr_device].size,
  41 + (u_char *)bmp_load_addr);
  42 +
  43 +splash_address_too_high:
  44 + printf("Error: splashimage address too high. Data overwrites U-Boot "
  45 + "and/or placed beyond DRAM boundaries.\n");
  46 +
  47 + return -1;
  48 +}
  49 +#else
  50 +static inline int splash_load_from_nand(u32 bmp_load_addr, int nand_offset)
  51 +{
  52 + return -1;
  53 +}
  54 +#endif /* CONFIG_CMD_NAND */
  55 +
  56 +int cl_splash_screen_prepare(int nand_offset)
  57 +{
  58 + char *env_splashimage_value;
  59 + u32 bmp_load_addr;
  60 +
  61 + env_splashimage_value = getenv("splashimage");
  62 + if (env_splashimage_value == NULL)
  63 + return -1;
  64 +
  65 + bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16);
  66 + if (bmp_load_addr == 0) {
  67 + printf("Error: bad splashimage address specified\n");
  68 + return -1;
  69 + }
  70 +
  71 + return splash_load_from_nand(bmp_load_addr, nand_offset);
  72 +}
board/siemens/pxm2/board.c
Diff comments   View file @ cfa1bd0
... ... @@ -229,7 +229,7 @@
229 229 #endif /* #ifdef CONFIG_FACTORYSET */
230 230  
231 231 /* Set rgmii mode and enable rmii clock to be sourced from chip */
232   - writel(RGMII_MODE_ENABLE , &cdev->miisel);
  232 + writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
233 233  
234 234 rv = cpsw_register(&cpsw_data);
235 235 if (rv < 0)
board/ti/am335x/Kconfig
Diff comments   View file @ cfa1bd0
... ... @@ -22,5 +22,20 @@
22 22 board you may want something other than UART0 as for example the IDK
23 23 uses UART3 so enter 4 here.
24 24  
  25 +config NOR
  26 + bool "Support for NOR flash"
  27 + help
  28 + The AM335x SoC supports having a NOR flash connected to the GPMC.
  29 + In practice this is seen as a NOR flash module connected to the
  30 + "memory cape" for the BeagleBone family.
  31 +
  32 +config NOR_BOOT
  33 + bool "Support for booting from NOR flash"
  34 + depends on NOR
  35 + help
  36 + Enabling this will make a U-Boot binary that is capable of being
  37 + booted via NOR. In this case we will enable certain pinmux early
  38 + as the ROM only partially sets up pinmux. We also default to using
  39 + NOR for environment.
25 40 endif
board/ti/ks2_evm/README
Diff comments   View file @ cfa1bd0
... ... @@ -3,10 +3,11 @@
3 3  
4 4 Author: Murali Karicheri <m-karicheri2@ti.com>
5 5  
6   -This README has information on the u-boot port for K2HK, K2E boards.
  6 +This README has information on the u-boot port for K2HK, K2E, and K2L EVM boards.
7 7 Documentation for this board can be found at
8 8 http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx
9 9 https://www.einfochips.com/index.php/partnerships/texas-instruments/k2e-evm.html
  10 +https://www.einfochips.com/index.php/partnerships/texas-instruments/k2l-evm.html
10 11  
11 12 The K2HK board is based on Texas Instruments Keystone2 family of SoCs: K2H, K2K.
12 13 More details on these SoCs are available at company websites
13 14  
... ... @@ -14,8 +15,11 @@
14 15 K2H: http://www.ti.com/product/tci6638k2h
15 16  
16 17 The K2E SoC details are available at
17   - K2E http://www.ti.com/lit/ds/symlink/66ak2e05.pdf
  18 + http://www.ti.com/lit/ds/symlink/66ak2e05.pdf
18 19  
  20 +The K2L SoC details are available at
  21 + http://www.ti.com/lit/ds/symlink/tci6630k2l.pdf
  22 +
19 23 Board configuration:
20 24 ====================
21 25  
... ... @@ -25,6 +29,7 @@
25 29 +------+-------+-------+-----------+-----------+-------+-------+----+
26 30 |K2HK |2 |512MB |6MB |4(2) |2 |3 |3 |
27 31 |K2E |4 |512MB |2MB |8(2) |2 |3 |3 |
  32 +|K2L |2 |512MB |2MB |4(2) |4 |3 |3 |
28 33 +------+-------+-------+-----------+-----------+-------+-------+----+
29 34  
30 35 There are only 2 eth port installed on the boards.
31 36  
... ... @@ -41,10 +46,13 @@
41 46 Board configuration files:
42 47 include/configs/k2hk_evm.h
43 48 include/configs/k2e_evm.h
  49 +include/configs/k2l_evm.h
  50 +include/configs/k2l_evm.h
44 51  
45 52 As u-boot is migrating to Kconfig there is also board defconfig files
46 53 configs/k2e_evm_defconfig
47 54 configs/k2hk_evm_defconfig
  55 +configs/k2l_evm_defconfig
48 56  
49 57 Supported boot modes:
50 58 - SPI NOR boot
... ... @@ -58,7 +66,7 @@
58 66  
59 67 Build instructions:
60 68 ===================
61   -Examples for k2hk, for k2e just replace k2hk prefix accordingly.
  69 +Examples for k2hk, for k2e and k2l just replace k2hk prefix accordingly.
62 70 Don't forget to add ARCH=arm and CROSS_COMPILE.
63 71  
64 72 To build u-boot.bin
... ... @@ -84,6 +92,8 @@
84 92 on EVM. Follow instructions at
85 93 K2HK http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup
86 94 K2E http://processors.wiki.ti.com/index.php/EVMK2E_Hardware_Setup
  95 +K2L http://processors.wiki.ti.com/index.php/TCIEVMK2L_Hardware_Setup
  96 +
87 97 to configure SW1 dip switch to use "No Boot/JTAG DSP Little Endian Boot Mode"
88 98 and Power ON the EVM. Follow instructions to connect serial port of EVM to
89 99 PC and start TeraTerm or Hyper Terminal.
... ... @@ -128,8 +138,8 @@
128 138 2. Suspend Target. Select Run -> Suspend from top level menu
129 139 CortexA15_1 (Free Running)"
130 140 3. Load u-boot-spi.gph binary from build folder on to DDR address 0x87000000
131   - through CCS as described in step 2 of "Load and Run U-Boot on K2HK/K2E EVM
132   - using CCS", but using address 0x87000000.
  141 + through CCS as described in step 2 of "Load and Run U-Boot on K2HK/K2E/K2L
  142 + EVM using CCS", but using address 0x87000000.
133 143 4. Free Run the target as described earlier (step 4) to get u-boot prompt
134 144 5. At the U-Boot console type following to setup u-boot environment variables.
135 145 setenv addr_uboot 0x87000000
board/ti/ks2_evm/board.c
Diff comments   View file @ cfa1bd0
... ... @@ -122,7 +122,6 @@
122 122 int nbanks;
123 123 u64 size[2];
124 124 u64 start[2];
125   - char name[32];
126 125 int nodeoffset;
127 126 u32 ddr3a_size;
128 127 int unitrd_fixup = 0;
129 128  
... ... @@ -158,15 +157,13 @@
158 157 }
159 158  
160 159 /* reserve memory at start of bank */
161   - sprintf(name, "mem_reserve_head");
162   - env = getenv(name);
  160 + env = getenv("mem_reserve_head");
163 161 if (env) {
164 162 start[0] += ustrtoul(env, &endp, 0);
165 163 size[0] -= ustrtoul(env, &endp, 0);
166 164 }
167 165  
168   - sprintf(name, "mem_reserve");
169   - env = getenv(name);
  166 + env = getenv("mem_reserve");
170 167 if (env)
171 168 size[0] -= ustrtoul(env, &endp, 0);
172 169  
board/ti/ks2_evm/board_k2l.c
Diff comments   View file @ cfa1bd0
... ... @@ -10,7 +10,7 @@
10 10 #include <common.h>
11 11 #include <asm/arch/ddr3.h>
12 12 #include <asm/arch/hardware.h>
13   -#include <asm/ti-common/ti-aemif.h>
  13 +#include <asm/ti-common/keystone_net.h>
14 14  
15 15 DECLARE_GLOBAL_DATA_PTR;
16 16  
... ... @@ -41,6 +41,44 @@
41 41  
42 42 static struct pll_init_data pa_pll_config =
43 43 PASS_PLL_983;
  44 +
  45 +#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
  46 +struct eth_priv_t eth_priv_cfg[] = {
  47 + {
  48 + .int_name = "K2L_EMAC",
  49 + .rx_flow = 0,
  50 + .phy_addr = 0,
  51 + .slave_port = 1,
  52 + .sgmii_link_type = SGMII_LINK_MAC_PHY,
  53 + },
  54 + {
  55 + .int_name = "K2L_EMAC1",
  56 + .rx_flow = 8,
  57 + .phy_addr = 1,
  58 + .slave_port = 2,
  59 + .sgmii_link_type = SGMII_LINK_MAC_PHY,
  60 + },
  61 + {
  62 + .int_name = "K2L_EMAC2",
  63 + .rx_flow = 16,
  64 + .phy_addr = 2,
  65 + .slave_port = 3,
  66 + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
  67 + },
  68 + {
  69 + .int_name = "K2L_EMAC3",
  70 + .rx_flow = 32,
  71 + .phy_addr = 3,
  72 + .slave_port = 4,
  73 + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
  74 + },
  75 +};
  76 +
  77 +int get_num_eth_ports(void)
  78 +{
  79 + return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
  80 +}
  81 +#endif
44 82  
45 83 #ifdef CONFIG_BOARD_EARLY_INIT_F
46 84 int board_early_init_f(void)
configs/am335x_evm_nor_defconfig
Diff comments   View file @ cfa1bd0
1 1 CONFIG_SPL=y
2   -CONFIG_SYS_EXTRA_OPTIONS="NAND,NOR"
  2 +CONFIG_SYS_EXTRA_OPTIONS="NAND"
3 3 CONFIG_CONS_INDEX=1
4 4 +S:CONFIG_ARM=y
5 5 +S:CONFIG_TARGET_AM335X_EVM=y
  6 +CONFIG_NOR=y
configs/am335x_evm_norboot_defconfig
Diff comments   View file @ cfa1bd0
1   -CONFIG_SYS_EXTRA_OPTIONS="NOR,NOR_BOOT"
2 1 CONFIG_CONS_INDEX=1
3 2 CONFIG_ARM=y
4 3 CONFIG_TARGET_AM335X_EVM=y
  4 +CONFIG_NOR=y
  5 +CONFIG_NOR_BOOT=y
configs/cm_t3517_defconfig
Diff comments   View file @ cfa1bd0
  1 +CONFIG_SPL=n
  2 ++S:CONFIG_ARM=y
  3 ++S:CONFIG_OMAP34XX=y
  4 ++S:CONFIG_TARGET_CM_T3517=y
drivers/dma/keystone_nav.c
Diff comments   View file @ cfa1bd0
... ... @@ -81,9 +81,6 @@
81 81 {
82 82 u32 j;
83 83  
84   - if (qm_cfg == NULL)
85   - return;
86   -
87 84 queue_close(qm_cfg->qpool_num);
88 85  
89 86 qm_cfg->mngr_cfg->link_ram_base0 = 0;
... ... @@ -105,9 +102,6 @@
105 102 {
106 103 u32 regd;
107 104  
108   - if (!qm_cfg)
109   - return;
110   -
111 105 cpu_to_bus((u32 *)hd, sizeof(struct qm_host_desc)/4);
112 106 regd = (u32)hd | ((sizeof(struct qm_host_desc) >> 4) - 1);
113 107 writel(regd, &qm_cfg->queue[qnum].ptr_size_thresh);
... ... @@ -127,9 +121,6 @@
127 121 {
128 122 u32 uhd;
129 123  
130   - if (!qm_cfg)
131   - return NULL;
132   -
133 124 uhd = readl(&qm_cfg->queue[qnum].ptr_size_thresh) & ~0xf;
134 125 if (uhd)
135 126 cpu_to_bus((u32 *)uhd, sizeof(struct qm_host_desc)/4);
... ... @@ -139,9 +130,6 @@
139 130  
140 131 struct qm_host_desc *qm_pop_from_free_pool(void)
141 132 {
142   - if (!qm_cfg)
143   - return NULL;
144   -
145 133 return qm_pop(qm_cfg->qpool_num);
146 134 }
147 135  
drivers/mmc/omap_hsmmc.c
Diff comments   View file @ cfa1bd0
... ... @@ -611,7 +611,8 @@
611 611 if (cd_gpio < 0)
612 612 return 1;
613 613  
614   - return gpio_get_value(cd_gpio);
  614 + /* NOTE: assumes card detect signal is active-low */
  615 + return !gpio_get_value(cd_gpio);
615 616 }
616 617  
617 618 static int omap_hsmmc_getwp(struct mmc *mmc)
... ... @@ -624,6 +625,7 @@
624 625 if (wp_gpio < 0)
625 626 return 0;
626 627  
  628 + /* NOTE: assumes write protect signal is active-high */
627 629 return gpio_get_value(wp_gpio);
628 630 }
629 631 #endif
drivers/net/keystone_net.c
Diff comments   View file @ cfa1bd0
... ... @@ -315,7 +315,7 @@
315 315 writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
316 316 writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
317 317  
318   -#ifdef CONFIG_K2E_EVM
  318 +#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
319 319 /* Map RX packet flow priority to 0 */
320 320 writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP);
321 321 #endif
... ... @@ -400,6 +400,9 @@
400 400  
401 401 keystone2_net_serdes_setup();
402 402  
  403 + if (sys_has_mdio)
  404 + keystone2_mdio_reset(mdio_bus);
  405 +
403 406 keystone_sgmii_config(phy_dev, eth_priv->slave_port - 1,
404 407 eth_priv->sgmii_link_type);
405 408  
... ... @@ -582,7 +585,7 @@
582 585 &ks2_serdes_sgmii_156p25mhz,
583 586 CONFIG_KSNET_SERDES_LANES_PER_SGMII);
584 587  
585   -#ifdef CONFIG_SOC_K2E
  588 +#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
586 589 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE,
587 590 &ks2_serdes_sgmii_156p25mhz,
588 591 CONFIG_KSNET_SERDES_LANES_PER_SGMII);
drivers/net/phy/marvell.c
Diff comments   View file @ cfa1bd0
... ... @@ -276,6 +276,57 @@
276 276 return 0;
277 277 }
278 278  
  279 +/**
  280 + * m88e1518_phy_writebits - write bits to a register
  281 + */
  282 +void m88e1518_phy_writebits(struct phy_device *phydev,
  283 + u8 reg_num, u16 offset, u16 len, u16 data)
  284 +{
  285 + u16 reg, mask;
  286 +
  287 + if ((len + offset) >= 16)
  288 + mask = 0 - (1 << offset);
  289 + else
  290 + mask = (1 << (len + offset)) - (1 << offset);
  291 +
  292 + reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num);
  293 +
  294 + reg &= ~mask;
  295 + reg |= data << offset;
  296 +
  297 + phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg);
  298 +}
  299 +
  300 +static int m88e1518_config(struct phy_device *phydev)
  301 +{
  302 + /*
  303 + * As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512
  304 + * /88E1514 Rev A0, Errata Section 3.1
  305 + */
  306 + if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
  307 + phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00ff); /* page 0xff */
  308 + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B);
  309 + phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144);
  310 + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28);
  311 + phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146);
  312 + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233);
  313 + phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D);
  314 + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C);
  315 + phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159);
  316 + phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000); /* reg page 0 */
  317 + phy_write(phydev, MDIO_DEVAD_NONE, 22, 18); /* reg page 18 */
  318 + /* Write HWCFG_MODE = SGMII to Copper */
  319 + m88e1518_phy_writebits(phydev, 20, 0, 3, 1);
  320 +
  321 + /* Phy reset */
  322 + m88e1518_phy_writebits(phydev, 20, 15, 1, 1);
  323 + phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); /* reg page 18 */
  324 + udelay(100);
  325 + }
  326 +
  327 + return m88e1111s_config(phydev);
  328 +}
  329 +
279 330 /* Marvell 88E1118 */
280 331 static int m88e1118_config(struct phy_device *phydev)
281 332 {
... ... @@ -493,7 +544,7 @@
493 544 .uid = 0x1410dd1,
494 545 .mask = 0xffffff0,
495 546 .features = PHY_GBIT_FEATURES,
496   - .config = &m88e1111s_config,
  547 + .config = &m88e1518_config,
497 548 .startup = &m88e1011s_startup,
498 549 .shutdown = &genphy_shutdown,
499 550 };
include/configs/am335x_evm.h
Diff comments   View file @ cfa1bd0
... ... @@ -314,6 +314,18 @@
314 314 #define CONFIG_AM335X_USB1
315 315 #define CONFIG_AM335X_USB1_MODE MUSB_HOST
316 316  
  317 +#ifndef CONFIG_SPL_USBETH_SUPPORT
  318 +/* Fastboot */
  319 +#define CONFIG_CMD_FASTBOOT
  320 +#define CONFIG_ANDROID_BOOT_IMAGE
  321 +#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
  322 +#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000
  323 +
  324 +/* To support eMMC booting */
  325 +#define CONFIG_STORAGE_EMMC
  326 +#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
  327 +#endif
  328 +
317 329 #ifdef CONFIG_MUSB_HOST
318 330 #define CONFIG_CMD_USB
319 331 #define CONFIG_USB_STORAGE
... ... @@ -325,8 +337,8 @@
325 337 #define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00"
326 338  
327 339 /* USB TI's IDs */
328   -#define CONFIG_G_DNL_VENDOR_NUM 0x0403
329   -#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00
  340 +#define CONFIG_G_DNL_VENDOR_NUM 0x0451
  341 +#define CONFIG_G_DNL_PRODUCT_NUM 0xD022
330 342 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
331 343 #endif /* CONFIG_MUSB_GADGET */
332 344  
include/configs/cm_t3517.h
Diff comments   View file @ cfa1bd0
  1 +/*
  2 + * (C) Copyright 2013 CompuLab, Ltd.
  3 + * Author: Igor Grinberg <grinberg@compulab.co.il>
  4 + *
  5 + * Configuration settings for the CompuLab CM-T3517 board
  6 + *
  7 + * SPDX-License-Identifier: GPL-2.0+
  8 + */
  9 +
  10 +#ifndef __CONFIG_H
  11 +#define __CONFIG_H
  12 +
  13 +/*
  14 + * High Level Configuration Options
  15 + */
  16 +#define CONFIG_OMAP /* in a TI OMAP core */
  17 +#define CONFIG_CM_T3517 /* working with CM-T3517 */
  18 +#define CONFIG_OMAP_COMMON
  19 +#define CONFIG_SYS_GENERIC_BOARD
  20 +
  21 +#define CONFIG_SYS_TEXT_BASE 0x80008000
  22 +
  23 +/*
  24 + * This is needed for the DMA stuff.
  25 + * Although the default iss 64, we still define it
  26 + * to be on the safe side once the default is changed.
  27 + */
  28 +#define CONFIG_SYS_CACHELINE_SIZE 64
  29 +
  30 +#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
  31 +
  32 +#include <asm/arch/cpu.h> /* get chip and board defs */
  33 +#include <asm/arch/omap3.h>
  34 +
  35 +/*
  36 + * Display CPU and Board information
  37 + */
  38 +#define CONFIG_DISPLAY_CPUINFO
  39 +#define CONFIG_DISPLAY_BOARDINFO
  40 +
  41 +/* Clock Defines */
  42 +#define V_OSCK 26000000 /* Clock output from T2 */
  43 +#define V_SCLK (V_OSCK >> 1)
  44 +
  45 +#define CONFIG_MISC_INIT_R
  46 +
  47 +#define CONFIG_OF_LIBFDT
  48 +/*
  49 + * The early kernel mapping on ARM currently only maps from the base of DRAM
  50 + * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000.
  51 + * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
  52 + * so that leaves DRAM base to DRAM base + 0x4000 available.
  53 + */
  54 +#define CONFIG_SYS_BOOTMAPSZ 0x4000
  55 +
  56 +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
  57 +#define CONFIG_SETUP_MEMORY_TAGS
  58 +#define CONFIG_INITRD_TAG
  59 +#define CONFIG_REVISION_TAG
  60 +#define CONFIG_SERIAL_TAG
  61 +
  62 +/*
  63 + * Size of malloc() pool
  64 + */
  65 +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
  66 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
  67 +
  68 +/*
  69 + * Hardware drivers
  70 + */
  71 +
  72 +/*
  73 + * NS16550 Configuration
  74 + */
  75 +#define CONFIG_SYS_NS16550
  76 +#define CONFIG_SYS_NS16550_SERIAL
  77 +#define CONFIG_SYS_NS16550_REG_SIZE (-4)
  78 +#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
  79 +
  80 +/*
  81 + * select serial console configuration
  82 + */
  83 +#define CONFIG_CONS_INDEX 3
  84 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
  85 +#define CONFIG_SERIAL3 3 /* UART3 */
  86 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV
  87 +
  88 +/* allow to overwrite serial and ethaddr */
  89 +#define CONFIG_ENV_OVERWRITE
  90 +#define CONFIG_BAUDRATE 115200
  91 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
  92 + 115200}
  93 +
  94 +#define CONFIG_OMAP_GPIO
  95 +
  96 +#define CONFIG_GENERIC_MMC
  97 +#define CONFIG_MMC
  98 +#define CONFIG_OMAP_HSMMC
  99 +#define CONFIG_DOS_PARTITION
  100 +
  101 +/* USB */
  102 +#define CONFIG_USB_MUSB_AM35X
  103 +
  104 +#ifndef CONFIG_USB_MUSB_AM35X
  105 +#define CONFIG_USB_OMAP3
  106 +#define CONFIG_USB_EHCI
  107 +#define CONFIG_USB_EHCI_OMAP
  108 +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146
  109 +#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147
  110 +#else /* !CONFIG_USB_MUSB_AM35X */
  111 +#define CONFIG_MUSB_HOST
  112 +#define CONFIG_MUSB_PIO_ONLY
  113 +#endif /* CONFIG_USB_MUSB_AM35X */
  114 +
  115 +#define CONFIG_USB_STORAGE
  116 +#define CONFIG_CMD_USB
  117 +
  118 +/* commands to include */
  119 +#include <config_cmd_default.h>
  120 +
  121 +#define CONFIG_CMD_CACHE
  122 +#define CONFIG_CMD_EXT2 /* EXT2 Support */
  123 +#define CONFIG_CMD_FAT /* FAT support */
  124 +#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
  125 +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
  126 +#define CONFIG_MTD_PARTITIONS
  127 +#define MTDIDS_DEFAULT "nand0=nand"
  128 +#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
  129 + "1920k(u-boot),256k(u-boot-env),"\
  130 + "4m(kernel),-(fs)"
  131 +
  132 +#define CONFIG_CMD_I2C /* I2C serial bus support */
  133 +#define CONFIG_CMD_MMC /* MMC support */
  134 +#define CONFIG_CMD_NAND /* NAND support */
  135 +#define CONFIG_CMD_DHCP
  136 +#define CONFIG_CMD_PING
  137 +#define CONFIG_CMD_GPIO
  138 +
  139 +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
  140 +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
  141 +#undef CONFIG_CMD_IMLS /* List all found images */
  142 +
  143 +#define CONFIG_SYS_NO_FLASH
  144 +#define CONFIG_SYS_I2C
  145 +#define CONFIG_SYS_OMAP24_I2C_SPEED 400000
  146 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
  147 +#define CONFIG_SYS_I2C_OMAP34XX
  148 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  149 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  150 +#define CONFIG_SYS_I2C_EEPROM_BUS 0
  151 +#define CONFIG_I2C_MULTI_BUS
  152 +
  153 +/*
  154 + * Board NAND Info.
  155 + */
  156 +#define CONFIG_SYS_NAND_QUIET_TEST
  157 +#define CONFIG_NAND_OMAP_GPMC
  158 +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
  159 + /* to access nand */
  160 +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
  161 + /* to access nand at */
  162 + /* CS0 */
  163 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
  164 + /* devices */
  165 +
  166 +/* Environment information */
  167 +#define CONFIG_BOOTDELAY 3
  168 +#define CONFIG_ZERO_BOOTDELAY_CHECK
  169 +
  170 +#define CONFIG_EXTRA_ENV_SETTINGS \
  171 + "loadaddr=0x82000000\0" \
  172 + "baudrate=115200\0" \
  173 + "console=ttyO2,115200n8\0" \
  174 + "mpurate=auto\0" \
  175 + "vram=12M\0" \
  176 + "dvimode=1024x768MR-16@60\0" \
  177 + "defaultdisplay=dvi\0" \
  178 + "mmcdev=0\0" \
  179 + "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
  180 + "mmcrootfstype=ext4\0" \
  181 + "nandroot=/dev/mtdblock4 rw\0" \
  182 + "nandrootfstype=ubifs\0" \
  183 + "mmcargs=setenv bootargs console=${console} " \
  184 + "mpurate=${mpurate} " \
  185 + "vram=${vram} " \
  186 + "omapfb.mode=dvi:${dvimode} " \
  187 + "omapdss.def_disp=${defaultdisplay} " \
  188 + "root=${mmcroot} " \
  189 + "rootfstype=${mmcrootfstype}\0" \
  190 + "nandargs=setenv bootargs console=${console} " \
  191 + "mpurate=${mpurate} " \
  192 + "vram=${vram} " \
  193 + "omapfb.mode=dvi:${dvimode} " \
  194 + "omapdss.def_disp=${defaultdisplay} " \
  195 + "root=${nandroot} " \
  196 + "rootfstype=${nandrootfstype}\0" \
  197 + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
  198 + "bootscript=echo Running bootscript from mmc ...; " \
  199 + "source ${loadaddr}\0" \
  200 + "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
  201 + "mmcboot=echo Booting from mmc ...; " \
  202 + "run mmcargs; " \
  203 + "bootm ${loadaddr}\0" \
  204 + "nandboot=echo Booting from nand ...; " \
  205 + "run nandargs; " \
  206 + "nand read ${loadaddr} 2a0000 400000; " \
  207 + "bootm ${loadaddr}\0" \
  208 +
  209 +#define CONFIG_CMD_BOOTZ
  210 +#define CONFIG_BOOTCOMMAND \
  211 + "mmc dev ${mmcdev}; if mmc rescan; then " \
  212 + "if run loadbootscript; then " \
  213 + "run bootscript; " \
  214 + "else " \
  215 + "if run loaduimage; then " \
  216 + "run mmcboot; " \
  217 + "else run nandboot; " \
  218 + "fi; " \
  219 + "fi; " \
  220 + "else run nandboot; fi"
  221 +
  222 +/*
  223 + * Miscellaneous configurable options
  224 + */
  225 +#define CONFIG_AUTO_COMPLETE
  226 +#define CONFIG_CMDLINE_EDITING
  227 +#define CONFIG_TIMESTAMP
  228 +#define CONFIG_SYS_AUTOLOAD "no"
  229 +#define CONFIG_SYS_LONGHELP /* undef to save memory */
  230 +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
  231 +#define CONFIG_SYS_PROMPT "CM-T3517 # "
  232 +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  233 +/* Print Buffer Size */
  234 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  235 + sizeof(CONFIG_SYS_PROMPT) + 16)
  236 +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
  237 +/* Boot Argument Buffer Size */
  238 +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
  239 +
  240 +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
  241 +
  242 +/*
  243 + * AM3517 has 12 GP timers, they can be driven by the system clock
  244 + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
  245 + * This rate is divided by a local divisor.
  246 + */
  247 +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
  248 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
  249 +#define CONFIG_SYS_HZ 1000
  250 +
  251 +/*-----------------------------------------------------------------------
  252 + * Physical Memory Map
  253 + */
  254 +#define CONFIG_NR_DRAM_BANKS 1 /* CM-T3517 DRAM is only on CS0 */
  255 +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
  256 +#define CONFIG_SYS_CS0_SIZE (256 << 20)
  257 +
  258 +/*-----------------------------------------------------------------------
  259 + * FLASH and environment organization
  260 + */
  261 +
  262 +/* **** PISMO SUPPORT *** */
  263 +/* Monitor at start of flash */
  264 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  265 +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
  266 +
  267 +#define CONFIG_ENV_IS_IN_NAND
  268 +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
  269 +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
  270 +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
  271 +
  272 +#if defined(CONFIG_CMD_NET)
  273 +#define CONFIG_DRIVER_TI_EMAC
  274 +#define CONFIG_DRIVER_TI_EMAC_USE_RMII
  275 +#define CONFIG_MII
  276 +#define CONFIG_SMC911X
  277 +#define CONFIG_SMC911X_32_BIT
  278 +#define CONFIG_SMC911X_BASE (0x2C000000 + (16 << 20))
  279 +#endif /* CONFIG_CMD_NET */
  280 +
  281 +/* additions for new relocation code, must be added to all boards */
  282 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  283 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
  284 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800
  285 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
  286 + CONFIG_SYS_INIT_RAM_SIZE - \
  287 + GENERATED_GBL_DATA_SIZE)
  288 +
  289 +/* Status LED */
  290 +#define CONFIG_STATUS_LED /* Status LED enabled */
  291 +#define CONFIG_BOARD_SPECIFIC_LED
  292 +#define CONFIG_GPIO_LED
  293 +#define GREEN_LED_GPIO 186 /* CM-T3517 Green LED is GPIO186 */
  294 +#define GREEN_LED_DEV 0
  295 +#define STATUS_LED_BIT GREEN_LED_GPIO
  296 +#define STATUS_LED_STATE STATUS_LED_ON
  297 +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
  298 +#define STATUS_LED_BOOT GREEN_LED_DEV
  299 +
  300 +/* GPIO banks */
  301 +#ifdef CONFIG_STATUS_LED
  302 +#define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */
  303 +#endif
  304 +
  305 +/* Display Configuration */
  306 +#define CONFIG_OMAP3_GPIO_2
  307 +#define CONFIG_OMAP3_GPIO_5
  308 +#define CONFIG_VIDEO_OMAP3
  309 +#define LCD_BPP LCD_COLOR16
  310 +
  311 +#define CONFIG_LCD
  312 +#define CONFIG_SPLASH_SCREEN
  313 +#define CONFIG_SPLASHIMAGE_GUARD
  314 +#define CONFIG_CMD_BMP
  315 +#define CONFIG_BMP_16BPP
  316 +#define CONFIG_SCF0403_LCD
  317 +
  318 +#define CONFIG_OMAP3_SPI
  319 +
  320 +#endif /* __CONFIG_H */
include/configs/k2e_evm.h
Diff comments   View file @ cfa1bd0
... ... @@ -17,15 +17,16 @@
17 17 /* U-Boot general configuration */
18 18 #define CONFIG_SYS_PROMPT "K2E EVM # "
19 19  
20   -#define KS2_ARGS_UBI "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\
21   - "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0"
  20 +#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
  21 + "addr_mon=0x0c140000\0" \
  22 + "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \
  23 + "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0" \
  24 + "name_fdt=uImage-k2e-evm.dtb\0" \
  25 + "name_mon=skern-k2e-evm.bin\0" \
  26 + "name_ubi=k2e-evm-ubifs.ubi\0" \
  27 + "name_uboot=u-boot-spi-k2e-evm.gph\0" \
  28 + "name_fs=arago-console-image-k2e-evm.cpio.gz\0"
22 29  
23   -#define KS2_FDT_NAME "name_fdt=k2e-evm.dtb\0"
24   -#define KS2_ADDR_MON "addr_mon=0x0c140000\0"
25   -#define KS2_NAME_MON "name_mon=skern-k2e-evm.bin\0"
26   -#define NAME_UBOOT "name_uboot=u-boot-spi-k2e-evm.gph\0"
27   -#define NAME_UBI "name_ubi=k2e-evm-ubifs.ubi\0"
28   -
29 30 #include <configs/ks2_evm.h>
30 31  
31 32 /* SPL SPI Loader Configuration */
32 33  
... ... @@ -35,15 +36,9 @@
35 36 #define CONFIG_SYS_NAND_PAGE_2K
36 37  
37 38 /* Network */
38   -#define CONFIG_DRIVER_TI_KEYSTONE_NET
39   -#define CONFIG_TI_KSNAV
40   -#define CONFIG_KSNAV_PKTDMA_NETCP
41 39 #define CONFIG_KSNET_NETCP_V1_5
42 40 #define CONFIG_KSNET_CPSW_NUM_PORTS 9
43 41 #define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
44   -
45   -/* SerDes */
46   -#define CONFIG_TI_KEYSTONE_SERDES
47 42  
48 43 #endif /* __CONFIG_K2E_EVM_H */
include/configs/k2hk_evm.h
Diff comments   View file @ cfa1bd0
... ... @@ -17,15 +17,16 @@
17 17 /* U-Boot general configuration */
18 18 #define CONFIG_SYS_PROMPT "K2HK EVM # "
19 19  
20   -#define KS2_ARGS_UBI "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\
21   - "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0"
  20 +#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
  21 + "addr_mon=0x0c5f0000\0" \
  22 + "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \
  23 + "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0" \
  24 + "name_fdt=uImage-k2hk-evm.dtb\0" \
  25 + "name_mon=skern-k2hk-evm.bin\0" \
  26 + "name_ubi=k2hk-evm-ubifs.ubi\0" \
  27 + "name_uboot=u-boot-spi-k2hk-evm.gph\0" \
  28 + "name_fs=arago-console-image-k2hk-evm.cpio.gz\0"
22 29  
23   -#define KS2_FDT_NAME "name_fdt=k2hk-evm.dtb\0"
24   -#define KS2_ADDR_MON "addr_mon=0x0c5f0000\0"
25   -#define KS2_NAME_MON "name_mon=skern-k2hk-evm.bin\0"
26   -#define NAME_UBOOT "name_uboot=u-boot-spi-k2hk-evm.gph\0"
27   -#define NAME_UBI "name_ubi=k2hk-evm-ubifs.ubi\0"
28   -
29 30 #include <configs/ks2_evm.h>
30 31  
31 32 /* SPL SPI Loader Configuration */
32 33  
... ... @@ -35,14 +36,8 @@
35 36 #define CONFIG_SYS_NAND_PAGE_2K
36 37  
37 38 /* Network */
38   -#define CONFIG_DRIVER_TI_KEYSTONE_NET
39   -#define CONFIG_TI_KSNAV
40   -#define CONFIG_KSNAV_PKTDMA_NETCP
41 39 #define CONFIG_KSNET_NETCP_V1_0
42 40 #define CONFIG_KSNET_CPSW_NUM_PORTS 5
43   -
44   -/* SerDes */
45   -#define CONFIG_TI_KEYSTONE_SERDES
46 41  
47 42 #endif /* __CONFIG_K2HK_EVM_H */
include/configs/k2l_evm.h
Diff comments   View file @ cfa1bd0
... ... @@ -17,15 +17,16 @@
17 17 /* U-Boot general configuration */
18 18 #define CONFIG_SYS_PROMPT "K2L EVM # "
19 19  
20   -#define KS2_ARGS_UBI "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\
21   - "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,4096\0"
  20 +#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
  21 + "addr_mon=0x0c140000\0" \
  22 + "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \
  23 + "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,4096\0" \
  24 + "name_fdt=uImage-k2l-evm.dtb\0" \
  25 + "name_mon=skern-k2l-evm.bin\0" \
  26 + "name_ubi=k2l-evm-ubifs.ubi\0" \
  27 + "name_uboot=u-boot-spi-k2l-evm.gph\0" \
  28 + "name_fs=arago-console-image-k2l-evm.cpio.gz\0"
22 29  
23   -#define KS2_FDT_NAME "name_fdt=k2l-evm.dtb\0"
24   -#define KS2_ADDR_MON "addr_mon=0x0c140000\0"
25   -#define KS2_NAME_MON "name_mon=skern-k2l-evm.bin\0"
26   -#define NAME_UBOOT "name_uboot=u-boot-spi-k2l-evm.gph\0"
27   -#define NAME_UBI "name_ubi=k2l-evm-ubifs.ubi\0"
28   -
29 30 #include <configs/ks2_evm.h>
30 31  
31 32 /* SPL SPI Loader Configuration */
... ... @@ -33,6 +34,11 @@
33 34  
34 35 /* NAND Configuration */
35 36 #define CONFIG_SYS_NAND_PAGE_4K
  37 +
  38 +/* Network */
  39 +#define CONFIG_KSNET_NETCP_V1_5
  40 +#define CONFIG_KSNET_CPSW_NUM_PORTS 5
  41 +#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
36 42  
37 43 #endif /* __CONFIG_K2L_EVM_H */
include/configs/ks2_evm.h
Diff comments   View file @ cfa1bd0
... ... @@ -105,6 +105,7 @@
105 105 #define CONFIG_SYS_SGMII_RATESCALE 2
106 106  
107 107 /* Keyston Navigator Configuration */
  108 +#define CONFIG_TI_KSNAV
108 109 #define CONFIG_KSNAV_QM_BASE_ADDRESS KS2_QM_BASE_ADDRESS
109 110 #define CONFIG_KSNAV_QM_CONF_BASE KS2_QM_CONF_BASE
110 111 #define CONFIG_KSNAV_QM_DESC_SETUP_BASE KS2_QM_DESC_SETUP_BASE
... ... @@ -121,6 +122,7 @@
121 122 #define CONFIG_KSNAV_QM_QPOOL_NUM KS2_QM_QPOOL_NUM
122 123  
123 124 /* NETCP pktdma */
  125 +#define CONFIG_KSNAV_PKTDMA_NETCP
124 126 #define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE KS2_NETCP_PDMA_CTRL_BASE
125 127 #define CONFIG_KSNAV_NETCP_PDMA_TX_BASE KS2_NETCP_PDMA_TX_BASE
126 128 #define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM KS2_NETCP_PDMA_TX_CH_NUM
127 129  
... ... @@ -134,12 +136,16 @@
134 136 #define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE KS2_NETCP_PDMA_TX_SND_QUEUE
135 137  
136 138 /* Keystone net */
  139 +#define CONFIG_DRIVER_TI_KEYSTONE_NET
137 140 #define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR
138 141 #define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE
139 142 #define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE
140 143 #define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE
141 144 #define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES
142 145  
  146 +/* SerDes */
  147 +#define CONFIG_TI_KEYSTONE_SERDES
  148 +
143 149 /* AEMIF */
144 150 #define CONFIG_TI_AEMIF
145 151 #define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
... ... @@ -218,6 +224,8 @@
218 224 #define CONFIG_CMD_SF
219 225 #define CONFIG_CMD_EEPROM
220 226 #define CONFIG_CMD_USB
  227 +#define CONFIG_CMD_FAT
  228 +#define CONFIG_CMD_FS_GENERIC
221 229  
222 230 /* U-Boot general configuration */
223 231 #define CONFIG_SYS_GENERIC_BOARD
224 232  
225 233  
226 234  
... ... @@ -239,30 +247,25 @@
239 247 #define CONFIG_BOOTDELAY 3
240 248 #define CONFIG_BOOTFILE "uImage"
241 249 #define CONFIG_EXTRA_ENV_SETTINGS \
242   - "boot=ramfs\0" \
  250 + CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
  251 + "boot=ubi\0" \
243 252 "tftp_root=/\0" \
244 253 "nfs_root=/export\0" \
245 254 "mem_lpae=1\0" \
246 255 "mem_reserve=512M\0" \
247 256 "addr_fdt=0x87000000\0" \
248 257 "addr_kern=0x88000000\0" \
249   - KS2_ADDR_MON \
250 258 "addr_uboot=0x87000000\0" \
251 259 "addr_fs=0x82000000\0" \
252 260 "addr_ubi=0x82000000\0" \
253 261 "addr_secdb_key=0xc000000\0" \
254 262 "fdt_high=0xffffffff\0" \
255   - KS2_FDT_NAME \
256   - "name_fs=arago-console-image.cpio.gz\0" \
257   - "name_kern=uImage\0" \
258   - KS2_NAME_MON \
259   - NAME_UBOOT \
260   - NAME_UBI \
  263 + "name_kern=uImage-keystone-evm.bin\0" \
261 264 "run_mon=mon_install ${addr_mon}\0" \
262 265 "run_kern=bootm ${addr_kern} - ${addr_fdt}\0" \
263 266 "init_net=run args_all args_net\0" \
264 267 "init_ubi=run args_all args_ubi; " \
265   - "ubi part ubifs; ubifsmount boot;" \
  268 + "ubi part ubifs; ubifsmount ubi:boot;" \
266 269 "ubifsload ${addr_secdb_key} securedb.key.bin;\0" \
267 270 "get_fdt_net=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \
268 271 "get_fdt_ubi=ubifsload ${addr_fdt} ${name_fdt}\0" \
... ... @@ -276,7 +279,6 @@
276 279 "burn_uboot_nand=nand erase 0 0x100000; " \
277 280 "nand write ${addr_uboot} 0 ${filesize}\0" \
278 281 "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0" \
279   - KS2_ARGS_UBI \
280 282 "args_net=setenv bootargs ${bootargs} rootfstype=nfs " \
281 283 "root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \
282 284 "${nfs_options} ip=dhcp\0" \
include/configs/omap3_igep00x0.h
Diff comments   View file @ cfa1bd0
... ... @@ -29,8 +29,6 @@
29 29  
30 30 #define CONFIG_REVISION_TAG 1
31 31  
32   -#define CONFIG_SUPPORT_RAW_INITRD
33   -
34 32 /* define to enable boot progress via leds */
35 33 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
36 34 (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
include/configs/ti_armv7_common.h
Diff comments   View file @ cfa1bd0
... ... @@ -174,6 +174,7 @@
174 174 #define CONFIG_CMD_ASKENV
175 175 #define CONFIG_CMD_ECHO
176 176 #define CONFIG_CMD_BOOTZ
  177 +#define CONFIG_SUPPORT_RAW_INITRD
177 178  
178 179 /*
179 180 * Common filesystems support. When we have removable storage we
... ... @@ -390,6 +390,8 @@
390 390  
391 391 /* Voltage Selection in PM Receiver Module */
392 392 #define TWL4030_PM_RECEIVER_VAUX2_VSEL_18 0x05
  393 +#define TWL4030_PM_RECEIVER_VAUX2_VSEL_28 0x09
  394 +#define TWL4030_PM_RECEIVER_VAUX3_VSEL_18 0x01
393 395 #define TWL4030_PM_RECEIVER_VAUX3_VSEL_28 0x03
394 396 #define TWL4030_PM_RECEIVER_VPLL2_VSEL_18 0x05
395 397 #define TWL4030_PM_RECEIVER_VDAC_VSEL_18 0x03