* Fix NSCU config; add ethernet wakeup code.

* Add link for preloader for Motorola Coldfire to RAEDME.m68k

* Fix NSCU config; add ethernet wakeup code.
* Add link for preloader for Motorola Coldfire to RAEDME.m68k
wdenk
1 parent 45eeb8983c
Showing 4 changed files with 40 additions and 42 deletions Side-by-side Diff
CHANGELOG
board/tqm8xx/tqm8xx.c
doc/README.m68k
include/configs/NSCU.h
@@ -5,6 +5,10 @@
 * Patch by Stefan Roese, 15 Jul 2004:
   cpu/ppc4xx/sdram.c rewritten now using get_ram_size()
  
+* Fix NSCU config; add ethernet wakeup code.
+
+* Add link for preloader for Motorola Coldfire to RAEDME.m68k
+
 * Patch by Michael Bendzick, 12 Jul 2004:
   fix output formatting in drivers/cfi_flash.c
  
@@ -445,12 +445,14 @@
  
 #endif /* CONFIG_PS2MULT */
  
-/* ------------------------------------------------------------------------- */
+/* ---------------------------------------------------------------------------- */
+/* HMI10 specific stuff								*/
+/* ---------------------------------------------------------------------------- */
 #ifdef CONFIG_HMI10
  
 int misc_init_r (void)
 {
-#ifdef CONFIG_IDE_LED
+# ifdef CONFIG_IDE_LED
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
  
 	/* Configure PA15 as output port */
  
@@ -458,11 +460,11 @@
 	immap->im_ioport.iop_paodr |= 0x0001;
 	immap->im_ioport.iop_papar &= ~0x0001;
 	immap->im_ioport.iop_padat &= ~0x0001;	/* turn it off */
-#endif
+# endif
 	return (0);
 }
  
-#ifdef CONFIG_IDE_LED
+# ifdef CONFIG_IDE_LED
 void ide_led (uchar led, uchar status)
 {
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
  
@@ -474,8 +476,27 @@
 		immap->im_ioport.iop_padat &= ~0x0001;
 	}
 }
-#endif
+# endif
+#endif	/* CONFIG_HMI10 */
  
-#endif /* CONFIG_HMI10 */
+/* ---------------------------------------------------------------------------- */
+/* NSCU specific stuff								*/
+/* ---------------------------------------------------------------------------- */
+#ifdef CONFIG_NSCU
+
+int misc_init_r (void)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+
+	/* wake up ethernet module */
+	immr->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin	*/
+	immr->im_ioport.iop_pcdir |=  0x0004; /* output		*/
+	immr->im_ioport.iop_pcso  &= ~0x0004; /* for clarity	*/
+	immr->im_ioport.iop_pcdat |=  0x0004; /* enable		*/
+
+	return (0);
+}
+#endif	/* CONFIG_NSCU */
+
 /* ------------------------------------------------------------------------- */
@@ -37,6 +37,9 @@
 The preloader must initialize the processor and then start u-boot. The board
 must be configured for a pre-loader (see 4.1)
  
+For the preloader, please see
+http://mailman.uclinux.org/pipermail/uclinux-dev/2003-December/023384.html
+
 U-boot is configured to run at 0x20000 at default. This can be configured by
 change TEXT_BASE in board/m5282evb/config.mk and CFG_MONITOR_BASE in
 include/configs/M5282EVB.h.
@@ -45,8 +45,6 @@
  
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
  
-#undef	CONFIG_CLOCKS_IN_MHZ		/* clocks passsed to Linux in Hz */
-
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
  
 #define CONFIG_PREBOOT	"echo;"	\
@@ -75,6 +73,8 @@
 	""
 #define CONFIG_BOOTCOMMAND	"run flash_self"
  
+#define CONFIG_MISC_INIT_R	  1
+
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
  
  
  
@@ -252,15 +252,8 @@
  *-----------------------------------------------------------------------
  * Reset PLL lock status sticky bit, timer expired status bit and timer
  * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
  */
-#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_PLPRCR							\
-		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-#else			/* up to 66 MHz we use a 1:1 clock */
 #define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-#endif	/* CONFIG_80MHz */
  
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
  
@@ -269,17 +262,9 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_SCCR	(/* SCCR_TBS  | */ \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
-#else			/* up to 66 MHz we use a 1:1 clock */
-#define CFG_SCCR	(SCCR_TBS     | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-#endif	/* CONFIG_80MHz */
  
 /*-----------------------------------------------------------------------
  * PCMCIA stuff
  
@@ -355,19 +340,8 @@
 /*
  * FLASH timing:
  */
-#if   defined(CONFIG_80MHz)
-/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | 0       | OR_CSNT_SAM | \
-				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
-#elif defined(CONFIG_66MHz)
-/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
 #define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
-#else		/*   50 MHz */
-/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
-				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
-#endif	/*CONFIG_??MHz */
  
 #define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 #define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
@@ -437,13 +411,9 @@
  * 66 Mhz => 66.000.000 / Divider = 129
  * 80 Mhz => 80.000.000 / Divider = 156
  */
-#if   defined(CONFIG_80MHz)
-#define CFG_MAMR_PTA		156
-#elif defined(CONFIG_66MHz)
-#define CFG_MAMR_PTA		129
-#else		/*   50 MHz */
-#define CFG_MAMR_PTA		 98
-#endif	/*CONFIG_??MHz */
+
+#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CFG_MAMR_PTA	98
  
 /*
  * For 16 MBit, refresh rates could be 31.3 us
...	...	@@ -5,6 +5,10 @@
5	5	* Patch by Stefan Roese, 15 Jul 2004:
6	6	cpu/ppc4xx/sdram.c rewritten now using get_ram_size()
7	7
	8	+* Fix NSCU config; add ethernet wakeup code.
	9	+
	10	+* Add link for preloader for Motorola Coldfire to RAEDME.m68k
	11	+
8	12	* Patch by Michael Bendzick, 12 Jul 2004:
9	13	fix output formatting in drivers/cfi_flash.c
10	14
...	...	@@ -445,12 +445,14 @@
445	445
446	446	#endif /* CONFIG_PS2MULT */
447	447
448		-/* ------------------------------------------------------------------------- */
	448	+/* ---------------------------------------------------------------------------- */
	449	+/* HMI10 specific stuff */
	450	+/* ---------------------------------------------------------------------------- */
449	451	#ifdef CONFIG_HMI10
450	452
451	453	int misc_init_r (void)
452	454	{
453		-#ifdef CONFIG_IDE_LED
	455	+# ifdef CONFIG_IDE_LED
454	456	volatile immap_t immap = (immap_t ) CFG_IMMR;
455	457
456	458	/* Configure PA15 as output port */
457	459
...	...	@@ -458,11 +460,11 @@
458	460	immap->im_ioport.iop_paodr \|= 0x0001;
459	461	immap->im_ioport.iop_papar &= ~0x0001;
460	462	immap->im_ioport.iop_padat &= ~0x0001; /* turn it off */
461		-#endif
	463	+# endif
462	464	return (0);
463	465	}
464	466
465		-#ifdef CONFIG_IDE_LED
	467	+# ifdef CONFIG_IDE_LED
466	468	void ide_led (uchar led, uchar status)
467	469	{
468	470	volatile immap_t immap = (immap_t ) CFG_IMMR;
469	471
...	...	@@ -474,8 +476,27 @@
474	476	immap->im_ioport.iop_padat &= ~0x0001;
475	477	}
476	478	}
477		-#endif
	479	+# endif
	480	+#endif /* CONFIG_HMI10 */
478	481
479		-#endif /* CONFIG_HMI10 */
	482	+/* ---------------------------------------------------------------------------- */
	483	+/* NSCU specific stuff */
	484	+/* ---------------------------------------------------------------------------- */
	485	+#ifdef CONFIG_NSCU
	486	+
	487	+int misc_init_r (void)
	488	+{
	489	+ volatile immap_t immr = (immap_t ) CFG_IMMR;
	490	+
	491	+ /* wake up ethernet module */
	492	+ immr->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin */
	493	+ immr->im_ioport.iop_pcdir \|= 0x0004; /* output */
	494	+ immr->im_ioport.iop_pcso &= ~0x0004; /* for clarity */
	495	+ immr->im_ioport.iop_pcdat \|= 0x0004; /* enable */
	496	+
	497	+ return (0);
	498	+}
	499	+#endif /* CONFIG_NSCU */
	500	+
480	501	/* ------------------------------------------------------------------------- */
...	...	@@ -37,6 +37,9 @@
37	37	The preloader must initialize the processor and then start u-boot. The board
38	38	must be configured for a pre-loader (see 4.1)
39	39
	40	+For the preloader, please see
	41	+http://mailman.uclinux.org/pipermail/uclinux-dev/2003-December/023384.html
	42	+
40	43	U-boot is configured to run at 0x20000 at default. This can be configured by
41	44	change TEXT_BASE in board/m5282evb/config.mk and CFG_MONITOR_BASE in
42	45	include/configs/M5282EVB.h.
...	...	@@ -45,8 +45,6 @@
45	45
46	46	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
47	47
48		-#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in Hz */
49		-
50	48	#define CONFIG_BOARD_TYPES 1 /* support board types */
51	49
52	50	#define CONFIG_PREBOOT "echo;" \
...	...	@@ -75,6 +73,8 @@
75	73	""
76	74	#define CONFIG_BOOTCOMMAND "run flash_self"
77	75
	76	+#define CONFIG_MISC_INIT_R 1
	77	+
78	78	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
79	79	#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
80	80
81	81
82	82
...	...	@@ -252,15 +252,8 @@
252	252	*-----------------------------------------------------------------------
253	253	* Reset PLL lock status sticky bit, timer expired status bit and timer
254	254	* interrupt status bit
255		- *
256		- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
257	255	*/
258		-#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
259		-#define CFG_PLPRCR \
260		- ( (5-1)<<PLPRCR_MF_SHIFT \| PLPRCR_TEXPS \| PLPRCR_TMIST )
261		-#else /* up to 66 MHz we use a 1:1 clock */
262	256	#define CFG_PLPRCR (PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
263		-#endif /* CONFIG_80MHz */
264	257
265	258	/*-----------------------------------------------------------------------
266	259	* SCCR - System Clock and reset Control Register 15-27
267	260
...	...	@@ -269,17 +262,9 @@
269	262	* power management and some other internal clocks
270	263	*/
271	264	#define SCCR_MASK SCCR_EBDF11
272		-#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
273		-#define CFG_SCCR (/* SCCR_TBS \| */ \
274		- SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	265	+#define CFG_SCCR (SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
275	266	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
276	267	SCCR_DFALCD00)
277		-#else /* up to 66 MHz we use a 1:1 clock */
278		-#define CFG_SCCR (SCCR_TBS \| \
279		- SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
280		- SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
281		- SCCR_DFALCD00)
282		-#endif /* CONFIG_80MHz */
283	268
284	269	/*-----------------------------------------------------------------------
285	270	* PCMCIA stuff
286	271
...	...	@@ -355,19 +340,8 @@
355	340	/*
356	341	* FLASH timing:
357	342	*/
358		-#if defined(CONFIG_80MHz)
359		-/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
360		-#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 \| 0 \| OR_CSNT_SAM \| \
361		- OR_SCY_3_CLK \| OR_EHTR \| OR_BI)
362		-#elif defined(CONFIG_66MHz)
363		-/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
364	343	#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 \| OR_TRLX \| OR_CSNT_SAM \| \
365	344	OR_SCY_3_CLK \| OR_EHTR \| OR_BI)
366		-#else /* 50 MHz */
367		-/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
368		-#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 \| OR_TRLX \| OR_CSNT_SAM \| \
369		- OR_SCY_2_CLK \| OR_EHTR \| OR_BI)
370		-#endif /CONFIG_??MHz /
371	345
372	346	#define CFG_OR0_REMAP (CFG_REMAP_OR_AM \| CFG_OR_TIMING_FLASH)
373	347	#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_FLASH)
...	...	@@ -437,13 +411,9 @@
437	411	* 66 Mhz => 66.000.000 / Divider = 129
438	412	* 80 Mhz => 80.000.000 / Divider = 156
439	413	*/
440		-#if defined(CONFIG_80MHz)
441		-#define CFG_MAMR_PTA 156
442		-#elif defined(CONFIG_66MHz)
443		-#define CFG_MAMR_PTA 129
444		-#else /* 50 MHz */
445		-#define CFG_MAMR_PTA 98
446		-#endif /CONFIG_??MHz /
	414	+
	415	+#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
	416	+#define CFG_MAMR_PTA 98
447	417
448	418	/*
449	419	* For 16 MBit, refresh rates could be 31.3 us