Eric Lee / smarc-uboot

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Commit d102c193f3f903055239f07ddbaab63715dbf82f

Authored by Haoran Wang
Committed by guoyin.chen
1 parent f5dd3579cf
Exists in smarc-imx_v2015.04_4.1.15_1.0.0_ga and in 1 other branch imx_v2015.04_4.1.15_1.0.0_ga

MA-7455 Import picosom boot codes 

Imported the picosom boot codes and board
configs from technexion.

Signed-off-by: Tapani Utriainen <tapani@technexion.com>
Signed-off-by: Haoran Wang <Haoran.Wang@freescale.com>

Showing 9 changed files with 1329 additions and 0 deletions Side-by-side Diff

... ... @@ -576,6 +576,10 @@
576 576 bool "Support mx6ul_14x14_lpddr2_arm2"
577 577 select CPU_V7
578 578  
  579 +config TARGET_PICOSOM_IMX6UL
  580 + bool "Support picosom-imx6ul"
  581 + select CPU_V7
  582 +
579 583 config TARGET_GW_VENTANA
580 584 bool "Support gw_ventana"
581 585 select CPU_V7
... ... @@ -880,6 +884,7 @@
880 884 source "board/freescale/mx6ul_14x14_evk/Kconfig"
881 885 source "board/freescale/mx6ul_14x14_ddr3_arm2/Kconfig"
882 886 source "board/freescale/mx6ul_14x14_lpddr2_arm2/Kconfig"
  887 +source "board/technexion/picosom-imx6ul/Kconfig"
883 888 source "board/freescale/vf610twr/Kconfig"
884 889 source "board/gateworks/gw_ventana/Kconfig"
885 890 source "board/genesi/mx51_efikamx/Kconfig"
board/technexion/picosom-imx6ul/Kconfig
Diff comments   View file @ d102c19
  1 +if TARGET_PICOSOM_IMX6UL
  2 +
  3 +config SYS_BOARD
  4 + default "picosom-imx6ul"
  5 +
  6 +config SYS_VENDOR
  7 + default "technexion"
  8 +
  9 +config SYS_SOC
  10 + default "mx6"
  11 +
  12 +config SYS_CONFIG_NAME
  13 + default "picosom-imx6ul"
  14 +
  15 +endif
board/technexion/picosom-imx6ul/MAINTAINERS
Diff comments   View file @ d102c19
  1 +Technexion PICOSOM-IMX6UL board
  2 +M: Richard Hu <richard.hu@technexion.com>
  3 +S: Maintained
  4 +F: board/picosom-imx6ul/
  5 +F: include/configs/picosom-imx6ul.h
  6 +F: configs/picosom-imx6ul_defconfig
board/technexion/picosom-imx6ul/Makefile
Diff comments   View file @ d102c19
  1 +# (C) Copyright 2015 Technexion Ltd.
  2 +# (C) Copyright 2015 Freescale Semiconductor, Inc.
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +#
  6 +
  7 +obj-y := picosom-imx6ul.o
board/technexion/picosom-imx6ul/imximage.cfg
Diff comments   View file @ d102c19
  1 +/*
  2 + * Copyright (C) 2015 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Refer docs/README.imxmage for more details about how-to configure
  7 + * and create imximage boot image
  8 + *
  9 + * The syntax is taken as close as possible with the kwbimage
  10 + */
  11 +
  12 +#define __ASSEMBLY__
  13 +#include <config.h>
  14 +
  15 +/* image version */
  16 +
  17 +IMAGE_VERSION 2
  18 +
  19 +/*
  20 + * Boot Device : one of
  21 + * spi/sd/nand/onenand, qspi/nor
  22 + */
  23 +
  24 +#ifdef CONFIG_SYS_BOOT_QSPI
  25 +BOOT_FROM qspi
  26 +#elif defined(CONFIG_SYS_BOOT_EIMNOR)
  27 +BOOT_FROM nor
  28 +#else
  29 +BOOT_FROM sd
  30 +#endif
  31 +
  32 +#ifdef CONFIG_USE_PLUGIN
  33 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  34 +PLUGIN board/freescale/mx6ul_14x14_evk/plugin.bin 0x00907000
  35 +#else
  36 +
  37 +#ifdef CONFIG_SECURE_BOOT
  38 +CSF CONFIG_CSF_SIZE
  39 +#endif
  40 +
  41 +/*
  42 + * Device Configuration Data (DCD)
  43 + *
  44 + * Each entry must have the format:
  45 + * Addr-type Address Value
  46 + *
  47 + * where:
  48 + * Addr-type register length (1,2 or 4 bytes)
  49 + * Address absolute address of the register
  50 + * value value to be stored in the register
  51 + */
  52 +
  53 +/* Enable all clocks */
  54 +DATA 4 0x020c4068 0xffffffff
  55 +DATA 4 0x020c406c 0xffffffff
  56 +DATA 4 0x020c4070 0xffffffff
  57 +DATA 4 0x020c4074 0xffffffff
  58 +DATA 4 0x020c4078 0xffffffff
  59 +DATA 4 0x020c407c 0xffffffff
  60 +DATA 4 0x020c4080 0xffffffff
  61 +
  62 +DATA 4 0x020E04B4 0x000C0000
  63 +DATA 4 0x020E04AC 0x00000000
  64 +DATA 4 0x020E027C 0x00000030
  65 +DATA 4 0x020E0250 0x00000030
  66 +DATA 4 0x020E024C 0x00000030
  67 +DATA 4 0x020E0490 0x00000030
  68 +DATA 4 0x020E0288 0x00000030
  69 +DATA 4 0x020E0270 0x00000000
  70 +DATA 4 0x020E0260 0x00000030
  71 +DATA 4 0x020E0264 0x00000030
  72 +DATA 4 0x020E04A0 0x00000030
  73 +DATA 4 0x020E0494 0x00020000
  74 +DATA 4 0x020E0280 0x00000030
  75 +DATA 4 0x020E0284 0x00000030
  76 +DATA 4 0x020E04B0 0x00020000
  77 +DATA 4 0x020E0498 0x00000030
  78 +DATA 4 0x020E04A4 0x00000030
  79 +DATA 4 0x020E0244 0x00000030
  80 +DATA 4 0x020E0248 0x00000030
  81 +DATA 4 0x021B001C 0x00008000
  82 +DATA 4 0x021B0800 0xA1390003
  83 +DATA 4 0x021B080C 0x00000000
  84 +DATA 4 0x021B083C 0x01380134
  85 +DATA 4 0x021B0848 0x40404244
  86 +DATA 4 0x021B0850 0x40405050
  87 +DATA 4 0x021B081C 0x33333333
  88 +DATA 4 0x021B0820 0x33333333
  89 +DATA 4 0x021B082C 0xf3333333
  90 +DATA 4 0x021B0830 0xf3333333
  91 +DATA 4 0x021B08C0 0x00921012
  92 +DATA 4 0x021B08b8 0x00000800
  93 +DATA 4 0x021B0004 0x0002002D
  94 +DATA 4 0x021B0008 0x00333030
  95 +DATA 4 0x021B000C 0x676B52F3
  96 +DATA 4 0x021B0010 0xB66D8B63
  97 +DATA 4 0x021B0014 0x01FF00DB
  98 +DATA 4 0x021B0018 0x00201740
  99 +DATA 4 0x021B001C 0x00008000
  100 +DATA 4 0x021B002C 0x000026D2
  101 +DATA 4 0x021B0030 0x006B1023
  102 +DATA 4 0x021B0040 0x00000047
  103 +DATA 4 0x021B0000 0x83180000
  104 +DATA 4 0x021B001C 0x02008032
  105 +DATA 4 0x021B001C 0x00008033
  106 +DATA 4 0x021B001C 0x00048031
  107 +DATA 4 0x021B001C 0x15208030
  108 +DATA 4 0x021B001C 0x04008040
  109 +DATA 4 0x021B0020 0x00000800
  110 +DATA 4 0x021B0818 0x00000227
  111 +DATA 4 0x021B0004 0x0002552D
  112 +DATA 4 0x021B0404 0x00011006
  113 +DATA 4 0x021B001C 0x00000000
  114 +#endif
board/technexion/picosom-imx6ul/picosom-imx6ul.c
Diff comments   View file @ d102c19
  1 +/*
  2 + * Copyright (C) 2015 Technexion Ltd.
  3 + *
  4 + * Author: Richard Hu <richard.hu@technexion.com>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <asm/arch/clock.h>
  10 +#include <asm/arch/iomux.h>
  11 +#include <asm/arch/imx-regs.h>
  12 +#include <asm/arch/crm_regs.h>
  13 +#include <asm/arch/mx6-pins.h>
  14 +#include <asm/arch/sys_proto.h>
  15 +#include <asm/gpio.h>
  16 +#include <asm/imx-common/iomux-v3.h>
  17 +#include <asm/imx-common/boot_mode.h>
  18 +#include <asm/imx-common/mxc_i2c.h>
  19 +#include <asm/io.h>
  20 +#include <common.h>
  21 +#include <fsl_esdhc.h>
  22 +#include <i2c.h>
  23 +#include <linux/sizes.h>
  24 +#include <linux/fb.h>
  25 +#include <miiphy.h>
  26 +#include <mmc.h>
  27 +#include <mxsfb.h>
  28 +#include <netdev.h>
  29 +#include <usb.h>
  30 +#include <usb/ehci-fsl.h>
  31 +
  32 +#ifdef CONFIG_POWER
  33 +#include <power/pmic.h>
  34 +#include <power/pfuze300_pmic.h>
  35 +#include "../../freescale/common/pfuze.h"
  36 +#endif
  37 +
  38 +#ifdef CONFIG_FSL_FASTBOOT
  39 +#include <fsl_fastboot.h>
  40 +#ifdef CONFIG_ANDROID_RECOVERY
  41 +#include <recovery.h>
  42 +#endif
  43 +#endif /*CONFIG_FSL_FASTBOOT*/
  44 +
  45 +
  46 +DECLARE_GLOBAL_DATA_PTR;
  47 +
  48 +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  49 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  50 + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  51 +
  52 +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  53 + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
  54 + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  55 +
  56 +#define USDHC_SD_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  57 + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
  58 + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  59 +
  60 +
  61 +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  62 + PAD_CTL_SPEED_HIGH | \
  63 + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  64 +
  65 +#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  66 + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
  67 +
  68 +
  69 +#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  70 +
  71 +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  72 + PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
  73 +
  74 +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  75 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  76 + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  77 + PAD_CTL_ODE)
  78 +
  79 +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  80 + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
  81 +
  82 +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
  83 +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
  84 + PAD_CTL_SRE_FAST)
  85 +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
  86 +
  87 +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  88 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  89 + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  90 +
  91 +#define SPI_PAD_CTRL (PAD_CTL_HYS | \
  92 + PAD_CTL_SPEED_MED | \
  93 + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  94 +
  95 +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  96 + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
  97 + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  98 +
  99 +#ifdef CONFIG_SYS_I2C_MXC
  100 +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  101 +/* I2C2 for PMIC */
  102 +struct i2c_pads_info i2c_pad_info1 = {
  103 + .scl = {
  104 + .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC,
  105 + .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC,
  106 + .gp = IMX_GPIO_NR(1, 2),
  107 + },
  108 + .sda = {
  109 + .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC,
  110 + .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC,
  111 + .gp = IMX_GPIO_NR(1, 3),
  112 + },
  113 +};
  114 +#endif
  115 +
  116 +int dram_init(void)
  117 +{
  118 + gd->ram_size = PHYS_SDRAM_SIZE;
  119 +
  120 + return 0;
  121 +}
  122 +
  123 +static iomux_v3_cfg_t const uart6_pads[] = {
  124 + MX6_PAD_CSI_MCLK__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  125 + MX6_PAD_CSI_PIXCLK__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  126 +};
  127 +
  128 +static iomux_v3_cfg_t const usdhc1_pads[] = {
  129 + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  130 + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  131 + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  132 + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  133 + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  134 + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  135 + /* CD */
  136 + MX6_PAD_UART1_CTS_B__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
  137 +};
  138 +
  139 +#ifdef CONFIG_SYS_USE_NAND
  140 +static iomux_v3_cfg_t const nand_pads[] = {
  141 + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  142 + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  143 + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  144 + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  145 + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  146 + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  147 + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  148 + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  149 + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  150 + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  151 + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  152 + MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  153 + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  154 + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  155 + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  156 + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  157 + MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  158 +};
  159 +
  160 +static void setup_gpmi_nand(void)
  161 +{
  162 + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  163 +
  164 + /* config gpmi nand iomux */
  165 + imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
  166 +
  167 + clrbits_le32(&mxc_ccm->CCGR4,
  168 + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  169 + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  170 + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  171 + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  172 + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  173 +
  174 + /*
  175 + * config gpmi and bch clock to 100 MHz
  176 + * bch/gpmi select PLL2 PFD2 400M
  177 + * 100M = 400M / 4
  178 + */
  179 + clrbits_le32(&mxc_ccm->cscmr1,
  180 + MXC_CCM_CSCMR1_BCH_CLK_SEL |
  181 + MXC_CCM_CSCMR1_GPMI_CLK_SEL);
  182 + clrsetbits_le32(&mxc_ccm->cscdr1,
  183 + MXC_CCM_CSCDR1_BCH_PODF_MASK |
  184 + MXC_CCM_CSCDR1_GPMI_PODF_MASK,
  185 + (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
  186 + (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
  187 +
  188 + /* enable gpmi and bch clock gating */
  189 + setbits_le32(&mxc_ccm->CCGR4,
  190 + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  191 + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  192 + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  193 + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  194 + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  195 +
  196 + /* enable apbh clock gating */
  197 + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  198 +}
  199 +#endif
  200 +
  201 +#ifdef CONFIG_FEC_MXC
  202 +static iomux_v3_cfg_t const fec_pads[] = {
  203 + MX6_PAD_ENET1_TX_EN__ENET2_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL),
  204 + MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
  205 +
  206 + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  207 + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  208 + MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  209 + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  210 +
  211 + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  212 + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  213 + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  214 + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
  215 +
  216 + MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
  217 +};
  218 +
  219 +#define RMII_PHY_RESET IMX_GPIO_NR(1, 28)
  220 +
  221 +static void setup_iomux_fec(int fec_id)
  222 +{
  223 + imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
  224 +}
  225 +#endif
  226 +
  227 +static void setup_iomux_uart(void)
  228 +{
  229 + imx_iomux_v3_setup_multiple_pads(uart6_pads, ARRAY_SIZE(uart6_pads));
  230 +}
  231 +
  232 +#ifdef CONFIG_FSL_ESDHC
  233 +static struct fsl_esdhc_cfg usdhc_cfg[2] = {
  234 + {USDHC1_BASE_ADDR, 0, 4},
  235 +};
  236 +
  237 +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 18)
  238 +
  239 +int mmc_get_env_devno(void)
  240 +{
  241 + u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
  242 + int dev_no;
  243 + u32 bootsel;
  244 +
  245 + bootsel = (soc_sbmr & 0x000000FF) >> 6 ;
  246 +
  247 + /* If not boot from sd/mmc, use default value */
  248 + if (bootsel != 1)
  249 + return CONFIG_SYS_MMC_ENV_DEV;
  250 +
  251 + /* BOOT_CFG2[3] and BOOT_CFG2[4] */
  252 + dev_no = (soc_sbmr & 0x00001800) >> 11;
  253 +
  254 + return dev_no;
  255 +}
  256 +
  257 +int mmc_map_to_kernel_blk(int dev_no)
  258 +{
  259 + return dev_no;
  260 +}
  261 +
  262 +int board_mmc_getcd(struct mmc *mmc)
  263 +{
  264 + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  265 + int ret = 0;
  266 +
  267 + switch (cfg->esdhc_base) {
  268 + case USDHC1_BASE_ADDR:
  269 + ret = !gpio_get_value(USDHC1_CD_GPIO);
  270 + break;
  271 + }
  272 +
  273 + return ret;
  274 +
  275 +}
  276 +
  277 +int board_mmc_init(bd_t *bis)
  278 +{
  279 + int i, ret;
  280 +
  281 + /*
  282 + * According to the board_mmc_init() the following map is done:
  283 + * (U-boot device node) (Physical Port)
  284 + * mmc0 USDHC1
  285 + */
  286 + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  287 + switch (i) {
  288 + case 0:
  289 + imx_iomux_v3_setup_multiple_pads(
  290 + usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
  291 + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  292 + break;
  293 + default:
  294 + printf("Warning: you configured more USDHC controllers"
  295 + "(%d) than supported by the board\n", i + 1);
  296 + return -EINVAL;
  297 + }
  298 +
  299 + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  300 + if (ret) {
  301 + printf("Warning: failed to initialize mmc dev %d\n", i);
  302 + return ret;
  303 + }
  304 + }
  305 +
  306 + return 0;
  307 +}
  308 +
  309 +int check_mmc_autodetect(void)
  310 +{
  311 + char *autodetect_str = getenv("mmcautodetect");
  312 +
  313 + if ((autodetect_str != NULL) &&
  314 + (strcmp(autodetect_str, "yes") == 0)) {
  315 + return 1;
  316 + }
  317 +
  318 + return 0;
  319 +}
  320 +
  321 +void board_late_mmc_init(void)
  322 +{
  323 + char cmd[32];
  324 + char mmcblk[32];
  325 + u32 dev_no = mmc_get_env_devno();
  326 +
  327 + if (!check_mmc_autodetect())
  328 + return;
  329 +
  330 + setenv_ulong("mmcdev", dev_no);
  331 +
  332 + /* Set mmcblk env */
  333 + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
  334 + mmc_map_to_kernel_blk(dev_no));
  335 + setenv("mmcroot", mmcblk);
  336 +
  337 + sprintf(cmd, "mmc dev %d", dev_no);
  338 + run_command(cmd, 0);
  339 +}
  340 +#endif
  341 +
  342 +#ifdef CONFIG_VIDEO_MXS
  343 +static iomux_v3_cfg_t const lcd_pads[] = {
  344 + MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
  345 + MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
  346 + MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
  347 + MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
  348 + MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  349 + MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  350 + MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  351 + MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  352 + MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  353 + MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  354 + MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  355 + MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  356 + MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  357 + MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  358 + MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  359 + MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  360 + MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  361 + MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  362 + MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  363 + MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  364 + MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  365 + MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  366 + MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  367 + MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  368 + MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  369 + MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  370 + MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  371 + MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  372 +
  373 + /* LCD_RST */
  374 + MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
  375 +
  376 + /*
  377 + * Use GPIO for Brightness adjustment, duty cycle = period.
  378 + */
  379 + MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
  380 +};
  381 +
  382 +struct lcd_panel_info_t {
  383 + unsigned int lcdif_base_addr;
  384 + int depth;
  385 + void (*enable)(struct lcd_panel_info_t const *dev);
  386 + struct fb_videomode mode;
  387 +};
  388 +
  389 +void do_enable_parallel_lcd(struct lcd_panel_info_t const *dev)
  390 +{
  391 + enable_lcdif_clock(dev->lcdif_base_addr);
  392 +
  393 + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
  394 +
  395 + /* Reset the LCD */
  396 + gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
  397 + udelay(500);
  398 + gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);
  399 +
  400 + /* Set Brightness to high */
  401 + gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
  402 +}
  403 +
  404 +static struct lcd_panel_info_t const displays[] = {{
  405 + .lcdif_base_addr = LCDIF1_BASE_ADDR,
  406 + .depth = 24,
  407 + .enable = do_enable_parallel_lcd,
  408 + .mode = {
  409 + .name = "TFT43AB",
  410 + .xres = 480,
  411 + .yres = 272,
  412 + .pixclock = 108695,
  413 + .left_margin = 8,
  414 + .right_margin = 4,
  415 + .upper_margin = 2,
  416 + .lower_margin = 4,
  417 + .hsync_len = 41,
  418 + .vsync_len = 10,
  419 + .sync = 0,
  420 + .vmode = FB_VMODE_NONINTERLACED
  421 +} } };
  422 +
  423 +int board_video_skip(void)
  424 +{
  425 + int i;
  426 + int ret;
  427 + char const *panel = getenv("panel");
  428 + if (!panel) {
  429 + panel = displays[0].mode.name;
  430 + printf("No panel detected: default to %s\n", panel);
  431 + i = 0;
  432 + } else {
  433 + for (i = 0; i < ARRAY_SIZE(displays); i++) {
  434 + if (!strcmp(panel, displays[i].mode.name))
  435 + break;
  436 + }
  437 + }
  438 + if (i < ARRAY_SIZE(displays)) {
  439 + ret = mxs_lcd_panel_setup(displays[i].mode, displays[i].depth,
  440 + displays[i].lcdif_base_addr);
  441 + if (!ret) {
  442 + if (displays[i].enable)
  443 + displays[i].enable(displays+i);
  444 + printf("Display: %s (%ux%u)\n",
  445 + displays[i].mode.name,
  446 + displays[i].mode.xres,
  447 + displays[i].mode.yres);
  448 + } else
  449 + printf("LCD %s cannot be configured: %d\n",
  450 + displays[i].mode.name, ret);
  451 + } else {
  452 + printf("unsupported panel %s\n", panel);
  453 + return -EINVAL;
  454 + }
  455 +
  456 + return 0;
  457 +}
  458 +#endif
  459 +
  460 +#ifdef CONFIG_FEC_MXC
  461 +int board_eth_init(bd_t *bis)
  462 +{
  463 + int ret;
  464 +
  465 + setup_iomux_fec(CONFIG_FEC_ENET_DEV);
  466 +
  467 + gpio_direction_output(RMII_PHY_RESET, 0);
  468 + udelay(500);
  469 + gpio_direction_output(RMII_PHY_RESET, 1);
  470 +
  471 + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
  472 + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
  473 + if (ret)
  474 + printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__);
  475 +
  476 + return 0;
  477 +}
  478 +
  479 +static int setup_fec(int fec_id)
  480 +{
  481 + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
  482 + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
  483 + int ret;
  484 +
  485 + if (0 == fec_id) {
  486 + /* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]*/
  487 + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
  488 + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
  489 + } else {
  490 + /* Use 50M anatop loopback REF_CLK2 for ENET2, clear gpr1[14], set gpr1[18]*/
  491 + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
  492 + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
  493 + }
  494 +
  495 + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
  496 + if (ret)
  497 + return ret;
  498 +
  499 + enable_enet_clk(1);
  500 +
  501 + return 0;
  502 +}
  503 +
  504 +int board_phy_config(struct phy_device *phydev)
  505 +{
  506 +
  507 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
  508 +
  509 + if (phydev->drv->config)
  510 + phydev->drv->config(phydev);
  511 +
  512 + return 0;
  513 +}
  514 +#endif
  515 +
  516 +#ifdef CONFIG_USB_EHCI_MX6
  517 +#define USB_OTHERREGS_OFFSET 0x800
  518 +#define UCTRL_PWR_POL (1 << 9)
  519 +
  520 +static iomux_v3_cfg_t const usb_otg_pads[] = {
  521 + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
  522 +};
  523 +
  524 +/* At default the 3v3 enables the MIC2026 for VBUS power */
  525 +static void setup_usb(void)
  526 +{
  527 + imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
  528 + ARRAY_SIZE(usb_otg_pads));
  529 +}
  530 +
  531 +int board_usb_phy_mode(int port)
  532 +{
  533 + if (port == 1)
  534 + return USB_INIT_HOST;
  535 + else
  536 + return usb_phy_mode(port);
  537 +}
  538 +
  539 +int board_ehci_hcd_init(int port)
  540 +{
  541 + u32 *usbnc_usb_ctrl;
  542 +
  543 + if (port > 1)
  544 + return -EINVAL;
  545 +
  546 + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
  547 + port * 4);
  548 +
  549 + /* Set Power polarity */
  550 + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
  551 +
  552 + return 0;
  553 +}
  554 +#endif
  555 +
  556 +int board_early_init_f(void)
  557 +{
  558 + setup_iomux_uart();
  559 +
  560 + return 0;
  561 +}
  562 +
  563 +#ifdef CONFIG_POWER
  564 +#define I2C_PMIC 0
  565 +static struct pmic *pfuze;
  566 +int power_init_board(void)
  567 +{
  568 + int ret;
  569 + unsigned int reg, rev_id;
  570 +
  571 + ret = power_pfuze300_init(I2C_PMIC);
  572 + if (ret)
  573 + return ret;
  574 +
  575 + pfuze = pmic_get("PFUZE300");
  576 + ret = pmic_probe(pfuze);
  577 + if (ret)
  578 + return ret;
  579 +
  580 + pmic_reg_read(pfuze, PFUZE300_DEVICEID, &reg);
  581 + pmic_reg_read(pfuze, PFUZE300_REVID, &rev_id);
  582 + printf("PMIC: PFUZE300 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
  583 +
  584 + /* disable Low Power Mode during standby mode */
  585 + pmic_reg_read(pfuze, PFUZE300_LDOGCTL, &reg);
  586 + reg |= 0x1;
  587 + pmic_reg_write(pfuze, PFUZE300_LDOGCTL, reg);
  588 +
  589 + /* SW1B step ramp up time from 2us to 4us/25mV */
  590 + reg = 0x40;
  591 + pmic_reg_write(pfuze, PFUZE300_SW1BCONF, reg);
  592 +
  593 + /* SW1B mode to APS/PFM */
  594 + reg = 0xc;
  595 + pmic_reg_write(pfuze, PFUZE300_SW1BMODE, reg);
  596 +
  597 + /* SW1B standby voltage set to 0.975V */
  598 + reg = 0xb;
  599 + pmic_reg_write(pfuze, PFUZE300_SW1BSTBY, reg);
  600 +
  601 + return 0;
  602 +}
  603 +
  604 +#ifdef CONFIG_LDO_BYPASS_CHECK
  605 +void ldo_mode_set(int ldo_bypass)
  606 +{
  607 + unsigned int value;
  608 + u32 vddarm;
  609 +
  610 + struct pmic *p = pfuze;
  611 +
  612 + if (!p) {
  613 + printf("No PMIC found!\n");
  614 + return;
  615 + }
  616 +
  617 + /* switch to ldo_bypass mode */
  618 + if (ldo_bypass) {
  619 + prep_anatop_bypass();
  620 + /* decrease VDDARM to 1.275V */
  621 + pmic_reg_read(pfuze, PFUZE300_SW1BVOLT, &value);
  622 + value &= ~0x1f;
  623 + value |= PFUZE300_SW1AB_SETP(1275);
  624 + pmic_reg_write(pfuze, PFUZE300_SW1BVOLT, value);
  625 +
  626 + set_anatop_bypass(1);
  627 + vddarm = PFUZE300_SW1AB_SETP(1175);
  628 +
  629 + pmic_reg_read(pfuze, PFUZE300_SW1BVOLT, &value);
  630 + value &= ~0x1f;
  631 + value |= vddarm;
  632 + pmic_reg_write(pfuze, PFUZE300_SW1BVOLT, value);
  633 +
  634 + finish_anatop_bypass();
  635 +
  636 + printf("switch to ldo_bypass mode!\n");
  637 + }
  638 +}
  639 +#endif
  640 +#endif
  641 +
  642 +int board_init(void)
  643 +{
  644 + /* Address of boot parameters */
  645 + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  646 +
  647 +#ifdef CONFIG_SYS_I2C_MXC
  648 + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  649 +#endif
  650 +
  651 +#ifdef CONFIG_FEC_MXC
  652 + setup_fec(CONFIG_FEC_ENET_DEV);
  653 +#endif
  654 +
  655 +#ifdef CONFIG_SYS_USE_NAND
  656 + setup_gpmi_nand();
  657 +#endif
  658 +
  659 +#ifdef CONFIG_USB_EHCI_MX6
  660 + setup_usb();
  661 +#endif
  662 +
  663 + return 0;
  664 +}
  665 +
  666 +#ifdef CONFIG_CMD_BMODE
  667 +static const struct boot_mode board_boot_modes[] = {
  668 + /* 4 bit bus width */
  669 + {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
  670 + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  671 + {NULL, 0},
  672 +};
  673 +#endif
  674 +
  675 +int board_late_init(void)
  676 +{
  677 +#ifdef CONFIG_CMD_BMODE
  678 + add_board_boot_modes(board_boot_modes);
  679 +#endif
  680 +
  681 +#ifdef CONFIG_ENV_IS_IN_MMC
  682 + board_late_mmc_init();
  683 +#endif
  684 +
  685 + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
  686 +
  687 + return 0;
  688 +}
  689 +
  690 +u32 get_board_rev(void)
  691 +{
  692 + return get_cpu_rev();
  693 +}
  694 +
  695 +int checkboard(void)
  696 +{
  697 + puts("Board: PicoSOM i.mx6UL\n");
  698 +
  699 + return 0;
  700 +}
  701 +
  702 +#ifdef CONFIG_FSL_FASTBOOT
  703 +
  704 +void board_fastboot_setup(void)
  705 +{
  706 + switch (get_boot_device()) {
  707 +#if defined(CONFIG_FASTBOOT_STORAGE_MMC)
  708 + case SD1_BOOT:
  709 + case MMC1_BOOT:
  710 + if (!getenv("fastboot_dev"))
  711 + setenv("fastboot_dev", "mmc0");
  712 + if (!getenv("bootcmd"))
  713 + setenv("bootcmd", "boota mmc0");
  714 + break;
  715 + case SD2_BOOT:
  716 + case MMC2_BOOT:
  717 + if (!getenv("fastboot_dev"))
  718 + setenv("fastboot_dev", "mmc1");
  719 + if (!getenv("bootcmd"))
  720 + setenv("bootcmd", "boota mmc1");
  721 + break;
  722 +#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
  723 +#if defined(CONFIG_FASTBOOT_STORAGE_NAND)
  724 + case NAND_BOOT:
  725 + if (!getenv("fastboot_dev"))
  726 + setenv("fastboot_dev", "nand");
  727 + if (!getenv("fbparts"))
  728 + setenv("fbparts", ANDROID_FASTBOOT_NAND_PARTS);
  729 + if (!getenv("bootcmd"))
  730 + setenv("bootcmd",
  731 + "nand read ${loadaddr} ${boot_nand_offset} "
  732 + "${boot_nand_size};boota ${loadaddr}");
  733 + break;
  734 +#endif /*CONFIG_FASTBOOT_STORAGE_NAND*/
  735 +
  736 + default:
  737 + printf("unsupported boot devices\n");
  738 + break;
  739 + }
  740 +}
  741 +
  742 +#ifdef CONFIG_ANDROID_RECOVERY
  743 +int check_recovery_cmd_file(void)
  744 +{
  745 + int recovery_mode = 0;
  746 +
  747 + recovery_mode = recovery_check_and_clean_flag();
  748 +
  749 + return recovery_mode;
  750 +}
  751 +
  752 +void board_recovery_setup(void)
  753 +{
  754 + int bootdev = get_boot_device();
  755 +
  756 + switch (bootdev) {
  757 +#if defined(CONFIG_FASTBOOT_STORAGE_MMC)
  758 + case SD1_BOOT:
  759 + case MMC1_BOOT:
  760 + if (!getenv("bootcmd_android_recovery"))
  761 + setenv("bootcmd_android_recovery", "boota mmc0 recovery");
  762 + break;
  763 + case SD2_BOOT:
  764 + case MMC2_BOOT:
  765 + if (!getenv("bootcmd_android_recovery"))
  766 + setenv("bootcmd_android_recovery", "boota mmc1 recovery");
  767 + break;
  768 +#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
  769 +#if defined(CONFIG_FASTBOOT_STORAGE_NAND)
  770 + case NAND_BOOT:
  771 + if (!getenv("bootcmd_android_recovery"))
  772 + setenv("bootcmd_android_recovery",
  773 + "nand read ${loadaddr} ${recovery_nand_offset} "
  774 + "${recovery_nand_size};boota ${loadaddr}");
  775 + break;
  776 +#endif /*CONFIG_FASTBOOT_STORAGE_NAND*/
  777 +
  778 + default:
  779 + printf("Unsupported bootup device for recovery: dev: %d\n",
  780 + bootdev);
  781 + return;
  782 + }
  783 +
  784 + printf("setup env for recovery..\n");
  785 + setenv("bootcmd", "run bootcmd_android_recovery");
  786 +}
  787 +#endif /*CONFIG_ANDROID_RECOVERY*/
  788 +
  789 +#endif /*CONFIG_FSL_FASTBOOT*/
configs/picosom-imx6ul-qspi_defconfig
Diff comments   View file @ d102c19
  1 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/picosom-imx6ul/imximage.cfg,MX6UL,SYS_BOOT_QSPI"
  2 +CONFIG_ARM=y
  3 +CONFIG_TARGET_PICOSOM_IMX6UL=y
  4 +CONFIG_DM=y
  5 +CONFIG_DM_THERMAL=y
configs/picosom-imx6ul_defconfig
Diff comments   View file @ d102c19
  1 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/picosom-imx6ul/imximage.cfg,MX6UL"
  2 +CONFIG_ARM=y
  3 +CONFIG_TARGET_PICOSOM_IMX6UL=y
  4 +CONFIG_DM=y
  5 +CONFIG_DM_THERMAL=y
include/configs/picosom-imx6ul.h
Diff comments   View file @ d102c19
  1 +/*
  2 + * Copyright (C) 2015 Technexion Ltd.
  3 + *
  4 + * Configuration settings for the Technexion PicoSOM i.mx6UL board.
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +#ifndef __PICOSOM_IMX6UL_CONFIG_H
  9 +#define __PICOSOM_IMX6UL_CONFIG_H
  10 +
  11 +
  12 +#include <asm/arch/imx-regs.h>
  13 +#include <linux/sizes.h>
  14 +#include "mx6_common.h"
  15 +#include <asm/imx-common/gpio.h>
  16 +
  17 +#define CONFIG_MX6
  18 +#define CONFIG_ROM_UNIFIED_SECTIONS
  19 +#define CONFIG_SYS_GENERIC_BOARD
  20 +#define CONFIG_DISPLAY_CPUINFO
  21 +#define CONFIG_DISPLAY_BOARDINFO
  22 +
  23 +/* uncomment for SECURE mode support */
  24 +/* #define CONFIG_SECURE_BOOT */
  25 +
  26 +#ifdef CONFIG_SECURE_BOOT
  27 +#ifndef CONFIG_CSF_SIZE
  28 +#define CONFIG_CSF_SIZE 0x4000
  29 +#endif
  30 +#endif
  31 +
  32 +#define CONFIG_CMDLINE_TAG
  33 +#define CONFIG_SETUP_MEMORY_TAGS
  34 +#define CONFIG_INITRD_TAG
  35 +#define CONFIG_REVISION_TAG
  36 +
  37 +/* Size of malloc() pool */
  38 +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
  39 +
  40 +#define CONFIG_BOARD_EARLY_INIT_F
  41 +#define CONFIG_BOARD_LATE_INIT
  42 +#define CONFIG_MXC_GPIO
  43 +
  44 +#define CONFIG_MXC_UART
  45 +#define CONFIG_MXC_UART_BASE UART6_BASE_ADDR
  46 +
  47 +/* allow to overwrite serial and ethaddr */
  48 +#define CONFIG_ENV_OVERWRITE
  49 +#define CONFIG_CONS_INDEX 1
  50 +#define CONFIG_BAUDRATE 115200
  51 +
  52 +#define CONFIG_CMD_FUSE
  53 +#ifdef CONFIG_CMD_FUSE
  54 +#define CONFIG_MXC_OCOTP
  55 +#endif
  56 +
  57 +/* MMC Configs */
  58 +#define CONFIG_FSL_USDHC
  59 +#ifdef CONFIG_FSL_USDHC
  60 +#define CONFIG_FSL_ESDHC
  61 +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
  62 +
  63 +#define CONFIG_SYS_FSL_USDHC_NUM 1
  64 +
  65 +#define CONFIG_MMC
  66 +#define CONFIG_CMD_MMC
  67 +#define CONFIG_GENERIC_MMC
  68 +#define CONFIG_CMD_FAT
  69 +#define CONFIG_DOS_PARTITION
  70 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
  71 +#endif
  72 +
  73 +#undef CONFIG_BOOTM_NETBSD
  74 +#undef CONFIG_BOOTM_PLAN9
  75 +#undef CONFIG_BOOTM_RTEMS
  76 +
  77 +#undef CONFIG_CMD_EXPORTENV
  78 +#undef CONFIG_CMD_IMPORTENV
  79 +
  80 +#define CONFIG_CMD_NET
  81 +#ifdef CONFIG_CMD_NET
  82 +#define CONFIG_CMD_PING
  83 +#define CONFIG_CMD_DHCP
  84 +#define CONFIG_CMD_MII
  85 +#define CONFIG_FEC_MXC
  86 +#define CONFIG_MII
  87 +#define CONFIG_FEC_ENET_DEV 1
  88 +
  89 +#if (CONFIG_FEC_ENET_DEV == 0)
  90 +#define IMX_FEC_BASE ENET_BASE_ADDR
  91 +#define CONFIG_FEC_MXC_PHYADDR 0x2
  92 +#define CONFIG_FEC_XCV_TYPE RMII
  93 +#elif (CONFIG_FEC_ENET_DEV == 1)
  94 +#define IMX_FEC_BASE ENET2_BASE_ADDR
  95 +#define CONFIG_FEC_MXC_PHYADDR 0x1 /* need board rework */
  96 +#define CONFIG_FEC_XCV_TYPE RMII
  97 +#endif
  98 +#define CONFIG_ETHPRIME "FEC"
  99 +
  100 +#define CONFIG_PHYLIB
  101 +#define CONFIG_PHY_MICREL
  102 +#define CONFIG_FEC_DMA_MINALIGN 64
  103 +#endif
  104 +
  105 +/* allow to overwrite serial and ethaddr */
  106 +#define CONFIG_ENV_OVERWRITE
  107 +#define CONFIG_CONS_INDEX 1
  108 +
  109 +/* I2C configs */
  110 +#define CONFIG_CMD_I2C
  111 +#ifdef CONFIG_CMD_I2C
  112 +#define CONFIG_SYS_I2C
  113 +#define CONFIG_SYS_I2C_MXC
  114 +#define CONFIG_SYS_I2C_SPEED 100000
  115 +#endif
  116 +
  117 +
  118 +#define CONFIG_DEFAULT_FDT_FILE "imx6ul-picosom.dtb"
  119 +#define PHYS_SDRAM_SIZE SZ_256M
  120 +#define CONFIG_BOOTARGS_CMA_SIZE "cma=96M "
  121 +
  122 +/* PMIC */
  123 +#define CONFIG_POWER
  124 +#define CONFIG_POWER_I2C
  125 +#define CONFIG_POWER_PFUZE300
  126 +#define CONFIG_POWER_PFUZE300_I2C_ADDR 0x08
  127 +
  128 +
  129 +/* #define CONFIG_VIDEO */
  130 +
  131 +/* Command definition */
  132 +#include <config_cmd_default.h>
  133 +
  134 +#undef CONFIG_CMD_IMLS
  135 +
  136 +#define CONFIG_BOOTDELAY 3
  137 +
  138 +#define CONFIG_LOADADDR 0x80800000
  139 +#define CONFIG_SYS_TEXT_BASE 0x87800000
  140 +
  141 +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
  142 +#ifdef CONFIG_SYS_BOOT_NAND
  143 +#define CONFIG_MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs) "
  144 +#else
  145 +#define CONFIG_MFG_NAND_PARTITION ""
  146 +#endif
  147 +
  148 +#ifdef CONFIG_VIDEO
  149 +#define CONFIG_VIDEO_MODE \
  150 + "panel=TFT43AB\0"
  151 +#else
  152 +#define CONFIG_VIDEO_MODE ""
  153 +#endif
  154 +
  155 +#define CONFIG_MFG_ENV_SETTINGS \
  156 + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
  157 + CONFIG_BOOTARGS_CMA_SIZE \
  158 + "rdinit=/linuxrc " \
  159 + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
  160 + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
  161 + "g_mass_storage.iSerialNumber=\"\" "\
  162 + CONFIG_MFG_NAND_PARTITION \
  163 + "clk_ignore_unused "\
  164 + "\0" \
  165 + "initrd_addr=0x83800000\0" \
  166 + "initrd_high=0xffffffff\0" \
  167 + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
  168 +
  169 +#if defined(CONFIG_SYS_BOOT_NAND)
  170 +#define CONFIG_EXTRA_ENV_SETTINGS \
  171 + CONFIG_MFG_ENV_SETTINGS \
  172 + CONFIG_VIDEO_MODE \
  173 + "fdt_addr=0x83000000\0" \
  174 + "fdt_high=0xffffffff\0" \
  175 + "console=ttymxc5\0" \
  176 + "bootargs=console=ttymxc5,115200 ubi.mtd=3 " \
  177 + "root=ubi0:rootfs rootfstype=ubifs " \
  178 + CONFIG_BOOTARGS_CMA_SIZE \
  179 + "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs)\0"\
  180 + "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\
  181 + "nand read ${fdt_addr} 0x5000000 0x100000;"\
  182 + "bootz ${loadaddr} - ${fdt_addr}\0"
  183 +
  184 +#else
  185 +#define CONFIG_EXTRA_ENV_SETTINGS \
  186 + CONFIG_MFG_ENV_SETTINGS \
  187 + CONFIG_VIDEO_MODE \
  188 + "script=boot.scr\0" \
  189 + "image=zImage\0" \
  190 + "console=ttymxc5\0" \
  191 + "fdt_high=0xffffffff\0" \
  192 + "initrd_high=0xffffffff\0" \
  193 + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
  194 + "fdt_addr=0x83000000\0" \
  195 + "boot_fdt=try\0" \
  196 + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
  197 + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
  198 + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
  199 + "mmcautodetect=yes\0" \
  200 + "mmcargs=setenv bootargs console=${console},${baudrate} " \
  201 + CONFIG_BOOTARGS_CMA_SIZE \
  202 + "root=${mmcroot}\0" \
  203 + "loadbootscript=" \
  204 + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
  205 + "bootscript=echo Running bootscript from mmc ...; " \
  206 + "source\0" \
  207 + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
  208 + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
  209 + "mmcboot=echo Booting from mmc ...; " \
  210 + "run mmcargs; " \
  211 + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  212 + "if run loadfdt; then " \
  213 + "bootz ${loadaddr} - ${fdt_addr}; " \
  214 + "else " \
  215 + "if test ${boot_fdt} = try; then " \
  216 + "bootz; " \
  217 + "else " \
  218 + "echo WARN: Cannot load the DT; " \
  219 + "fi; " \
  220 + "fi; " \
  221 + "else " \
  222 + "bootz; " \
  223 + "fi;\0"
  224 +
  225 +#define CONFIG_BOOTCOMMAND \
  226 + "mmc dev ${mmcdev};" \
  227 + "mmc dev ${mmcdev}; if mmc rescan; then " \
  228 + "if run loadbootscript; then " \
  229 + "run bootscript; " \
  230 + "else " \
  231 + "if run loadimage; then " \
  232 + "run mmcboot; " \
  233 + "else run netboot; " \
  234 + "fi; " \
  235 + "fi; " \
  236 + "else run netboot; fi"
  237 +#endif
  238 +
  239 +/* Miscellaneous configurable options */
  240 +#define CONFIG_SYS_LONGHELP
  241 +#define CONFIG_SYS_HUSH_PARSER
  242 +#define CONFIG_SYS_PROMPT "=> "
  243 +#define CONFIG_AUTO_COMPLETE
  244 +#define CONFIG_SYS_CBSIZE 1024
  245 +
  246 +/* Print Buffer Size */
  247 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  248 +#define CONFIG_SYS_MAXARGS 256
  249 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  250 +
  251 +#define CONFIG_CMD_MEMTEST
  252 +#define CONFIG_SYS_MEMTEST_START 0x80000000
  253 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
  254 +
  255 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  256 +#define CONFIG_SYS_HZ 1000
  257 +
  258 +#define CONFIG_CMDLINE_EDITING
  259 +#define CONFIG_STACKSIZE SZ_128K
  260 +
  261 +/* Physical Memory Map */
  262 +#define CONFIG_NR_DRAM_BANKS 1
  263 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
  264 +
  265 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
  266 +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
  267 +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
  268 +
  269 +#define CONFIG_SYS_INIT_SP_OFFSET \
  270 + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  271 +#define CONFIG_SYS_INIT_SP_ADDR \
  272 + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  273 +
  274 +/* FLASH and environment organization */
  275 +#define CONFIG_SYS_NO_FLASH
  276 +
  277 +#define CONFIG_ENV_SIZE SZ_8K
  278 +
  279 +#ifdef CONFIG_SYS_BOOT_QSPI
  280 +#define CONFIG_FSL_QSPI
  281 +#define CONFIG_ENV_IS_IN_SPI_FLASH
  282 +#elif defined CONFIG_SYS_BOOT_NAND
  283 +#define CONFIG_SYS_USE_NAND
  284 +#define CONFIG_ENV_IS_IN_NAND
  285 +#else
  286 +#define CONFIG_FSL_QSPI
  287 +#define CONFIG_ENV_IS_IN_MMC
  288 +#endif
  289 +
  290 +#ifdef CONFIG_SYS_USE_NAND
  291 +#define CONFIG_CMD_NAND
  292 +#define CONFIG_CMD_NAND_TRIMFFS
  293 +
  294 +/* NAND stuff */
  295 +#define CONFIG_NAND_MXS
  296 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
  297 +#define CONFIG_SYS_NAND_BASE 0x40000000
  298 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
  299 +#define CONFIG_SYS_NAND_ONFI_DETECTION
  300 +
  301 +/* DMA stuff, needed for GPMI/MXS NAND support */
  302 +#define CONFIG_APBH_DMA
  303 +#define CONFIG_APBH_DMA_BURST
  304 +#define CONFIG_APBH_DMA_BURST8
  305 +#endif
  306 +
  307 +#ifdef CONFIG_FSL_QSPI
  308 +#define CONFIG_QSPI_BASE QSPI1_BASE_ADDR
  309 +#define CONFIG_QSPI_MEMMAP_BASE QSPI1_ARB_BASE_ADDR
  310 +
  311 +#define CONFIG_CMD_SF
  312 +#define CONFIG_SPI_FLASH
  313 +#define CONFIG_SPI_FLASH_STMICRO
  314 +#define CONFIG_SPI_FLASH_BAR
  315 +#define CONFIG_SF_DEFAULT_BUS 0
  316 +#define CONFIG_SF_DEFAULT_CS 0
  317 +#define CONFIG_SF_DEFAULT_SPEED 40000000
  318 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
  319 +#endif
  320 +
  321 +#if defined(CONFIG_ENV_IS_IN_MMC)
  322 +#define CONFIG_ENV_OFFSET (8 * SZ_64K)
  323 +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
  324 +#define CONFIG_ENV_OFFSET (384 * 1024)
  325 +#define CONFIG_ENV_SECT_SIZE (64 * 1024)
  326 +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
  327 +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
  328 +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
  329 +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
  330 +#elif defined(CONFIG_ENV_IS_IN_NAND)
  331 +#undef CONFIG_ENV_SIZE
  332 +#define CONFIG_ENV_OFFSET (37 << 20)
  333 +#define CONFIG_ENV_SECT_SIZE (128 << 10)
  334 +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
  335 +#endif
  336 +
  337 +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
  338 +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
  339 +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
  340 +
  341 +#define CONFIG_OF_LIBFDT
  342 +#define CONFIG_CMD_BOOTZ
  343 +
  344 +#define CONFIG_CMD_BMODE
  345 +
  346 +#ifndef CONFIG_SYS_DCACHE_OFF
  347 +#define CONFIG_CMD_CACHE
  348 +#endif
  349 +
  350 +#ifdef CONFIG_VIDEO
  351 +#define CONFIG_CFB_CONSOLE
  352 +#define CONFIG_VIDEO_MXS
  353 +#define CONFIG_VIDEO_LOGO
  354 +#define CONFIG_VIDEO_SW_CURSOR
  355 +#define CONFIG_VGA_AS_SINGLE_DEVICE
  356 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV
  357 +#define CONFIG_SPLASH_SCREEN
  358 +#define CONFIG_SPLASH_SCREEN_ALIGN
  359 +#define CONFIG_CMD_BMP
  360 +#define CONFIG_BMP_16BPP
  361 +#define CONFIG_VIDEO_BMP_RLE8
  362 +#define CONFIG_VIDEO_BMP_LOGO
  363 +#endif
  364 +
  365 +/* USB Configs */
  366 +#define CONFIG_CMD_USB
  367 +#ifdef CONFIG_CMD_USB
  368 +#define CONFIG_USB_EHCI
  369 +#define CONFIG_USB_EHCI_MX6
  370 +#define CONFIG_USB_STORAGE
  371 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  372 +#define CONFIG_USB_HOST_ETHER
  373 +#define CONFIG_USB_ETHER_ASIX
  374 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
  375 +#define CONFIG_MXC_USB_FLAGS 0
  376 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  377 +#endif
  378 +
  379 +#if defined(CONFIG_ANDROID_SUPPORT)
  380 +#include "mx6ul_14x14_evk_android.h"
  381 +#endif
  382 +
  383 +#endif