net: gmac_rockchip: Add support for the RK3228 GMAC

The GMAC in the RK3228 once again is identical to the incarnation in the RK3288 and the RK3399, except for where some of the configuration and control registers are located in the GRF. This adds the RK3368-specific logic necessary to reuse this driver. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

net: gmac_rockchip: Add support for the RK3228 GMAC
The GMAC in the RK3228 once again is identical to the incarnation in the RK3288 and the RK3399, except for where some of the configuration and control registers are located in the GRF. This adds the RK3368-specific logic necessary to reuse this driver. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu · Philipp Tomsich
1 parent 5bb616c6e2
Showing 1 changed file with 85 additions and 0 deletions Side-by-side Diff
drivers/net/gmac_rockchip.c
@@ -15,6 +15,7 @@
 #include <asm/arch/periph.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/grf_rk322x.h>
 #include <asm/arch/grf_rk3288.h>
 #include <asm/arch/grf_rk3328.h>
 #include <asm/arch/grf_rk3368.h>
@@ -69,6 +70,39 @@
 	return designware_eth_ofdata_to_platdata(dev);
 }
  
+static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+{
+	struct rk322x_grf *grf;
+	int clk;
+	enum {
+		RK3228_GMAC_CLK_SEL_SHIFT = 8,
+		RK3228_GMAC_CLK_SEL_MASK  = GENMASK(9, 8),
+		RK3228_GMAC_CLK_SEL_125M  = 0 << 8,
+		RK3228_GMAC_CLK_SEL_25M   = 3 << 8,
+		RK3228_GMAC_CLK_SEL_2_5M  = 2 << 8,
+	};
+
+	switch (priv->phydev->speed) {
+	case 10:
+		clk = RK3228_GMAC_CLK_SEL_2_5M;
+		break;
+	case 100:
+		clk = RK3228_GMAC_CLK_SEL_25M;
+		break;
+	case 1000:
+		clk = RK3228_GMAC_CLK_SEL_125M;
+		break;
+	default:
+		debug("Unknown phy speed: %d\n", priv->phydev->speed);
+		return -EINVAL;
+	}
+
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	rk_clrsetreg(&grf->mac_con[1], RK3228_GMAC_CLK_SEL_MASK, clk);
+
+	return 0;
+}
+
 static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 {
 	struct rk3288_grf *grf;
@@ -221,6 +255,50 @@
 	return 0;
 }
  
+static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+	struct rk322x_grf *grf;
+	enum {
+		RK3228_RMII_MODE_SHIFT = 10,
+		RK3228_RMII_MODE_MASK  = BIT(10),
+
+		RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4,
+		RK3228_GMAC_PHY_INTF_SEL_MASK  = GENMASK(6, 4),
+		RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
+
+		RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
+		RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+		RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
+
+		RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
+		RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+		RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
+	};
+	enum {
+		RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
+		RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
+
+		RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
+		RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
+	};
+
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	rk_clrsetreg(&grf->mac_con[1],
+		     RK3228_RMII_MODE_MASK |
+		     RK3228_GMAC_PHY_INTF_SEL_MASK |
+		     RK3228_RXCLK_DLY_ENA_GMAC_MASK |
+		     RK3228_TXCLK_DLY_ENA_GMAC_MASK,
+		     RK3228_GMAC_PHY_INTF_SEL_RGMII |
+		     RK3228_RXCLK_DLY_ENA_GMAC_ENABLE |
+		     RK3228_TXCLK_DLY_ENA_GMAC_ENABLE);
+
+	rk_clrsetreg(&grf->mac_con[0],
+		     RK3228_CLK_RX_DL_CFG_GMAC_MASK |
+		     RK3228_CLK_TX_DL_CFG_GMAC_MASK,
+		     pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT |
+		     pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT);
+}
+
 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 {
 	struct rk3288_grf *grf;
@@ -448,6 +526,11 @@
 	.write_hwaddr		= designware_eth_write_hwaddr,
 };
  
+const struct rk_gmac_ops rk3228_gmac_ops = {
+	.fix_mac_speed = rk3228_gmac_fix_mac_speed,
+	.set_to_rgmii = rk3228_gmac_set_to_rgmii,
+};
+
 const struct rk_gmac_ops rk3288_gmac_ops = {
 	.fix_mac_speed = rk3288_gmac_fix_mac_speed,
 	.set_to_rgmii = rk3288_gmac_set_to_rgmii,
@@ -474,6 +557,8 @@
 };
  
 static const struct udevice_id rockchip_gmac_ids[] = {
+	{ .compatible = "rockchip,rk3228-gmac",
+	  .data = (ulong)&rk3228_gmac_ops },
 	{ .compatible = "rockchip,rk3288-gmac",
 	  .data = (ulong)&rk3288_gmac_ops },
 	{ .compatible = "rockchip,rk3328-gmac",
...	...	@@ -15,6 +15,7 @@
15	15	#include <asm/arch/periph.h>
16	16	#include <asm/arch/clock.h>
17	17	#include <asm/arch/hardware.h>
	18	+#include <asm/arch/grf_rk322x.h>
18	19	#include <asm/arch/grf_rk3288.h>
19	20	#include <asm/arch/grf_rk3328.h>
20	21	#include <asm/arch/grf_rk3368.h>
...	...	@@ -69,6 +70,39 @@
69	70	return designware_eth_ofdata_to_platdata(dev);
70	71	}
71	72
	73	+static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
	74	+{
	75	+ struct rk322x_grf *grf;
	76	+ int clk;
	77	+ enum {
	78	+ RK3228_GMAC_CLK_SEL_SHIFT = 8,
	79	+ RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8),
	80	+ RK3228_GMAC_CLK_SEL_125M = 0 << 8,
	81	+ RK3228_GMAC_CLK_SEL_25M = 3 << 8,
	82	+ RK3228_GMAC_CLK_SEL_2_5M = 2 << 8,
	83	+ };
	84	+
	85	+ switch (priv->phydev->speed) {
	86	+ case 10:
	87	+ clk = RK3228_GMAC_CLK_SEL_2_5M;
	88	+ break;
	89	+ case 100:
	90	+ clk = RK3228_GMAC_CLK_SEL_25M;
	91	+ break;
	92	+ case 1000:
	93	+ clk = RK3228_GMAC_CLK_SEL_125M;
	94	+ break;
	95	+ default:
	96	+ debug("Unknown phy speed: %d\n", priv->phydev->speed);
	97	+ return -EINVAL;
	98	+ }
	99	+
	100	+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	101	+ rk_clrsetreg(&grf->mac_con[1], RK3228_GMAC_CLK_SEL_MASK, clk);
	102	+
	103	+ return 0;
	104	+}
	105	+
72	106	static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
73	107	{
74	108	struct rk3288_grf *grf;
...	...	@@ -221,6 +255,50 @@
221	255	return 0;
222	256	}
223	257
	258	+static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
	259	+{
	260	+ struct rk322x_grf *grf;
	261	+ enum {
	262	+ RK3228_RMII_MODE_SHIFT = 10,
	263	+ RK3228_RMII_MODE_MASK = BIT(10),
	264	+
	265	+ RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4,
	266	+ RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
	267	+ RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
	268	+
	269	+ RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
	270	+ RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
	271	+ RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
	272	+
	273	+ RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
	274	+ RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
	275	+ RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
	276	+ };
	277	+ enum {
	278	+ RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
	279	+ RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
	280	+
	281	+ RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
	282	+ RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
	283	+ };
	284	+
	285	+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	286	+ rk_clrsetreg(&grf->mac_con[1],
	287	+ RK3228_RMII_MODE_MASK \|
	288	+ RK3228_GMAC_PHY_INTF_SEL_MASK \|
	289	+ RK3228_RXCLK_DLY_ENA_GMAC_MASK \|
	290	+ RK3228_TXCLK_DLY_ENA_GMAC_MASK,
	291	+ RK3228_GMAC_PHY_INTF_SEL_RGMII \|
	292	+ RK3228_RXCLK_DLY_ENA_GMAC_ENABLE \|
	293	+ RK3228_TXCLK_DLY_ENA_GMAC_ENABLE);
	294	+
	295	+ rk_clrsetreg(&grf->mac_con[0],
	296	+ RK3228_CLK_RX_DL_CFG_GMAC_MASK \|
	297	+ RK3228_CLK_TX_DL_CFG_GMAC_MASK,
	298	+ pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT \|
	299	+ pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT);
	300	+}
	301	+
224	302	static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
225	303	{
226	304	struct rk3288_grf *grf;
...	...	@@ -448,6 +526,11 @@
448	526	.write_hwaddr = designware_eth_write_hwaddr,
449	527	};
450	528
	529	+const struct rk_gmac_ops rk3228_gmac_ops = {
	530	+ .fix_mac_speed = rk3228_gmac_fix_mac_speed,
	531	+ .set_to_rgmii = rk3228_gmac_set_to_rgmii,
	532	+};
	533	+
451	534	const struct rk_gmac_ops rk3288_gmac_ops = {
452	535	.fix_mac_speed = rk3288_gmac_fix_mac_speed,
453	536	.set_to_rgmii = rk3288_gmac_set_to_rgmii,
...	...	@@ -474,6 +557,8 @@
474	557	};
475	558
476	559	static const struct udevice_id rockchip_gmac_ids[] = {
	560	+ { .compatible = "rockchip,rk3228-gmac",
	561	+ .data = (ulong)&rk3228_gmac_ops },
477	562	{ .compatible = "rockchip,rk3288-gmac",
478	563	.data = (ulong)&rk3288_gmac_ops },
479	564	{ .compatible = "rockchip,rk3328-gmac",