Merge remote-tracking branch 'u-boot-imx/master'

Albert ARIBAUD
2 parents 651eb73224 1d9b033269
Showing 51 changed files Side-by-side Diff
Makefile
arch/arm/cpu/arm1136/mx31/generic.c
arch/arm/cpu/arm1136/mx31/timer.c
arch/arm/cpu/arm1136/mx35/generic.c
arch/arm/cpu/arm1136/mx35/timer.c
arch/arm/cpu/arm926ejs/mx25/generic.c
arch/arm/cpu/arm926ejs/mx25/timer.c
arch/arm/cpu/arm926ejs/mxs/spl_boot.c
arch/arm/cpu/armv7/imx-common/Makefile
arch/arm/cpu/armv7/imx-common/cmd_bmode.c
arch/arm/cpu/armv7/imx-common/cpu.c
arch/arm/cpu/armv7/imx-common/i2c.c
arch/arm/cpu/armv7/imx-common/iomux-v3.c
arch/arm/cpu/armv7/imx-common/speed.c
arch/arm/cpu/armv7/imx-common/timer.c
arch/arm/imx-common/Makefile
arch/arm/imx-common/cmd_bmode.c
arch/arm/imx-common/cpu.c
arch/arm/imx-common/i2c-mxv7.c
arch/arm/imx-common/iomux-v3.c
@@ -306,12 +306,9 @@
 LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
 endif
  
-ifeq ($(SOC),mx5)
-LIBS-y += $(CPUDIR)/imx-common/libimx-common.o
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
+LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
 endif
-ifeq ($(SOC),mx6)
-LIBS-y += $(CPUDIR)/imx-common/libimx-common.o
-endif
  
 ifeq ($(SOC),s5pc1xx)
 LIBS-y += $(CPUDIR)/s5p-common/libs5p-common.o
@@ -776,6 +773,7 @@
 	       $(obj)tools/gen_eth_addr    $(obj)tools/img2srec		  \
 	       $(obj)tools/mk{env,}image   $(obj)tools/mpc86x_clk	  \
 	       $(obj)tools/mk{smdk5250,}spl				  \
+	       $(obj)tools/mxsboot					  \
 	       $(obj)tools/ncb		   $(obj)tools/ubsha1
 	@rm -f $(obj)board/cray/L1/{bootscript.c,bootscript.image}	  \
 	       $(obj)board/matrix_vision/*/bootscript.img		  \
@@ -22,6 +22,7 @@
  */
  
 #include <common.h>
+#include <div64.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
 #include <asm/io.h>
  
  
@@ -30,16 +31,17 @@
 static u32 mx31_decode_pll(u32 reg, u32 infreq)
 {
 	u32 mfi = GET_PLL_MFI(reg);
-	u32 mfn = GET_PLL_MFN(reg);
+	s32 mfn = GET_PLL_MFN(reg);
 	u32 mfd = GET_PLL_MFD(reg);
 	u32 pd =  GET_PLL_PD(reg);
  
 	mfi = mfi <= 5 ? 5 : mfi;
+	mfn = mfn >= 512 ? mfn - 1024 : mfn;
 	mfd += 1;
 	pd += 1;
  
-	return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) /
-		(mfd * pd)) << 10;
+	return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
+		mfd * pd);
 }
  
 static u32 mx31_get_mpl_dpdgck_clk(void)
  
@@ -47,9 +49,9 @@
 	u32 infreq;
  
 	if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
-		infreq = CONFIG_MX31_CLK32 * 1024;
+		infreq = MXC_CLK32 * 1024;
 	else
-		infreq = CONFIG_MX31_HCLK_FREQ;
+		infreq = MXC_HCLK;
  
 	return mx31_decode_pll(readl(CCM_MPCTL), infreq);
 }
@@ -23,6 +23,7 @@
  
 #include <common.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
 #include <div64.h>
 #include <watchdog.h>
 #include <asm/io.h>
  
  
  
@@ -53,28 +54,27 @@
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
 	tick *= CONFIG_SYS_HZ;
-	do_div(tick, CONFIG_MX31_CLK32);
+	do_div(tick, MXC_CLK32);
 	return tick;
 }
  
 static inline unsigned long long time_to_tick(unsigned long long time)
 {
-	time *= CONFIG_MX31_CLK32;
+	time *= MXC_CLK32;
 	do_div(time, CONFIG_SYS_HZ);
 	return time;
 }
  
 static inline unsigned long long us_to_tick(unsigned long long us)
 {
-	us = us * CONFIG_MX31_CLK32 + 999999;
+	us = us * MXC_CLK32 + 999999;
 	do_div(us, 1000000);
 	return us;
 }
 #else
 /* ~2% error */
-#define TICK_PER_TIME	((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) \
-							/ CONFIG_SYS_HZ)
-#define US_PER_TICK	(1000000 / CONFIG_MX31_CLK32)
+#define TICK_PER_TIME	((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
+#define US_PER_TICK	(1000000 / MXC_CLK32)
  
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
@@ -128,7 +128,7 @@
 {
 	/*
 	 * get_ticks() returns a long long (64 bit), it wraps in
-	 * 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+	 * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
 	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
 	 * 5 * 10^6 days - long enough.
 	 */
@@ -159,7 +159,7 @@
  */
 ulong get_tbclk(void)
 {
-	return CONFIG_MX31_CLK32;
+	return MXC_CLK32;
 }
  
 void reset_cpu(ulong addr)
@@ -24,6 +24,7 @@
  */
  
 #include <common.h>
+#include <div64.h>
 #include <asm/io.h>
 #include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
  
  
@@ -129,15 +130,17 @@
 static u32 decode_pll(u32 reg, u32 infreq)
 {
 	u32 mfi = (reg >> 10) & 0xf;
-	u32 mfn = reg & 0x3f;
-	u32 mfd = (reg >> 16) & 0x3f;
+	s32 mfn = reg & 0x3ff;
+	u32 mfd = (reg >> 16) & 0x3ff;
 	u32 pd = (reg >> 26) & 0xf;
  
 	mfi = mfi <= 5 ? 5 : mfi;
+	mfn = mfn >= 512 ? mfn - 1024 : mfn;
 	mfd += 1;
 	pd += 1;
  
-	return ((2 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
+	return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
+		mfd * pd);
 }
  
 static u32 get_mcu_main_clk(void)
@@ -146,9 +149,7 @@
 	struct ccm_regs *ccm =
 		(struct ccm_regs *)IMX_CCM_BASE;
 	arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd);
-	fi *=
-		decode_pll(readl(&ccm->mpctl),
-			CONFIG_MX35_HCLK_FREQ);
+	fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK);
 	return fi / (arm_div * fd);
 }
  
  
  
@@ -171,17 +172,14 @@
 	u32 pdr4 = readl(&ccm->pdr4);
 	u32 div;
 	if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
-		div = (CCM_GET_DIVIDER(pdr4,
-			MXC_CCM_PDR4_PER0_PRDF_MASK,
-			MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) *
-			(CCM_GET_DIVIDER(pdr4,
+		div = CCM_GET_DIVIDER(pdr4,
 			MXC_CCM_PDR4_PER0_PODF_MASK,
-			MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1);
+			MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1;
 	} else {
 		div = CCM_GET_DIVIDER(pdr0,
 			MXC_CCM_PDR0_PER_PODF_MASK,
 			MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
-		freq /= get_ahb_div(pdr0);
+		div *= get_ahb_div(pdr0);
 	}
 	return freq / div;
 }
  
  
  
@@ -193,25 +191,20 @@
 		(struct ccm_regs *)IMX_CCM_BASE;
 	u32 pdr4 = readl(&ccm->pdr4);
  
-	if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) {
+	if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U)
 		freq = get_mcu_main_clk();
-	} else {
-		freq = decode_pll(readl(&ccm->ppctl),
-			CONFIG_MX35_HCLK_FREQ);
-	}
-	freq /= ((CCM_GET_DIVIDER(pdr4,
-			MXC_CCM_PDR4_UART_PRDF_MASK,
-			MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) *
-		(CCM_GET_DIVIDER(pdr4,
+	else
+		freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
+	freq /= CCM_GET_DIVIDER(pdr4,
 			MXC_CCM_PDR4_UART_PODF_MASK,
-			MXC_CCM_PDR4_UART_PODF_OFFSET) + 1));
+			MXC_CCM_PDR4_UART_PODF_OFFSET) + 1;
 	return freq;
 }
  
 unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
 {
 	u32 nfc_pdf, hsp_podf;
-	u32 pll, ret_val = 0, usb_prdf, usb_podf;
+	u32 pll, ret_val = 0, usb_podf;
 	struct ccm_regs *ccm =
 		(struct ccm_regs *)IMX_CCM_BASE;
  
  
  
@@ -255,16 +248,13 @@
 		ret_val = pll / (nfc_pdf + 1);
 		break;
 	case USB_CLK:
-		usb_prdf = (reg4 >> 25) & 0x7;
-		usb_podf = (reg4 >> 22) & 0x7;
-		if (reg4 & 0x200) {
+		usb_podf = (reg4 >> 22) & 0x3F;
+		if (reg4 & 0x200)
 			pll = get_mcu_main_clk();
-		} else {
-			pll = decode_pll(readl(&ccm->ppctl),
-				CONFIG_MX35_HCLK_FREQ);
-		}
+		else
+			pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
  
-		ret_val = pll / ((usb_prdf + 1) * (usb_podf + 1));
+		ret_val = pll / (usb_podf + 1);
 		break;
 	default:
 		printf("Unknown clock: %d\n", clk);
  
  
@@ -287,18 +277,16 @@
 	case UART2_BAUD:
 	case UART3_BAUD:
 		clk_sel = mpdr3 & (1 << 14);
-		pre_pdf = (mpdr4 >> 13) & 0x7;
-		pdf = (mpdr4 >> 10) & 0x7;
+		pdf = (mpdr4 >> 10) & 0x3F;
 		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
-				((pre_pdf + 1) * (pdf + 1));
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
 		break;
 	case SSI1_BAUD:
 		pre_pdf = (mpdr2 >> 24) & 0x7;
 		pdf = mpdr2 & 0x3F;
 		clk_sel = mpdr2 & (1 << 6);
 		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
 				((pre_pdf + 1) * (pdf + 1));
 		break;
 	case SSI2_BAUD:
  
  
@@ -306,16 +294,14 @@
 		pdf = (mpdr2 >> 8) & 0x3F;
 		clk_sel = mpdr2 & (1 << 6);
 		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
 				((pre_pdf + 1) * (pdf + 1));
 		break;
 	case CSI_BAUD:
 		clk_sel = mpdr2 & (1 << 7);
-		pre_pdf = (mpdr2 >> 16) & 0x7;
-		pdf = (mpdr2 >> 19) & 0x7;
+		pdf = (mpdr2 >> 16) & 0x3F;
 		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
-				((pre_pdf + 1) * (pdf + 1));
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
 		break;
 	case MSHC_CLK:
 		pre_pdf = readl(&ccm->pdr1);
  
  
  
  
  
  
  
@@ -323,39 +309,33 @@
 		pdf = (pre_pdf >> 22) & 0x3F;
 		pre_pdf = (pre_pdf >> 28) & 0x7;
 		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
 				((pre_pdf + 1) * (pdf + 1));
 		break;
 	case ESDHC1_CLK:
 		clk_sel = mpdr3 & 0x40;
-		pre_pdf = mpdr3 & 0x7;
-		pdf = (mpdr3>>3) & 0x7;
+		pdf = mpdr3 & 0x3F;
 		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
-				((pre_pdf + 1) * (pdf + 1));
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
 		break;
 	case ESDHC2_CLK:
 		clk_sel = mpdr3 & 0x40;
-		pre_pdf = (mpdr3 >> 8) & 0x7;
-		pdf = (mpdr3 >> 11) & 0x7;
+		pdf = (mpdr3 >> 8) & 0x3F;
 		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
-				((pre_pdf + 1) * (pdf + 1));
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
 		break;
 	case ESDHC3_CLK:
 		clk_sel = mpdr3 & 0x40;
-		pre_pdf = (mpdr3 >> 16) & 0x7;
-		pdf = (mpdr3 >> 19) & 0x7;
+		pdf = (mpdr3 >> 16) & 0x3F;
 		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
-				((pre_pdf + 1) * (pdf + 1));
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
 		break;
 	case SPDIF_CLK:
 		clk_sel = mpdr3 & 0x400000;
 		pre_pdf = (mpdr3 >> 29) & 0x7;
 		pdf = (mpdr3 >> 23) & 0x3F;
 		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
 				((pre_pdf + 1) * (pdf + 1));
 		break;
 	default:
@@ -27,6 +27,7 @@
 #include <asm/io.h>
 #include <div64.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
  
 DECLARE_GLOBAL_DATA_PTR;
  
  
  
  
  
  
  
  
  
  
@@ -37,44 +38,53 @@
 /* General purpose timers bitfields */
 #define GPTCR_SWR       (1<<15)	/* Software reset */
 #define GPTCR_FRR       (1<<9)	/* Freerun / restart */
-#define GPTCR_CLKSOURCE_32   (0x100<<6)	/* Clock source */
-#define GPTCR_CLKSOURCE_IPG (0x001<<6)	/* Clock source */
+#define GPTCR_CLKSOURCE_32   (4<<6)	/* Clock source */
 #define GPTCR_TEN       (1)	/* Timer enable */
  
-#define	TIMER_FREQ_HZ	mxc_get_clock(MXC_IPG_CLK)
-
+/*
+ * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
+ * "tick" is internal timer period
+ */
+/* ~0.4% error - measured with stop-watch on 100s boot-delay */
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
 	tick *= CONFIG_SYS_HZ;
-	do_div(tick, TIMER_FREQ_HZ);
+	do_div(tick, MXC_CLK32);
  
 	return tick;
 }
  
-static inline unsigned long long us_to_tick(unsigned long long usec)
+static inline unsigned long long us_to_tick(unsigned long long us)
 {
-	usec *= TIMER_FREQ_HZ;
-	do_div(usec, 1000000);
+	us = us * MXC_CLK32 + 999999;
+	do_div(us, 1000000);
  
-	return usec;
+	return us;
 }
  
+/*
+ * nothing really to do with interrupts, just starts up a counter.
+ * The 32KHz 32-bit timer overruns in 134217 seconds
+ */
 int timer_init(void)
 {
 	int i;
 	struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
+	struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR;
  
 	/* setup GP Timer 1 */
 	writel(GPTCR_SWR, &gpt->ctrl);
-	for (i = 0; i < 100; i++)
-		writel(0, &gpt->ctrl);	/* We have no udelay by now */
  
-	writel(0, &gpt->pre);
-	/* Freerun Mode, PERCLK1 input */
-	writel(readl(&gpt->ctrl) |
-		GPTCR_CLKSOURCE_IPG | GPTCR_TEN,
-		&gpt->ctrl);
+	writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1);
  
+	for (i = 0; i < 100; i++)
+		writel(0, &gpt->ctrl); /* We have no udelay by now */
+	writel(0, &gpt->pre); /* prescaler = 1 */
+	/* Freerun Mode, 32KHz input */
+	writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
+			&gpt->ctrl);
+	writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl);
+
 	return 0;
 }
  
@@ -101,7 +111,7 @@
 {
 	/*
 	 * get_ticks() returns a long long (64 bit), it wraps in
-	 * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+	 * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
 	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
 	 * 5 * 10^6 days - long enough.
 	 */
@@ -132,6 +142,6 @@
  */
 ulong get_tbclk(void)
 {
-	return TIMER_FREQ_HZ;
+	return MXC_CLK32;
 }
@@ -64,7 +64,7 @@
 static ulong imx_get_mpllclk(void)
 {
 	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong fref = 24000000;
+	ulong fref = MXC_HCLK;
  
 	return imx_decode_pll(readl(&ccm->mpctl), fref);
 }
@@ -40,6 +40,7 @@
 #include <div64.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
  
 DECLARE_GLOBAL_DATA_PTR;
  
  
  
  
@@ -55,28 +56,27 @@
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
 	tick *= CONFIG_SYS_HZ;
-	do_div(tick, CONFIG_MX25_CLK32);
+	do_div(tick, MXC_CLK32);
 	return tick;
 }
  
 static inline unsigned long long time_to_tick(unsigned long long time)
 {
-	time *= CONFIG_MX25_CLK32;
+	time *= MXC_CLK32;
 	do_div(time, CONFIG_SYS_HZ);
 	return time;
 }
  
 static inline unsigned long long us_to_tick(unsigned long long us)
 {
-	us = us * CONFIG_MX25_CLK32 + 999999;
+	us = us * MXC_CLK32 + 999999;
 	do_div(us, 1000000);
 	return us;
 }
 #else
 /* ~2% error */
-#define TICK_PER_TIME	((CONFIG_MX25_CLK32 + CONFIG_SYS_HZ / 2) / \
-		CONFIG_SYS_HZ)
-#define US_PER_TICK	(1000000 / CONFIG_MX25_CLK32)
+#define TICK_PER_TIME	((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
+#define US_PER_TICK	(1000000 / MXC_CLK32)
  
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
@@ -144,7 +144,7 @@
 {
 	/*
 	 * get_ticks() returns a long long (64 bit), it wraps in
-	 * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+	 * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
 	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
 	 * 5 * 10^6 days - long enough.
 	 */
@@ -177,7 +177,7 @@
 {
 	ulong tbclk;
  
-	tbclk = CONFIG_MX25_CLK32;
+	tbclk = MXC_CLK32;
 	return tbclk;
 }
@@ -38,12 +38,14 @@
  * takes a few seconds to roll. The boot doesn't take that long, so to keep the
  * code simple, it doesn't take rolling into consideration.
  */
-#define	HW_DIGCTRL_MICROSECONDS	0x8001c0c0
 void early_delay(int delay)
 {
-	uint32_t st = readl(HW_DIGCTRL_MICROSECONDS);
+	struct mxs_digctl_regs *digctl_regs =
+		(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
+
+	uint32_t st = readl(&digctl_regs->hw_digctl_microseconds);
 	st += delay;
-	while (st > readl(HW_DIGCTRL_MICROSECONDS))
+	while (st > readl(&digctl_regs->hw_digctl_microseconds))
 		;
 }
  
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2011 Freescale Semiconductor, Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB     = $(obj)libimx-common.o
-
-COBJS-y	= iomux-v3.o timer.o cpu.o speed.o
-COBJS-$(CONFIG_I2C_MXC) += i2c.o
-COBJS-$(CONFIG_CMD_BMODE) += cmd_bmode.o
-COBJS	:= $(sort $(COBJS-y))
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
-/*
- * Copyright (C) 2012 Boundary Devices Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <asm/errno.h>
-#include <asm/io.h>
-#include <asm/imx-common/boot_mode.h>
-#include <malloc.h>
-
-static const struct boot_mode *modes[2];
-
-static const struct boot_mode *search_modes(char *arg)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(modes); i++) {
-		const struct boot_mode *p = modes[i];
-		if (p) {
-			while (p->name) {
-				if (!strcmp(p->name, arg))
-					return p;
-				p++;
-			}
-		}
-	}
-	return NULL;
-}
-
-static int create_usage(char *dest)
-{
-	int i;
-	int size = 0;
-
-	for (i = 0; i < ARRAY_SIZE(modes); i++) {
-		const struct boot_mode *p = modes[i];
-		if (p) {
-			while (p->name) {
-				int len = strlen(p->name);
-				if (dest) {
-					memcpy(dest, p->name, len);
-					dest += len;
-					*dest++ = '|';
-				}
-				size += len + 1;
-				p++;
-			}
-		}
-	}
-	if (dest)
-		memcpy(dest - 1, " [noreset]", 11);	/* include trailing 0 */
-	size += 10;
-	return size;
-}
-
-static int do_boot_mode(cmd_tbl_t *cmdtp, int flag, int argc,
-		char * const argv[])
-{
-	const struct boot_mode *p;
-	int reset_requested = 1;
-
-	if (argc < 2)
-		return CMD_RET_USAGE;
-	p = search_modes(argv[1]);
-	if (!p)
-		return CMD_RET_USAGE;
-	if (argc == 3) {
-		if (strcmp(argv[2], "noreset"))
-			return CMD_RET_USAGE;
-		reset_requested = 0;
-	}
-
-	boot_mode_apply(p->cfg_val);
-	if (reset_requested && p->cfg_val)
-		do_reset(NULL, 0, 0, NULL);
-	return 0;
-}
-
-U_BOOT_CMD(
-	bmode, 3, 0, do_boot_mode,
-	NULL,
-	"");
-
-void add_board_boot_modes(const struct boot_mode *p)
-{
-	int size;
-	char *dest;
-
-	if (__u_boot_cmd_bmode.usage) {
-		free(__u_boot_cmd_bmode.usage);
-		__u_boot_cmd_bmode.usage = NULL;
-	}
-
-	modes[0] = p;
-	modes[1] = soc_boot_modes;
-	size = create_usage(NULL);
-	dest = malloc(size);
-	if (dest) {
-		create_usage(dest);
-		__u_boot_cmd_bmode.usage = dest;
-	}
-}
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/errno.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/crm_regs.h>
-
-#ifdef CONFIG_FSL_ESDHC
-#include <fsl_esdhc.h>
-#endif
-
-char *get_reset_cause(void)
-{
-	u32 cause;
-	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
-
-	cause = readl(&src_regs->srsr);
-	writel(cause, &src_regs->srsr);
-
-	switch (cause) {
-	case 0x00001:
-	case 0x00011:
-		return "POR";
-	case 0x00004:
-		return "CSU";
-	case 0x00008:
-		return "IPP USER";
-	case 0x00010:
-		return "WDOG";
-	case 0x00020:
-		return "JTAG HIGH-Z";
-	case 0x00040:
-		return "JTAG SW";
-	case 0x10000:
-		return "WARM BOOT";
-	default:
-		return "unknown reset";
-	}
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-
-static const char *get_imx_type(u32 imxtype)
-{
-	switch (imxtype) {
-	case 0x63:
-		return "6Q";	/* Quad-core version of the mx6 */
-	case 0x61:
-		return "6DS";	/* Dual/Solo version of the mx6 */
-	case 0x60:
-		return "6SL";	/* Solo-Lite version of the mx6 */
-	case 0x51:
-		return "51";
-	case 0x53:
-		return "53";
-	default:
-		return "??";
-	}
-}
-
-int print_cpuinfo(void)
-{
-	u32 cpurev;
-
-	cpurev = get_cpu_rev();
-
-	printf("CPU:   Freescale i.MX%s rev%d.%d at %d MHz\n",
-		get_imx_type((cpurev & 0xFF000) >> 12),
-		(cpurev & 0x000F0) >> 4,
-		(cpurev & 0x0000F) >> 0,
-		mxc_get_clock(MXC_ARM_CLK) / 1000000);
-	printf("Reset cause: %s\n", get_reset_cause());
-	return 0;
-}
-#endif
-
-int cpu_eth_init(bd_t *bis)
-{
-	int rc = -ENODEV;
-
-#if defined(CONFIG_FEC_MXC)
-	rc = fecmxc_initialize(bis);
-#endif
-
-	return rc;
-}
-
-#ifdef CONFIG_FSL_ESDHC
-/*
- * Initializes on-chip MMC controllers.
- * to override, implement board_mmc_init()
- */
-int cpu_mmc_init(bd_t *bis)
-{
-	return fsl_esdhc_mmc_init(bis);
-}
-#endif
-
-void reset_cpu(ulong addr)
-{
-	__raw_writew(4, WDOG1_BASE_ADDR);
-}
-
-u32 get_ahb_clk(void)
-{
-	struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-	u32 reg, ahb_podf;
-
-	reg = __raw_readl(&imx_ccm->cbcdr);
-	reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
-	ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
-
-	return get_periph_clk() / (ahb_podf + 1);
-}
-/*
- * Copyright (C) 2012 Boundary Devices Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/errno.h>
-#include <asm/gpio.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <watchdog.h>
-
-static int force_idle_bus(void *priv)
-{
-	int i;
-	int sda, scl;
-	ulong elapsed, start_time;
-	struct i2c_pads_info *p = (struct i2c_pads_info *)priv;
-	int ret = 0;
-
-	gpio_direction_input(p->sda.gp);
-	gpio_direction_input(p->scl.gp);
-
-	imx_iomux_v3_setup_pad(p->sda.gpio_mode);
-	imx_iomux_v3_setup_pad(p->scl.gpio_mode);
-
-	sda = gpio_get_value(p->sda.gp);
-	scl = gpio_get_value(p->scl.gp);
-	if ((sda & scl) == 1)
-		goto exit;		/* Bus is idle already */
-
-	printf("%s: sda=%d scl=%d sda.gp=0x%x scl.gp=0x%x\n", __func__,
-		sda, scl, p->sda.gp, p->scl.gp);
-	/* Send high and low on the SCL line */
-	for (i = 0; i < 9; i++) {
-		gpio_direction_output(p->scl.gp, 0);
-		udelay(50);
-		gpio_direction_input(p->scl.gp);
-		udelay(50);
-	}
-	start_time = get_timer(0);
-	for (;;) {
-		sda = gpio_get_value(p->sda.gp);
-		scl = gpio_get_value(p->scl.gp);
-		if ((sda & scl) == 1)
-			break;
-		WATCHDOG_RESET();
-		elapsed = get_timer(start_time);
-		if (elapsed > (CONFIG_SYS_HZ / 5)) {	/* .2 seconds */
-			ret = -EBUSY;
-			printf("%s: failed to clear bus, sda=%d scl=%d\n",
-					__func__, sda, scl);
-			break;
-		}
-	}
-exit:
-	imx_iomux_v3_setup_pad(p->sda.i2c_mode);
-	imx_iomux_v3_setup_pad(p->scl.i2c_mode);
-	return ret;
-}
-
-static void * const i2c_bases[] = {
-	(void *)I2C1_BASE_ADDR,
-	(void *)I2C2_BASE_ADDR,
-#ifdef I2C3_BASE_ADDR
-	(void *)I2C3_BASE_ADDR,
-#endif
-};
-
-/* i2c_index can be from 0 - 2 */
-void setup_i2c(unsigned i2c_index, int speed, int slave_addr,
-		struct i2c_pads_info *p)
-{
-	if (i2c_index >= ARRAY_SIZE(i2c_bases))
-		return;
-	/* Enable i2c clock */
-	enable_i2c_clk(1, i2c_index);
-	/* Make sure bus is idle */
-	force_idle_bus(p);
-	bus_i2c_init(i2c_bases[i2c_index], speed, slave_addr,
-			force_idle_bus, p);
-}
-/*
- * Based on the iomux-v3.c from Linux kernel:
- * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
- * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
- *                       <armlinux@phytec.de>
- *
- * Copyright (C) 2004-2011 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/iomux-v3.h>
-
-static void *base = (void *)IOMUXC_BASE_ADDR;
-
-/*
- * configures a single pad in the iomuxer
- */
-int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
-{
-	u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
-	u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
-	u32 sel_input_ofs =
-		(pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
-	u32 sel_input =
-		(pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
-	u32 pad_ctrl_ofs =
-		(pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
-	u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
-
-	if (mux_ctrl_ofs)
-		__raw_writel(mux_mode, base + mux_ctrl_ofs);
-
-	if (sel_input_ofs)
-		__raw_writel(sel_input, base + sel_input_ofs);
-
-	if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
-		__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
-
-	return 0;
-}
-
-int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
-{
-	iomux_v3_cfg_t *p = pad_list;
-	int i;
-	int ret;
-
-	for (i = 0; i < count; i++) {
-		ret = imx_iomux_v3_setup_pad(*p);
-		if (ret)
-			return ret;
-		p++;
-	}
-	return 0;
-}
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-
-#ifdef CONFIG_FSL_ESDHC
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
-int get_clocks(void)
-{
-#ifdef CONFIG_FSL_ESDHC
-#ifdef CONFIG_FSL_USDHC
-	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-#else
-	gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK);
-#endif
-#endif
-	return 0;
-}
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <div64.h>
-#include <asm/arch/imx-regs.h>
-
-/* General purpose timers registers */
-struct mxc_gpt {
-	unsigned int control;
-	unsigned int prescaler;
-	unsigned int status;
-	unsigned int nouse[6];
-	unsigned int counter;
-};
-
-static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
-
-/* General purpose timers bitfields */
-#define GPTCR_SWR		(1 << 15)	/* Software reset */
-#define GPTCR_FRR		(1 << 9)	/* Freerun / restart */
-#define GPTCR_CLKSOURCE_32	(4 << 6)	/* Clock source */
-#define GPTCR_TEN		1		/* Timer enable */
-#define CLK_32KHZ		32768		/* 32Khz input */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define timestamp (gd->tbl)
-#define lastinc (gd->lastinc)
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	tick *= CONFIG_SYS_HZ;
-	do_div(tick, CLK_32KHZ);
-
-	return tick;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long usec)
-{
-	usec = usec * CLK_32KHZ + 999999;
-	do_div(usec, 1000000);
-
-	return usec;
-}
-
-int timer_init(void)
-{
-	int i;
-	ulong val;
-
-	/* setup GP Timer 1 */
-	__raw_writel(GPTCR_SWR, &cur_gpt->control);
-
-	/* We have no udelay by now */
-	for (i = 0; i < 100; i++)
-		__raw_writel(0, &cur_gpt->control);
-
-	__raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
-
-	/* Freerun Mode, PERCLK1 input */
-	i = __raw_readl(&cur_gpt->control);
-	__raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
-
-	val = __raw_readl(&cur_gpt->counter);
-	lastinc = val / (CLK_32KHZ / CONFIG_SYS_HZ);
-	timestamp = 0;
-
-	return 0;
-}
-
-unsigned long long get_ticks(void)
-{
-	ulong now = __raw_readl(&cur_gpt->counter); /* current tick value */
-
-	if (now >= lastinc) {
-		/*
-		 * normal mode (non roll)
-		 * move stamp forward with absolut diff ticks
-		 */
-		timestamp += (now - lastinc);
-	} else {
-		/* we have rollover of incrementer */
-		timestamp += (0xFFFFFFFF - lastinc) + now;
-	}
-	lastinc = now;
-	return timestamp;
-}
-
-ulong get_timer_masked(void)
-{
-	/*
-	 * get_ticks() returns a long long (64 bit), it wraps in
-	 * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
-	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
-	 * 5 * 10^6 days - long enough.
-	 */
-	return tick_to_time(get_ticks());
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-/* delay x useconds AND preserve advance timstamp value */
-void __udelay(unsigned long usec)
-{
-	unsigned long long tmp;
-	ulong tmo;
-
-	tmo = us_to_tick(usec);
-	tmp = get_ticks() + tmo;	/* get current timestamp */
-
-	while (get_ticks() < tmp)	/* loop till event */
-		 /*NOP*/;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return CLK_32KHZ;
-}
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB     = $(obj)libimx-common.o
+
+ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
+COBJS-y	= iomux-v3.o timer.o cpu.o speed.o
+COBJS-$(CONFIG_I2C_MXC) += i2c-mxv7.o
+endif
+COBJS-$(CONFIG_CMD_BMODE) += cmd_bmode.o
+COBJS	:= $(sort $(COBJS-y))
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+/*
+ * Copyright (C) 2012 Boundary Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/imx-common/boot_mode.h>
+#include <malloc.h>
+
+static const struct boot_mode *modes[2];
+
+static const struct boot_mode *search_modes(char *arg)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(modes); i++) {
+		const struct boot_mode *p = modes[i];
+		if (p) {
+			while (p->name) {
+				if (!strcmp(p->name, arg))
+					return p;
+				p++;
+			}
+		}
+	}
+	return NULL;
+}
+
+static int create_usage(char *dest)
+{
+	int i;
+	int size = 0;
+
+	for (i = 0; i < ARRAY_SIZE(modes); i++) {
+		const struct boot_mode *p = modes[i];
+		if (p) {
+			while (p->name) {
+				int len = strlen(p->name);
+				if (dest) {
+					memcpy(dest, p->name, len);
+					dest += len;
+					*dest++ = '|';
+				}
+				size += len + 1;
+				p++;
+			}
+		}
+	}
+	if (dest)
+		memcpy(dest - 1, " [noreset]", 11);	/* include trailing 0 */
+	size += 10;
+	return size;
+}
+
+static int do_boot_mode(cmd_tbl_t *cmdtp, int flag, int argc,
+		char * const argv[])
+{
+	const struct boot_mode *p;
+	int reset_requested = 1;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+	p = search_modes(argv[1]);
+	if (!p)
+		return CMD_RET_USAGE;
+	if (argc == 3) {
+		if (strcmp(argv[2], "noreset"))
+			return CMD_RET_USAGE;
+		reset_requested = 0;
+	}
+
+	boot_mode_apply(p->cfg_val);
+	if (reset_requested && p->cfg_val)
+		do_reset(NULL, 0, 0, NULL);
+	return 0;
+}
+
+U_BOOT_CMD(
+	bmode, 3, 0, do_boot_mode,
+	NULL,
+	"");
+
+void add_board_boot_modes(const struct boot_mode *p)
+{
+	int size;
+	char *dest;
+
+	if (__u_boot_cmd_bmode.usage) {
+		free(__u_boot_cmd_bmode.usage);
+		__u_boot_cmd_bmode.usage = NULL;
+	}
+
+	modes[0] = p;
+	modes[1] = soc_boot_modes;
+	size = create_usage(NULL);
+	dest = malloc(size);
+	if (dest) {
+		create_usage(dest);
+		__u_boot_cmd_bmode.usage = dest;
+	}
+}
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+
+#ifdef CONFIG_FSL_ESDHC
+#include <fsl_esdhc.h>
+#endif
+
+char *get_reset_cause(void)
+{
+	u32 cause;
+	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+
+	cause = readl(&src_regs->srsr);
+	writel(cause, &src_regs->srsr);
+
+	switch (cause) {
+	case 0x00001:
+	case 0x00011:
+		return "POR";
+	case 0x00004:
+		return "CSU";
+	case 0x00008:
+		return "IPP USER";
+	case 0x00010:
+		return "WDOG";
+	case 0x00020:
+		return "JTAG HIGH-Z";
+	case 0x00040:
+		return "JTAG SW";
+	case 0x10000:
+		return "WARM BOOT";
+	default:
+		return "unknown reset";
+	}
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+
+static const char *get_imx_type(u32 imxtype)
+{
+	switch (imxtype) {
+	case 0x63:
+		return "6Q";	/* Quad-core version of the mx6 */
+	case 0x61:
+		return "6DS";	/* Dual/Solo version of the mx6 */
+	case 0x60:
+		return "6SL";	/* Solo-Lite version of the mx6 */
+	case 0x51:
+		return "51";
+	case 0x53:
+		return "53";
+	default:
+		return "??";
+	}
+}
+
+int print_cpuinfo(void)
+{
+	u32 cpurev;
+
+	cpurev = get_cpu_rev();
+
+	printf("CPU:   Freescale i.MX%s rev%d.%d at %d MHz\n",
+		get_imx_type((cpurev & 0xFF000) >> 12),
+		(cpurev & 0x000F0) >> 4,
+		(cpurev & 0x0000F) >> 0,
+		mxc_get_clock(MXC_ARM_CLK) / 1000000);
+	printf("Reset cause: %s\n", get_reset_cause());
+	return 0;
+}
+#endif
+
+int cpu_eth_init(bd_t *bis)
+{
+	int rc = -ENODEV;
+
+#if defined(CONFIG_FEC_MXC)
+	rc = fecmxc_initialize(bis);
+#endif
+
+	return rc;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+	return fsl_esdhc_mmc_init(bis);
+}
+#endif
+
+void reset_cpu(ulong addr)
+{
+	__raw_writew(4, WDOG1_BASE_ADDR);
+}
+
+u32 get_ahb_clk(void)
+{
+	struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	u32 reg, ahb_podf;
+
+	reg = __raw_readl(&imx_ccm->cbcdr);
+	reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
+	ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
+
+	return get_periph_clk() / (ahb_podf + 1);
+}
+/*
+ * Copyright (C) 2012 Boundary Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <watchdog.h>
+
+static int force_idle_bus(void *priv)
+{
+	int i;
+	int sda, scl;
+	ulong elapsed, start_time;
+	struct i2c_pads_info *p = (struct i2c_pads_info *)priv;
+	int ret = 0;
+
+	gpio_direction_input(p->sda.gp);
+	gpio_direction_input(p->scl.gp);
+
+	imx_iomux_v3_setup_pad(p->sda.gpio_mode);
+	imx_iomux_v3_setup_pad(p->scl.gpio_mode);
+
+	sda = gpio_get_value(p->sda.gp);
+	scl = gpio_get_value(p->scl.gp);
+	if ((sda & scl) == 1)
+		goto exit;		/* Bus is idle already */
+
+	printf("%s: sda=%d scl=%d sda.gp=0x%x scl.gp=0x%x\n", __func__,
+		sda, scl, p->sda.gp, p->scl.gp);
+	/* Send high and low on the SCL line */
+	for (i = 0; i < 9; i++) {
+		gpio_direction_output(p->scl.gp, 0);
+		udelay(50);
+		gpio_direction_input(p->scl.gp);
+		udelay(50);
+	}
+	start_time = get_timer(0);
+	for (;;) {
+		sda = gpio_get_value(p->sda.gp);
+		scl = gpio_get_value(p->scl.gp);
+		if ((sda & scl) == 1)
+			break;
+		WATCHDOG_RESET();
+		elapsed = get_timer(start_time);
+		if (elapsed > (CONFIG_SYS_HZ / 5)) {	/* .2 seconds */
+			ret = -EBUSY;
+			printf("%s: failed to clear bus, sda=%d scl=%d\n",
+					__func__, sda, scl);
+			break;
+		}
+	}
+exit:
+	imx_iomux_v3_setup_pad(p->sda.i2c_mode);
+	imx_iomux_v3_setup_pad(p->scl.i2c_mode);
+	return ret;
+}
+
+static void * const i2c_bases[] = {
+	(void *)I2C1_BASE_ADDR,
+	(void *)I2C2_BASE_ADDR,
+#ifdef I2C3_BASE_ADDR
+	(void *)I2C3_BASE_ADDR,
+#endif
+};
+
+/* i2c_index can be from 0 - 2 */
+void setup_i2c(unsigned i2c_index, int speed, int slave_addr,
+		struct i2c_pads_info *p)
+{
+	if (i2c_index >= ARRAY_SIZE(i2c_bases))
+		return;
+	/* Enable i2c clock */
+	enable_i2c_clk(1, i2c_index);
+	/* Make sure bus is idle */
+	force_idle_bus(p);
+	bus_i2c_init(i2c_bases[i2c_index], speed, slave_addr,
+			force_idle_bus, p);
+}
+/*
+ * Based on the iomux-v3.c from Linux kernel:
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
+ *                       <armlinux@phytec.de>
+ *
+ * Copyright (C) 2004-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/iomux-v3.h>
+
+static void *base = (void *)IOMUXC_BASE_ADDR;
+
+/*
+ * configures a single pad in the iomuxer
+ */
+int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
+{
+	u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
+	u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
+	u32 sel_input_ofs =
+		(pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
+	u32 sel_input =
+		(pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
+	u32 pad_ctrl_ofs =
+		(pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
+	u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
+
+	if (mux_ctrl_ofs)
+		__raw_writel(mux_mode, base + mux_ctrl_ofs);
+
+	if (sel_input_ofs)
+		__raw_writel(sel_input, base + sel_input_ofs);
+
+	if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
+		__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
+
+	return 0;
+}
+
+int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
+{
+	iomux_v3_cfg_t *p = pad_list;
+	int i;
+	int ret;
+
+	for (i = 0; i < count; i++) {
+		ret = imx_iomux_v3_setup_pad(*p);
+		if (ret)
+			return ret;
+		p++;
+	}
+	return 0;
+}
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+
+#ifdef CONFIG_FSL_ESDHC
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+int get_clocks(void)
+{
+#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_USDHC
+	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#else
+	gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK);
+#endif
+#endif
+	return 0;
+}
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <div64.h>
+#include <asm/arch/imx-regs.h>
+
+/* General purpose timers registers */
+struct mxc_gpt {
+	unsigned int control;
+	unsigned int prescaler;
+	unsigned int status;
+	unsigned int nouse[6];
+	unsigned int counter;
+};
+
+static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
+
+/* General purpose timers bitfields */
+#define GPTCR_SWR		(1 << 15)	/* Software reset */
+#define GPTCR_FRR		(1 << 9)	/* Freerun / restart */
+#define GPTCR_CLKSOURCE_32	(4 << 6)	/* Clock source */
+#define GPTCR_TEN		1		/* Timer enable */
+#define CLK_32KHZ		32768		/* 32Khz input */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp (gd->tbl)
+#define lastinc (gd->lastinc)
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+	tick *= CONFIG_SYS_HZ;
+	do_div(tick, CLK_32KHZ);
+
+	return tick;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long usec)
+{
+	usec = usec * CLK_32KHZ + 999999;
+	do_div(usec, 1000000);
+
+	return usec;
+}
+
+int timer_init(void)
+{
+	int i;
+	ulong val;
+
+	/* setup GP Timer 1 */
+	__raw_writel(GPTCR_SWR, &cur_gpt->control);
+
+	/* We have no udelay by now */
+	for (i = 0; i < 100; i++)
+		__raw_writel(0, &cur_gpt->control);
+
+	__raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
+
+	/* Freerun Mode, PERCLK1 input */
+	i = __raw_readl(&cur_gpt->control);
+	__raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
+
+	val = __raw_readl(&cur_gpt->counter);
+	lastinc = val / (CLK_32KHZ / CONFIG_SYS_HZ);
+	timestamp = 0;
+
+	return 0;
+}
+
+unsigned long long get_ticks(void)
+{
+	ulong now = __raw_readl(&cur_gpt->counter); /* current tick value */
+
+	if (now >= lastinc) {
+		/*
+		 * normal mode (non roll)
+		 * move stamp forward with absolut diff ticks
+		 */
+		timestamp += (now - lastinc);
+	} else {
+		/* we have rollover of incrementer */
+		timestamp += (0xFFFFFFFF - lastinc) + now;
+	}
+	lastinc = now;
+	return timestamp;
+}
+
+ulong get_timer_masked(void)
+{
+	/*
+	 * get_ticks() returns a long long (64 bit), it wraps in
+	 * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
+	 * 5 * 10^6 days - long enough.
+	 */
+	return tick_to_time(get_ticks());
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+/* delay x useconds AND preserve advance timstamp value */
+void __udelay(unsigned long usec)
+{
+	unsigned long long tmp;
+	ulong tmo;
+
+	tmo = us_to_tick(usec);
+	tmp = get_ticks() + tmo;	/* get current timestamp */
+
+	while (get_ticks() < tmp)	/* loop till event */
+		 /*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return CLK_32KHZ;
+}
@@ -26,6 +26,20 @@
 #ifndef __ASM_ARCH_CLOCK_H
 #define __ASM_ARCH_CLOCK_H
  
+#include <common.h>
+
+#ifdef CONFIG_MX25_HCLK_FREQ
+#define MXC_HCLK	CONFIG_MX25_HCLK_FREQ
+#else
+#define MXC_HCLK	24000000
+#endif
+
+#ifdef CONFIG_MX25_CLK32
+#define MXC_CLK32	CONFIG_MX25_CLK32
+#else
+#define MXC_CLK32	32768
+#endif
+
 enum mxc_clock {
 	MXC_CSI_CLK,
 	MXC_EPIT_CLK,
@@ -24,6 +24,20 @@
 #ifndef __ASM_ARCH_CLOCK_H
 #define __ASM_ARCH_CLOCK_H
  
+#include <common.h>
+
+#ifdef CONFIG_MX31_HCLK_FREQ
+#define MXC_HCLK	CONFIG_MX31_HCLK_FREQ
+#else
+#define MXC_HCLK	26000000
+#endif
+
+#ifdef CONFIG_MX31_CLK32
+#define MXC_CLK32	CONFIG_MX31_CLK32
+#else
+#define MXC_CLK32	32768
+#endif
+
 enum mxc_clock {
 	MXC_ARM_CLK,
 	MXC_IPG_CLK,
@@ -24,6 +24,20 @@
 #ifndef __ASM_ARCH_CLOCK_H
 #define __ASM_ARCH_CLOCK_H
  
+#include <common.h>
+
+#ifdef CONFIG_MX35_HCLK_FREQ
+#define MXC_HCLK	CONFIG_MX35_HCLK_FREQ
+#else
+#define MXC_HCLK	24000000
+#endif
+
+#ifdef CONFIG_MX35_CLK32
+#define MXC_CLK32	CONFIG_MX35_CLK32
+#else
+#define MXC_CLK32	32768
+#endif
+
 enum mxc_clock {
 	MXC_ARM_CLK,
 	MXC_AHB_CLK,
@@ -32,8 +32,8 @@
 #define MXC_CCM_CCMR_VOL_RDY_CNT_MASK          (0xF << 20)
 #define MXC_CCM_CCMR_ROMW_OFFSET               18
 #define MXC_CCM_CCMR_ROMW_MASK                 (0x3 << 18)
-#define MXC_CCM_CCMR_RAMW_OFFSET               21
-#define MXC_CCM_CCMR_RAMW_MASK                 (0x3 << 21)
+#define MXC_CCM_CCMR_RAMW_OFFSET               16
+#define MXC_CCM_CCMR_RAMW_MASK                 (0x3 << 16)
 #define MXC_CCM_CCMR_LPM_OFFSET                 14
 #define MXC_CCM_CCMR_LPM_MASK                   (0x3 << 14)
 #define MXC_CCM_CCMR_UPE                        (1 << 9)
@@ -47,7 +47,7 @@
 #define MXC_CCM_PDR0_CON_MUX_DIV_MASK           (0xF << 16)
 #define MXC_CCM_PDR0_CKIL_SEL			(1 << 15)
 #define MXC_CCM_PDR0_PER_PODF_OFFSET            12
-#define MXC_CCM_PDR0_PER_PODF_MASK              (0xF << 12)
+#define MXC_CCM_PDR0_PER_PODF_MASK              (0x7 << 12)
 #define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET        9
 #define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK          (0x7 << 9)
 #define MXC_CCM_PDR0_AUTO_CON	                0x1
  
@@ -62,10 +62,8 @@
 #define MXC_CCM_PDR2_SSI2_PRDF_MASK             (0x7 << 27)
 #define MXC_CCM_PDR2_SSI1_PRDF_OFFSET           24
 #define MXC_CCM_PDR2_SSI1_PRDF_MASK             (0x7 << 24)
-#define MXC_CCM_PDR2_CSI_PRDF_OFFSET            19
-#define MXC_CCM_PDR2_CSI_PRDF_MASK              (0x7 << 19)
 #define MXC_CCM_PDR2_CSI_PODF_OFFSET            16
-#define MXC_CCM_PDR2_CSI_PODF_MASK              (0x7 << 16)
+#define MXC_CCM_PDR2_CSI_PODF_MASK              (0x3F << 16)
 #define MXC_CCM_PDR2_SSI2_PODF_OFFSET           8
 #define MXC_CCM_PDR2_SSI2_PODF_MASK             (0x3F << 8)
 #define MXC_CCM_PDR2_CSI_M_U			(1 << 7)
  
  
  
  
  
  
  
  
@@ -78,35 +76,23 @@
 #define MXC_CCM_PDR3_SPDIF_PODF_OFFSET          23
 #define MXC_CCM_PDR3_SPDIF_PODF_MASK            (0x3F << 23)
 #define MXC_CCM_PDR3_SPDIF_M_U			(1 << 22)
-#define MXC_CCM_PDR3_ESDHC3_PRDF_OFFSET         19
-#define MXC_CCM_PDR3_ESDHC3_PRDF_MASK           (0x7 << 19)
 #define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET         16
-#define MXC_CCM_PDR3_ESDHC3_PODF_MASK           (0x7 << 16)
-#define MXC_CCM_PDR3_UART_M_U			(1 << 15)
-#define MXC_CCM_PDR3_ESDHC2_PRDF_OFFSET         11
-#define MXC_CCM_PDR3_ESDHC2_PRDF_MASK           (0x7 << 11)
+#define MXC_CCM_PDR3_ESDHC3_PODF_MASK           (0x3F << 16)
+#define MXC_CCM_PDR3_UART_M_U			(1 << 14)
 #define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET         8
-#define MXC_CCM_PDR3_ESDHC2_PODF_MASK           (0x7 << 8)
+#define MXC_CCM_PDR3_ESDHC2_PODF_MASK           (0x3F << 8)
 #define MXC_CCM_PDR3_ESDHC_M_U			(1 << 6)
-#define MXC_CCM_PDR3_ESDHC1_PRDF_OFFSET         3
-#define MXC_CCM_PDR3_ESDHC1_PRDF_MASK           (0x7 << 3)
 #define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET         0
-#define MXC_CCM_PDR3_ESDHC1_PODF_MASK           (0x7)
+#define MXC_CCM_PDR3_ESDHC1_PODF_MASK           (0x3F)
  
 #define MXC_CCM_PDR4_NFC_PODF_OFFSET		28
 #define MXC_CCM_PDR4_NFC_PODF_MASK		(0xF << 28)
-#define MXC_CCM_PDR4_USB_PRDF_OFFSET		25
-#define MXC_CCM_PDR4_USB_PRDF_MASK		(0x7 << 25)
 #define MXC_CCM_PDR4_USB_PODF_OFFSET		22
-#define MXC_CCM_PDR4_USB_PODF_MASK		(0x7 << 22)
-#define MXC_CCM_PDR4_PER0_PRDF_OFFSET		19
-#define MXC_CCM_PDR4_PER0_PRDF_MASK		(0x7 << 19)
+#define MXC_CCM_PDR4_USB_PODF_MASK		(0x3F << 22)
 #define MXC_CCM_PDR4_PER0_PODF_OFFSET		16
-#define MXC_CCM_PDR4_PER0_PODF_MASK		(0x7 << 16)
-#define MXC_CCM_PDR4_UART_PRDF_OFFSET		13
-#define MXC_CCM_PDR4_UART_PRDF_MASK		(0x7 << 13)
+#define MXC_CCM_PDR4_PER0_PODF_MASK		(0x3F << 16)
 #define MXC_CCM_PDR4_UART_PODF_OFFSET		10
-#define MXC_CCM_PDR4_UART_PODF_MASK		(0x7 << 10)
+#define MXC_CCM_PDR4_UART_PODF_MASK		(0x3F << 10)
 #define MXC_CCM_PDR4_USB_M_U			(1 << 9)
  
 /* Bit definitions for RCSR */
@@ -144,6 +130,12 @@
 #define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK		(0xF << 0)
  
 /* Bit definitions for Clock gating Register*/
+#define MXC_CCM_CGR_CG_MASK			0x3
+#define MXC_CCM_CGR_CG_OFF			0x0
+#define MXC_CCM_CGR_CG_RUN_ON			0x1
+#define MXC_CCM_CGR_CG_RUN_WAIT_ON		0x2
+#define MXC_CCM_CGR_CG_ON			0x3
+
 #define MXC_CCM_CGR0_ASRC_OFFSET		0
 #define MXC_CCM_CGR0_ASRC_MASK			(0x3 << 0)
 #define MXC_CCM_CGR0_ATA_OFFSET			2
@@ -251,10 +243,8 @@
 #define MXC_CCM_COSR_CLKOSEL_OFFSET		0
 #define MXC_CCM_COSR_CLKOEN			(1 << 5)
 #define MXC_CCM_COSR_CLKOUTDIV_1		(1 << 6)
-#define MXC_CCM_COSR_CLKOUT_PREDIV_MASK		(0x7 << 10)
-#define MXC_CCM_COSR_CLKOUT_PREDIV_OFFSET	10
-#define MXC_CCM_COSR_CLKOUT_PRODIV_MASK		(0x7 << 13)
-#define MXC_CCM_COSR_CLKOUT_PRODIV_OFFSET	13
+#define MXC_CCM_COSR_CLKOUT_DIV_MASK		(0x3F << 10)
+#define MXC_CCM_COSR_CLKOUT_DIV_OFFSET		10
 #define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK	(0x3 << 16)
 #define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET	16
 #define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK	(0x3 << 18)
@@ -34,21 +34,21 @@
 #define IOMUXC_GPR13_SATA_PHY_2_MASK	(0x1f<<2)
 #define IOMUXC_GPR13_SATA_PHY_1_MASK	(3<<0)
  
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB	(0b000<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB	(0b001<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB	(0b010<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB	(0b011<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB	(0b100<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB	(0b101<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB	(0b110<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB	(0b111<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB	(0<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB	(1<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB	(2<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB	(3<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB	(4<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB	(5<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB	(6<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB	(7<<24)
  
-#define IOMUXC_GPR13_SATA_PHY_7_SATA1I	(0b10000<<19)
-#define IOMUXC_GPR13_SATA_PHY_7_SATA1M	(0b10000<<19)
-#define IOMUXC_GPR13_SATA_PHY_7_SATA1X	(0b11010<<19)
-#define IOMUXC_GPR13_SATA_PHY_7_SATA2I	(0b10010<<19)
-#define IOMUXC_GPR13_SATA_PHY_7_SATA2M	(0b10010<<19)
-#define IOMUXC_GPR13_SATA_PHY_7_SATA2X	(0b11010<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA1I	(0x10<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA1M	(0x10<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA1X	(0x1A<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA2I	(0x12<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA2M	(0x12<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA2X	(0x1A<<19)
  
 #define IOMUXC_GPR13_SATA_SPEED_1P5G	(0<<15)
 #define IOMUXC_GPR13_SATA_SPEED_3G	(1<<15)
  
@@ -63,55 +63,55 @@
 #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16		(4<<11)
 #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_8_16		(5<<11)
  
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB	(0b0000<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB	(0b0001<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB	(0b0010<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB	(0b0011<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB	(0b0100<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB	(0b0101<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB	(0b0110<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB	(0b0111<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB	(0b1000<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB	(0b1001<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB	(0b1010<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB	(0b1011<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB	(0b1100<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB	(0b1101<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB	(0b1110<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB	(0b1111<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB	(0<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB	(1<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB	(2<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB	(3<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB	(4<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB	(5<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB	(6<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB	(7<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB	(8<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB	(9<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB	(0xA<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB	(0xB<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB	(0xC<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB	(0xD<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB	(0xE<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB	(0xF<<7)
  
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V	(0b00000<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V	(0b00001<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V	(0b00010<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V	(0b00011<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V	(0b00100<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V	(0b00101<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V	(0b00110<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V	(0b00111<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V	(0b01000<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V	(0b01001<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V	(0b01010<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V	(0b01011<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V	(0b01100<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V	(0b01101<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V	(0b01110<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V	(0b01111<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V	(0b10000<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V	(0b10001<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V	(0b10010<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V	(0b10011<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V	(0b10100<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V	(0b10101<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V	(0b10110<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V	(0b10111<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V	(0b11000<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V	(0b11001<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V	(0b11010<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V	(0b11011<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V	(0b11100<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V	(0b11101<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V	(0b11110<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V	(0b11111<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V	(0<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V	(1<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V	(2<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V	(3<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V	(4<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V	(5<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V	(6<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V	(7<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V	(8<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V	(9<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V	(0xA<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V	(0xB<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V	(0xC<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V	(0xD<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V	(0xE<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V	(0xF<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V	(0x10<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V	(0x11<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V	(0x12<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V	(0x13<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V	(0x14<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V	(0x15<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V	(0x16<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V	(0x17<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V	(0x18<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V	(0x19<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V	(0x1A<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V	(0x1B<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V	(0x1C<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V	(0x1D<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V	(0x1E<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V	(0x1F<<2)
  
 #define IOMUXC_GPR13_SATA_PHY_1_FAST	0
 #define IOMUXC_GPR13_SATA_PHY_1_MEDIUM	1
@@ -173,7 +173,7 @@
 #define HW_DRAM_CTL29_CONFIG	(CS_MAP << 24 | COLUMN_SIZE << 16 | \
 					ADDR_PINS << 8 | APREBIT)
  
-void mx28_adjust_memory_params(uint32_t *dram_vals)
+void mxs_adjust_memory_params(uint32_t *dram_vals)
 {
 	dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG;
 }
@@ -49,8 +49,8 @@
  
 	/* SSP0 clock at 96MHz */
 	mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
-	/* SSP2 clock at 96MHz */
-	mx28_set_sspclk(MXC_SSPCLK2, 96000, 0);
+	/* SSP2 clock at 160MHz */
+	mx28_set_sspclk(MXC_SSPCLK2, 160000, 0);
  
 #ifdef	CONFIG_CMD_USB
 	mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
@@ -71,90 +71,16 @@
 Flashing U-Boot
 --------------------------------
  
-There are two options: the original bootloader in NAND can be replaced with
-u-boot, or u-boot can be stored on the NOR flash without erasing
-the delivered bootloader.
+U-boot should be stored on the NOR flash.
+
 The boot storage can be select using the switches on the personality board
 (SW1-SW2) and on the DEBUG board (SW4-SW10).
  
-The second option is to be preferred if you have not a JTAG debugger.
 If something goes wrong flashing the bootloader, it is always possible to
 recover the board booting from the other device.
  
-Replacing the bootloader on the NAND
---------------------------------------
-To replace RedBoot with U-Boot, the easy way is to do this in linux.
-Start the kernel with the suggested options. Make sure to have set the
-mtdparts exactly as described, because this matches the layout on the
-mx35pdk.
-
-You should see in your boot log the following entries for the NAND
-flash:
-
-5 cmdlinepart partitions found on MTD device mxc_nand
-Creating 5 MTD partitions on "mxc_nand":
-0x000000000000-0x000000100000 : "boot"
-0x000000100000-0x000000600000 : "linux"
-0x000000600000-0x000006600000 : "root"
-0x000006600000-0x000006e00000 : "cfg"
-0x000006e00000-0x000080000000 : "user"
-
-You can use the utilities flash_eraseall and nandwrite to put
-u-boot on the NAND. The bootloader is marked as "boot", and 1MB is
-reserved. If everything is correct, this partition is accessed as
-/dev/mtd4. However, check if it is correct with "cat /proc/mtd" and
-get the device node from the partition name:
-
-$ cat /proc/mtd | grep boot
-
-I suggest you try the utilities on a different partition to be sure
-if everything works correctly. If not, and you remove RedBoot, you have to
-reinstall it using the ATK tool as suggested by Freescale, or using a
-JTAG debugger.
-
-I report the versions of the utilities I used (they are provided with ELDK):
-
--bash-3.2# nandwrite --version
-nandwrite $Revision: 1.32 $
-
-flash_eraseall --version
-flash_eraseall $Revision: 1.22 $
-
-nandwrite reports a warning if the file to be saved is not sector aligned.
-This should have no consequences, but I preferred to pad u-boot.bin
-to get no problem at all.
-$ dd if=/dev/zero of=zeros bs=1 count=74800
-$ cat u-boot.bin zeros > u-boot-padded.bin
-
-To erase the partition:
-$ flash_eraseall /dev/mtd4
-
-Writing u-boot:
-
-$ nandwrite /dev/mtd4 u-boot-padded.bin
-
-Now U-Boot is stored on the booting partition.
-
-To boot from NAND, you have to select the switches as follows:
-
-Personality board
-	SW2	1, 4, 5 on
-		2, 3, 6, 7, 8 off
-	SW1	all off
-
-Debug Board:
-	SW5	0
-	SW6	0
-	SW7	0
-	SW8	1
-	SW9	1
-	SW10	0
-
-
 Saving U-Boot in the NOR flash
 ---------------------------------
-
-The procedure to save in the NOR flash is quite the same as to write into the NAND.
  
 Check the partition for boot in the NOR flash. Setting the mtdparts as reported,
 the boot partition should be /dev/mtd0.
@@ -32,6 +32,8 @@
 #include <i2c.h>
 #include <pmic.h>
 #include <fsl_pmic.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
 #include <mc9sdz60.h>
 #include <mc13892.h>
 #include <linux/types.h>
@@ -275,4 +277,27 @@
  
 	return rc;
 }
+
+#if defined(CONFIG_FSL_ESDHC)
+
+struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
+
+int board_mmc_init(bd_t *bis)
+{
+	/* configure pins for SDHC1 only */
+	mxc_request_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_SD1_CLK, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_SD1_DATA0, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_SD1_DATA1, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC);
+
+	return fsl_esdhc_initialize(bis, &esdhc_cfg);
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return !(mc9sdz60_reg_read(MC9SDZ60_REG_DES_FLAG) & 0x4);
+}
+#endif
@@ -197,18 +197,18 @@
  
 static void setup_iomux_enet(void)
 {
-	gpio_direction_output(87, 0);  /* GPIO 3-23 */
-	gpio_direction_output(190, 1); /* GPIO 6-30 */
-	gpio_direction_output(185, 1); /* GPIO 6-25 */
-	gpio_direction_output(187, 1); /* GPIO 6-27 */
-	gpio_direction_output(188, 1); /* GPIO 6-28*/
-	gpio_direction_output(189, 1); /* GPIO 6-29 */
+	gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
+	gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
 	imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
-	gpio_direction_output(184, 1); /* GPIO 6-24 */
+	gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
  
 	/* Need delay 10ms according to KSZ9021 spec */
 	udelay(1000 * 10);
-	gpio_set_value(87, 1);  /* GPIO 3-23 */
+	gpio_set_value(IMX_GPIO_NR(3, 23), 1);
  
 	imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
 }
  
@@ -249,11 +249,11 @@
        int ret;
  
        if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
-	       gpio_direction_input(192); /*GPIO7_0*/
-	       ret = !gpio_get_value(192);
+		gpio_direction_input(IMX_GPIO_NR(7, 0));
+		ret = !gpio_get_value(IMX_GPIO_NR(7, 0));
        } else {
-	       gpio_direction_input(38); /*GPIO2_6*/
-	       ret = !gpio_get_value(38);
+		gpio_direction_input(IMX_GPIO_NR(2, 6));
+		ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
        }
  
        return ret;
@@ -27,11 +27,7 @@
  
 LIB	= $(obj)lib$(BOARD).o
  
-COBJS	:= efikamx.o
-
-ifdef	CONFIG_CMD_USB
-COBJS	+= efikamx-usb.o
-endif
+COBJS	:= efikamx.o efikamx-usb.o
  
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
@@ -214,4 +214,16 @@
 	if (port)
 		mdelay(10);
 }
+
+/*
+ * Ethernet on the Smarttop is on the USB bus. Rather than give an error about
+ * "CPU Net Initialization Failed", just pass this test since no other settings
+ * are required. Smartbook doesn't have built-in Ethernet but we will let it
+ * pass anyway considering someone may have plugged in a USB stick and all
+ * they need to do is run "usb start".
+ */
+int board_eth_init(bd_t *bis)
+{
+	return 0;
+}
@@ -492,9 +492,6 @@
 					ARRAY_SIZE(efikamx_pata_pads));
 	setup_iomux_usb();
  
-	if (machine_is_efikasb())
-		setenv("preboot", "usb reset ; setenv stdin usbkbd\0");
-
 	return 0;
 }
  
@@ -119,6 +119,10 @@
 			(uint32_t)(priv->desc->cmd.address + cache_data_count));
 	}
  
+	/* Invalidate the area, so no writeback into the RAM races with DMA */
+	invalidate_dcache_range((uint32_t)priv->desc->cmd.address,
+			(uint32_t)(priv->desc->cmd.address + cache_data_count));
+
 	priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
 				(data_count << MXS_DMA_DESC_BYTES_OFFSET);
  
@@ -224,8 +224,10 @@
 	struct mxs_dma_desc *dp;
 	uint32_t ctrl0;
 	uint32_t cache_data_count;
+	const uint32_t dstart = (uint32_t)data;
 	int dmach;
 	int tl;
+	int ret = 0;
  
 	ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count);
  
  
  
  
@@ -239,18 +241,18 @@
 	if (!write)
 		ctrl0 |= SSP_CTRL0_READ;
  
-	writel(length, &ssp_regs->hw_ssp_xfer_size);
-
 	if (length % ARCH_DMA_MINALIGN)
 		cache_data_count = roundup(length, ARCH_DMA_MINALIGN);
 	else
 		cache_data_count = length;
  
+	/* Flush data to DRAM so DMA can pick them up */
 	if (write)
-		/* Flush data to DRAM so DMA can pick them up */
-		flush_dcache_range((uint32_t)data,
-			(uint32_t)(data + cache_data_count));
+		flush_dcache_range(dstart, dstart + cache_data_count);
  
+	/* Invalidate the area, so no writeback into the RAM races with DMA */
+	invalidate_dcache_range(dstart, dstart + cache_data_count);
+
 	dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus;
  
 	dp = desc;
  
  
  
  
  
  
@@ -281,41 +283,47 @@
 			tl = min(length, xfer_max_sz);
  
 		dp->cmd.data |=
-			(tl << MXS_DMA_DESC_BYTES_OFFSET) |
-			(1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
+			((tl & 0xffff) << MXS_DMA_DESC_BYTES_OFFSET) |
+			(4 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
 			MXS_DMA_DESC_HALT_ON_TERMINATE |
 			MXS_DMA_DESC_TERMINATE_FLUSH;
-		dp->cmd.pio_words[0] = ctrl0;
  
 		data += tl;
 		length -= tl;
  
+		if (!length) {
+			dp->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;
+
+			if (flags & SPI_XFER_END) {
+				ctrl0 &= ~SSP_CTRL0_LOCK_CS;
+				ctrl0 |= SSP_CTRL0_IGNORE_CRC;
+			}
+		}
+
+		/*
+		 * Write CTRL0, CMD0, CMD1, XFER_SIZE registers. It is
+		 * essential that the XFER_SIZE register is written on
+		 * a per-descriptor basis with the same size as is the
+		 * descriptor!
+		 */
+		dp->cmd.pio_words[0] = ctrl0;
+		dp->cmd.pio_words[1] = 0;
+		dp->cmd.pio_words[2] = 0;
+		dp->cmd.pio_words[3] = tl;
+
 		mxs_dma_desc_append(dmach, dp);
  
 		dp++;
 	}
  
-	dp->address = (dma_addr_t)dp;
-	dp->cmd.address = (dma_addr_t)0;
-	dp->cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER |
-			(1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
-			MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;
-	if (flags & SPI_XFER_END) {
-		ctrl0 &= ~SSP_CTRL0_LOCK_CS;
-		dp->cmd.pio_words[0] = ctrl0 | SSP_CTRL0_IGNORE_CRC;
-	}
-	mxs_dma_desc_append(dmach, dp);
-
 	if (mxs_dma_go(dmach))
-		return -EINVAL;
+		ret = -EINVAL;
  
 	/* The data arrived into DRAM, invalidate cache over them */
-	if (!write) {
-		invalidate_dcache_range((uint32_t)data,
-			(uint32_t)(data + cache_data_count));
-	}
+	if (!write)
+		invalidate_dcache_range(dstart, dstart + cache_data_count);
  
-	return 0;
+	return ret;
 }
  
 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
@@ -31,7 +31,6 @@
  /* High Level Configuration Options */
 #define CONFIG_ARM1136	/* This is an arm1136 CPU core */
 #define CONFIG_MX35
-#define CONFIG_MX35_HCLK_FREQ	24000000
  
 #define CONFIG_SYS_DCACHE_OFF
 #define CONFIG_SYS_CACHELINE_SIZE	32
@@ -64,7 +64,6 @@
 /* Ethernet on FEC */
 #define CONFIG_NET_MULTI
 #define CONFIG_MII
-#define CONFIG_DISCOVER_PHY
  
 #define CONFIG_FEC_MXC
 #define IMX_FEC_BASE			FEC_BASE_ADDR
@@ -72,7 +71,7 @@
 #define CONFIG_PHY_ADDR			CONFIG_FEC_MXC_PHYADDR
 #define CONFIG_RESET_PHY_R
 #define CONFIG_FEC_MXC_NO_ANEG
-#define CONFIG_PRIME	"FEC0"
+#define CONFIG_ETHPRIME			"FEC0"
  
 /* SPI */
 #define CONFIG_HARD_SPI
@@ -33,7 +33,6 @@
  /* High Level Configuration Options */
 #define CONFIG_ARM1136		1    /* This is an arm1136 CPU core */
 #define CONFIG_MX31		1    /* in a mx31 */
-#define CONFIG_MX31_HCLK_FREQ	26000000
 #define CONFIG_MX31_CLK32	32000
  
 #define CONFIG_DISPLAY_CPUINFO
@@ -33,7 +33,6 @@
 /* High Level Configuration Options */
 #define CONFIG_ARM1136			/* This is an arm1136 CPU core */
 #define CONFIG_MX31			/* in a mx31 */
-#define CONFIG_MX31_HCLK_FREQ	26000000
 #define CONFIG_MX31_CLK32	32000
  
 #define CONFIG_DISPLAY_CPUINFO
@@ -171,9 +171,9 @@
 #define	CONFIG_LZO
 #define	CONFIG_MTD_DEVICE
 #define	CONFIG_MTD_PARTITIONS
-#define	MTDIDS_DEFAULT			"nand0=gpmi-nand.0"
+#define	MTDIDS_DEFAULT			"nand0=gpmi-nand"
 #define	MTDPARTS_DEFAULT			\
-	"mtdparts=gpmi-nand.0:"			\
+	"mtdparts=gpmi-nand:"			\
 		"3m(bootloader)ro,"		\
 		"512k(environment),"		\
 		"512k(redundant-environment),"	\
@@ -17,7 +17,6 @@
  
 /* High Level Configuration Options */
  
-#define CONFIG_MX25_CLK32		32768	/* OSC32K frequency */
 #define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_TEXT_BASE		0x81200000
  
@@ -184,6 +184,9 @@
 #define	CONFIG_EHCI_MXS_PORT 1
 #define	CONFIG_EHCI_IS_TDI
 #define	CONFIG_USB_STORAGE
+#define	CONFIG_USB_HOST_ETHER
+#define	CONFIG_USB_ETHER_ASIX
+#define	CONFIG_USB_ETHER_SMSC95XX
 #endif
  
 /* I2C */
@@ -199,6 +202,7 @@
 #ifdef CONFIG_CMD_SPI
 #define CONFIG_HARD_SPI
 #define CONFIG_MXS_SPI
+#define CONFIG_MXS_SPI_DMA_ENABLE
 #define CONFIG_SPI_HALF_DUPLEX
 #define CONFIG_DEFAULT_SPI_BUS		2
 #define CONFIG_DEFAULT_SPI_MODE		SPI_MODE_0
@@ -235,7 +239,6 @@
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE	"uImage"
-#define CONFIG_BOOTCOMMAND	"run bootcmd_net"
 #define CONFIG_LOADADDR	0x42000000
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
 #define CONFIG_OF_LIBFDT
  
@@ -244,14 +247,81 @@
  * Extra Environments
  */
 #define CONFIG_EXTRA_ENV_SETTINGS \
-	"console_fsl=console=ttyAM0" \
-	"console_mainline=console=ttyAMA0" \
-	"netargs=setenv bootargs console=${console_mainline}" \
+	"update_nand_full_filename=u-boot.nand\0" \
+	"update_nand_firmware_filename=u-boot.sb\0"	\
+	"update_sd_firmware_filename=u-boot.sd\0" \
+	"update_nand_firmware_maxsz=0x100000\0"	\
+	"update_nand_stride=0x40\0"	/* MX28 datasheet ch. 12.12 */ \
+	"update_nand_count=0x4\0"	/* MX28 datasheet ch. 12.12 */ \
+	"update_nand_get_fcb_size="	/* Get size of FCB blocks */ \
+		"nand device 0 ; " \
+		"nand info ; " \
+		"setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \
+		"setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \
+	"update_nand_full="		    /* Update FCB, DBBT and FW */ \
+		"if tftp ${update_nand_full_filename} ; then " \
+		"run update_nand_get_fcb_size ; " \
+		"nand scrub -y 0x0 ${filesize} ; " \
+		"nand write.raw ${loadaddr} 0x0 ${update_nand_fcb} ; " \
+		"setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \
+		"setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \
+		"nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \
+		"fi\0" \
+	"update_nand_firmware="		/* Update only firmware */ \
+		"if tftp ${update_nand_firmware_filename} ; then " \
+		"run update_nand_get_fcb_size ; " \
+		"setexpr fcb_sz ${update_nand_fcb} * 2 ; " /* FCB + DBBT */ \
+		"setexpr fw_sz ${update_nand_firmware_maxsz} * 2 ; " \
+		"setexpr fw_off ${fcb_sz} + ${update_nand_firmware_maxsz};" \
+		"nand erase ${fcb_sz} ${fw_sz} ; " \
+		"nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \
+		"nand write ${loadaddr} ${fw_off} ${filesize} ; " \
+		"fi\0" \
+	"update_sd_firmware="		/* Update the SD firmware partition */ \
+		"if mmc rescan ; then "	\
+		"if tftp ${update_sd_firmware_filename} ; then " \
+		"setexpr fw_sz ${filesize} / 0x200 ; "	/* SD block size */ \
+		"setexpr fw_sz ${fw_sz} + 1 ; "	\
+		"mmc write ${loadaddr} 0x800 ${fw_sz} ; " \
+		"fi ; "	\
+		"fi\0" \
+	"script=boot.scr\0"	\
+	"uimage=uImage\0" \
+	"console_fsl=ttyAM0\0" \
+	"console_mainline=ttyAMA0\0" \
+	"mmcdev=0\0" \
+	"mmcpart=2\0" \
+	"mmcroot=/dev/mmcblk0p3 rw\0" \
+	"mmcrootfstype=ext3 rootwait\0"	\
+	"mmcargs=setenv bootargs console=${console_mainline},${baudrate} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0"	\
+	"loadbootscript="  \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; "	\
+		"source\0" \
+	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; "	\
+		"bootm\0" \
+	"netargs=setenv bootargs console=${console_mainline},${baudrate} " \
 		"root=/dev/nfs " \
-		"ip=dhcp nfsroot=${serverip}:${nfsroot}\0" \
-	"bootcmd_net=echo Booting from net ...; " \
-		"run netargs; " \
-		"dhcp ${uimage}; bootm\0" \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; "	\
+		"dhcp ${uimage}; bootm\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmc rescan ${mmcdev}; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run netboot; " \
+			"fi; " \
+		"fi; " \
+	"else run netboot; fi"
  
 #endif /* __MX28EVK_CONFIG_H__ */
@@ -27,8 +27,6 @@
  /* High Level Configuration Options */
 #define CONFIG_ARM1136		1		/* This is an arm1136 CPU core */
 #define CONFIG_MX31		1		/* in a mx31 */
-#define CONFIG_MX31_HCLK_FREQ	26000000	/* RedBoot says 26MHz */
-#define CONFIG_MX31_CLK32	32768
  
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
@@ -35,8 +35,6 @@
 /* High Level Configuration Options */
 #define CONFIG_ARM1136			/* This is an arm1136 CPU core */
 #define CONFIG_MX31			/* in a mx31 */
-#define CONFIG_MX31_HCLK_FREQ	26000000
-#define CONFIG_MX31_CLK32	32768
  
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
@@ -31,7 +31,6 @@
  /* High Level Configuration Options */
 #define CONFIG_ARM1136	/* This is an arm1136 CPU core */
 #define CONFIG_MX35
-#define CONFIG_MX35_HCLK_FREQ	24000000
  
 #define CONFIG_DISPLAY_CPUINFO
  
@@ -111,6 +110,12 @@
 #define CONFIG_NET_RETRY_COUNT	100
 #define CONFIG_CMD_DATE
  
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+
 #define CONFIG_BOOTDELAY	3
  
 #define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */
@@ -238,6 +243,13 @@
 #define CONFIG_MXC_NAND_HWECC
 #define CONFIG_SYS_NAND_LARGEPAGE
  
+/* mmc driver */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	1
+
 /*
  * Default environment and default scripts
  * to update uboot and load kernel
@@ -279,8 +291,8 @@
 	"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0"			\
 	"load=tftp ${loadaddr} ${u-boot}\0"				\
 	"uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0"		\
-	"update=protect off ${uboot_addr} +40000;"			\
-		"erase ${uboot_addr} +40000;"				\
+	"update=protect off ${uboot_addr} +80000;"			\
+		"erase ${uboot_addr} +80000;"				\
 		"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0"		\
 	"upd=if run load;then echo Updating u-boot;if run update;"	\
 		"then echo U-Boot updated;"				\
@@ -28,8 +28,6 @@
 #define CONFIG_ARM1136			/* This is an arm1136 CPU core */
 #define CONFIG_MX31			/* in a mx31 */
 #define CONFIG_QONG
-#define CONFIG_MX31_HCLK_FREQ	26000000	/* 26MHz */
-#define CONFIG_MX31_CLK32	32768
  
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
@@ -39,8 +39,6 @@
 #include <asm/arch/regs-base.h>
  
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_ARCH_MISC_INIT
@@ -31,8 +31,6 @@
 /* High Level Configuration Options */
 #define CONFIG_ARM1136
 #define CONFIG_MX31
-#define CONFIG_MX31_HCLK_FREQ	26000000
-#define CONFIG_MX31_CLK32	32768
  
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
@@ -28,7 +28,6 @@
  
 #define CONFIG_ARM926EJS			/* arm926ejs CPU core */
 #define CONFIG_MX25
-#define CONFIG_MX25_CLK32		32768	/* OSC32K frequency */
 #define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_TEXT_BASE		0xA0000000
...	...	@@ -306,12 +306,9 @@
306	306	LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
307	307	endif
308	308
309		-ifeq ($(SOC),mx5)
310		-LIBS-y += $(CPUDIR)/imx-common/libimx-common.o
	309	+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
	310	+LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
311	311	endif
312		-ifeq ($(SOC),mx6)
313		-LIBS-y += $(CPUDIR)/imx-common/libimx-common.o
314		-endif
315	312
316	313	ifeq ($(SOC),s5pc1xx)
317	314	LIBS-y += $(CPUDIR)/s5p-common/libs5p-common.o
...	...	@@ -776,6 +773,7 @@
776	773	$(obj)tools/gen_eth_addr $(obj)tools/img2srec \
777	774	$(obj)tools/mk{env,}image $(obj)tools/mpc86x_clk \
778	775	$(obj)tools/mk{smdk5250,}spl \
	776	+ $(obj)tools/mxsboot \
779	777	$(obj)tools/ncb $(obj)tools/ubsha1
780	778	@rm -f $(obj)board/cray/L1/{bootscript.c,bootscript.image} \
781	779	$(obj)board/matrix_vision/*/bootscript.img \
...	...	@@ -22,6 +22,7 @@
22	22	*/
23	23
24	24	#include <common.h>
	25	+#include <div64.h>
25	26	#include <asm/arch/imx-regs.h>
26	27	#include <asm/arch/clock.h>
27	28	#include <asm/io.h>
28	29
29	30
...	...	@@ -30,16 +31,17 @@
30	31	static u32 mx31_decode_pll(u32 reg, u32 infreq)
31	32	{
32	33	u32 mfi = GET_PLL_MFI(reg);
33		- u32 mfn = GET_PLL_MFN(reg);
	34	+ s32 mfn = GET_PLL_MFN(reg);
34	35	u32 mfd = GET_PLL_MFD(reg);
35	36	u32 pd = GET_PLL_PD(reg);
36	37
37	38	mfi = mfi <= 5 ? 5 : mfi;
	39	+ mfn = mfn >= 512 ? mfn - 1024 : mfn;
38	40	mfd += 1;
39	41	pd += 1;
40	42
41		- return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) /
42		- (mfd * pd)) << 10;
	43	+ return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
	44	+ mfd * pd);
43	45	}
44	46
45	47	static u32 mx31_get_mpl_dpdgck_clk(void)
46	48
...	...	@@ -47,9 +49,9 @@
47	49	u32 infreq;
48	50
49	51	if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
50		- infreq = CONFIG_MX31_CLK32 * 1024;
	52	+ infreq = MXC_CLK32 * 1024;
51	53	else
52		- infreq = CONFIG_MX31_HCLK_FREQ;
	54	+ infreq = MXC_HCLK;
53	55
54	56	return mx31_decode_pll(readl(CCM_MPCTL), infreq);
55	57	}
...	...	@@ -23,6 +23,7 @@
23	23
24	24	#include <common.h>
25	25	#include <asm/arch/imx-regs.h>
	26	+#include <asm/arch/clock.h>
26	27	#include <div64.h>
27	28	#include <watchdog.h>
28	29	#include <asm/io.h>
29	30
30	31
31	32
...	...	@@ -53,28 +54,27 @@
53	54	static inline unsigned long long tick_to_time(unsigned long long tick)
54	55	{
55	56	tick *= CONFIG_SYS_HZ;
56		- do_div(tick, CONFIG_MX31_CLK32);
	57	+ do_div(tick, MXC_CLK32);
57	58	return tick;
58	59	}
59	60
60	61	static inline unsigned long long time_to_tick(unsigned long long time)
61	62	{
62		- time *= CONFIG_MX31_CLK32;
	63	+ time *= MXC_CLK32;
63	64	do_div(time, CONFIG_SYS_HZ);
64	65	return time;
65	66	}
66	67
67	68	static inline unsigned long long us_to_tick(unsigned long long us)
68	69	{
69		- us = us * CONFIG_MX31_CLK32 + 999999;
	70	+ us = us * MXC_CLK32 + 999999;
70	71	do_div(us, 1000000);
71	72	return us;
72	73	}
73	74	#else
74	75	/* ~2% error */
75		-#define TICK_PER_TIME ((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) \
76		- / CONFIG_SYS_HZ)
77		-#define US_PER_TICK (1000000 / CONFIG_MX31_CLK32)
	76	+#define TICK_PER_TIME ((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
	77	+#define US_PER_TICK (1000000 / MXC_CLK32)
78	78
79	79	static inline unsigned long long tick_to_time(unsigned long long tick)
80	80	{
...	...	@@ -128,7 +128,7 @@
128	128	{
129	129	/*
130	130	* get_ticks() returns a long long (64 bit), it wraps in
131		- * 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
	131	+ * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
132	132	* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
133	133	* 5 * 10^6 days - long enough.
134	134	*/
...	...	@@ -159,7 +159,7 @@
159	159	*/
160	160	ulong get_tbclk(void)
161	161	{
162		- return CONFIG_MX31_CLK32;
	162	+ return MXC_CLK32;
163	163	}
164	164
165	165	void reset_cpu(ulong addr)
...	...	@@ -24,6 +24,7 @@
24	24	*/
25	25
26	26	#include <common.h>
	27	+#include <div64.h>
27	28	#include <asm/io.h>
28	29	#include <asm/errno.h>
29	30	#include <asm/arch/imx-regs.h>
30	31
31	32
...	...	@@ -129,15 +130,17 @@
129	130	static u32 decode_pll(u32 reg, u32 infreq)
130	131	{
131	132	u32 mfi = (reg >> 10) & 0xf;
132		- u32 mfn = reg & 0x3f;
133		- u32 mfd = (reg >> 16) & 0x3f;
	133	+ s32 mfn = reg & 0x3ff;
	134	+ u32 mfd = (reg >> 16) & 0x3ff;
134	135	u32 pd = (reg >> 26) & 0xf;
135	136
136	137	mfi = mfi <= 5 ? 5 : mfi;
	138	+ mfn = mfn >= 512 ? mfn - 1024 : mfn;
137	139	mfd += 1;
138	140	pd += 1;
139	141
140		- return ((2 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
	142	+ return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
	143	+ mfd * pd);
141	144	}
142	145
143	146	static u32 get_mcu_main_clk(void)
...	...	@@ -146,9 +149,7 @@
146	149	struct ccm_regs *ccm =
147	150	(struct ccm_regs *)IMX_CCM_BASE;
148	151	arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd);
149		- fi *=
150		- decode_pll(readl(&ccm->mpctl),
151		- CONFIG_MX35_HCLK_FREQ);
	152	+ fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK);
152	153	return fi / (arm_div * fd);
153	154	}
154	155
155	156
156	157
...	...	@@ -171,17 +172,14 @@
171	172	u32 pdr4 = readl(&ccm->pdr4);
172	173	u32 div;
173	174	if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
174		- div = (CCM_GET_DIVIDER(pdr4,
175		- MXC_CCM_PDR4_PER0_PRDF_MASK,
176		- MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) *
177		- (CCM_GET_DIVIDER(pdr4,
	175	+ div = CCM_GET_DIVIDER(pdr4,
178	176	MXC_CCM_PDR4_PER0_PODF_MASK,
179		- MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1);
	177	+ MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1;
180	178	} else {
181	179	div = CCM_GET_DIVIDER(pdr0,
182	180	MXC_CCM_PDR0_PER_PODF_MASK,
183	181	MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
184		- freq /= get_ahb_div(pdr0);
	182	+ div *= get_ahb_div(pdr0);
185	183	}
186	184	return freq / div;
187	185	}
188	186
189	187
190	188
...	...	@@ -193,25 +191,20 @@
193	191	(struct ccm_regs *)IMX_CCM_BASE;
194	192	u32 pdr4 = readl(&ccm->pdr4);
195	193
196		- if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) {
	194	+ if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U)
197	195	freq = get_mcu_main_clk();
198		- } else {
199		- freq = decode_pll(readl(&ccm->ppctl),
200		- CONFIG_MX35_HCLK_FREQ);
201		- }
202		- freq /= ((CCM_GET_DIVIDER(pdr4,
203		- MXC_CCM_PDR4_UART_PRDF_MASK,
204		- MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) *
205		- (CCM_GET_DIVIDER(pdr4,
	196	+ else
	197	+ freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
	198	+ freq /= CCM_GET_DIVIDER(pdr4,
206	199	MXC_CCM_PDR4_UART_PODF_MASK,
207		- MXC_CCM_PDR4_UART_PODF_OFFSET) + 1));
	200	+ MXC_CCM_PDR4_UART_PODF_OFFSET) + 1;
208	201	return freq;
209	202	}
210	203
211	204	unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
212	205	{
213	206	u32 nfc_pdf, hsp_podf;
214		- u32 pll, ret_val = 0, usb_prdf, usb_podf;
	207	+ u32 pll, ret_val = 0, usb_podf;
215	208	struct ccm_regs *ccm =
216	209	(struct ccm_regs *)IMX_CCM_BASE;
217	210
218	211
219	212
...	...	@@ -255,16 +248,13 @@
255	248	ret_val = pll / (nfc_pdf + 1);
256	249	break;
257	250	case USB_CLK:
258		- usb_prdf = (reg4 >> 25) & 0x7;
259		- usb_podf = (reg4 >> 22) & 0x7;
260		- if (reg4 & 0x200) {
	251	+ usb_podf = (reg4 >> 22) & 0x3F;
	252	+ if (reg4 & 0x200)
261	253	pll = get_mcu_main_clk();
262		- } else {
263		- pll = decode_pll(readl(&ccm->ppctl),
264		- CONFIG_MX35_HCLK_FREQ);
265		- }
	254	+ else
	255	+ pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
266	256
267		- ret_val = pll / ((usb_prdf + 1) * (usb_podf + 1));
	257	+ ret_val = pll / (usb_podf + 1);
268	258	break;
269	259	default:
270	260	printf("Unknown clock: %d\n", clk);
271	261
272	262
...	...	@@ -287,18 +277,16 @@
287	277	case UART2_BAUD:
288	278	case UART3_BAUD:
289	279	clk_sel = mpdr3 & (1 << 14);
290		- pre_pdf = (mpdr4 >> 13) & 0x7;
291		- pdf = (mpdr4 >> 10) & 0x7;
	280	+ pdf = (mpdr4 >> 10) & 0x3F;
292	281	ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
293		- decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
294		- ((pre_pdf + 1) * (pdf + 1));
	282	+ decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
295	283	break;
296	284	case SSI1_BAUD:
297	285	pre_pdf = (mpdr2 >> 24) & 0x7;
298	286	pdf = mpdr2 & 0x3F;
299	287	clk_sel = mpdr2 & (1 << 6);
300	288	ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
301		- decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
	289	+ decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
302	290	((pre_pdf + 1) * (pdf + 1));
303	291	break;
304	292	case SSI2_BAUD:
305	293
306	294
...	...	@@ -306,16 +294,14 @@
306	294	pdf = (mpdr2 >> 8) & 0x3F;
307	295	clk_sel = mpdr2 & (1 << 6);
308	296	ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
309		- decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
	297	+ decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
310	298	((pre_pdf + 1) * (pdf + 1));
311	299	break;
312	300	case CSI_BAUD:
313	301	clk_sel = mpdr2 & (1 << 7);
314		- pre_pdf = (mpdr2 >> 16) & 0x7;
315		- pdf = (mpdr2 >> 19) & 0x7;
	302	+ pdf = (mpdr2 >> 16) & 0x3F;
316	303	ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
317		- decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
318		- ((pre_pdf + 1) * (pdf + 1));
	304	+ decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
319	305	break;
320	306	case MSHC_CLK:
321	307	pre_pdf = readl(&ccm->pdr1);
322	308
323	309
324	310
325	311
326	312
327	313
328	314
...	...	@@ -323,39 +309,33 @@
323	309	pdf = (pre_pdf >> 22) & 0x3F;
324	310	pre_pdf = (pre_pdf >> 28) & 0x7;
325	311	ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
326		- decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
	312	+ decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
327	313	((pre_pdf + 1) * (pdf + 1));
328	314	break;
329	315	case ESDHC1_CLK:
330	316	clk_sel = mpdr3 & 0x40;
331		- pre_pdf = mpdr3 & 0x7;
332		- pdf = (mpdr3>>3) & 0x7;
	317	+ pdf = mpdr3 & 0x3F;
333	318	ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
334		- decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
335		- ((pre_pdf + 1) * (pdf + 1));
	319	+ decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
336	320	break;
337	321	case ESDHC2_CLK:
338	322	clk_sel = mpdr3 & 0x40;
339		- pre_pdf = (mpdr3 >> 8) & 0x7;
340		- pdf = (mpdr3 >> 11) & 0x7;
	323	+ pdf = (mpdr3 >> 8) & 0x3F;
341	324	ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
342		- decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
343		- ((pre_pdf + 1) * (pdf + 1));
	325	+ decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
344	326	break;
345	327	case ESDHC3_CLK:
346	328	clk_sel = mpdr3 & 0x40;
347		- pre_pdf = (mpdr3 >> 16) & 0x7;
348		- pdf = (mpdr3 >> 19) & 0x7;
	329	+ pdf = (mpdr3 >> 16) & 0x3F;
349	330	ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
350		- decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
351		- ((pre_pdf + 1) * (pdf + 1));
	331	+ decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
352	332	break;
353	333	case SPDIF_CLK:
354	334	clk_sel = mpdr3 & 0x400000;
355	335	pre_pdf = (mpdr3 >> 29) & 0x7;
356	336	pdf = (mpdr3 >> 23) & 0x3F;
357	337	ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
358		- decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
	338	+ decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
359	339	((pre_pdf + 1) * (pdf + 1));
360	340	break;
361	341	default:
...	...	@@ -27,6 +27,7 @@
27	27	#include <asm/io.h>
28	28	#include <div64.h>
29	29	#include <asm/arch/imx-regs.h>
	30	+#include <asm/arch/crm_regs.h>
30	31	#include <asm/arch/clock.h>
31	32
32	33	DECLARE_GLOBAL_DATA_PTR;
33	34
34	35
35	36
36	37
37	38
38	39
39	40
40	41
41	42
42	43
...	...	@@ -37,44 +38,53 @@
37	38	/* General purpose timers bitfields */
38	39	#define GPTCR_SWR (1<<15) /* Software reset */
39	40	#define GPTCR_FRR (1<<9) /* Freerun / restart */
40		-#define GPTCR_CLKSOURCE_32 (0x100<<6) /* Clock source */
41		-#define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */
	41	+#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
42	42	#define GPTCR_TEN (1) /* Timer enable */
43	43
44		-#define TIMER_FREQ_HZ mxc_get_clock(MXC_IPG_CLK)
45		-
	44	+/*
	45	+ * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
	46	+ * "tick" is internal timer period
	47	+ */
	48	+/* ~0.4% error - measured with stop-watch on 100s boot-delay */
46	49	static inline unsigned long long tick_to_time(unsigned long long tick)
47	50	{
48	51	tick *= CONFIG_SYS_HZ;
49		- do_div(tick, TIMER_FREQ_HZ);
	52	+ do_div(tick, MXC_CLK32);
50	53
51	54	return tick;
52	55	}
53	56
54		-static inline unsigned long long us_to_tick(unsigned long long usec)
	57	+static inline unsigned long long us_to_tick(unsigned long long us)
55	58	{
56		- usec *= TIMER_FREQ_HZ;
57		- do_div(usec, 1000000);
	59	+ us = us * MXC_CLK32 + 999999;
	60	+ do_div(us, 1000000);
58	61
59		- return usec;
	62	+ return us;
60	63	}
61	64
	65	+/*
	66	+ * nothing really to do with interrupts, just starts up a counter.
	67	+ * The 32KHz 32-bit timer overruns in 134217 seconds
	68	+ */
62	69	int timer_init(void)
63	70	{
64	71	int i;
65	72	struct gpt_regs gpt = (struct gpt_regs )GPT1_BASE_ADDR;
	73	+ struct ccm_regs ccm = (struct ccm_regs )CCM_BASE_ADDR;
66	74
67	75	/* setup GP Timer 1 */
68	76	writel(GPTCR_SWR, &gpt->ctrl);
69		- for (i = 0; i < 100; i++)
70		- writel(0, &gpt->ctrl); /* We have no udelay by now */
71	77
72		- writel(0, &gpt->pre);
73		- /* Freerun Mode, PERCLK1 input */
74		- writel(readl(&gpt->ctrl) \|
75		- GPTCR_CLKSOURCE_IPG \| GPTCR_TEN,
76		- &gpt->ctrl);
	78	+ writel(readl(&ccm->cgr1) \| 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1);
77	79
	80	+ for (i = 0; i < 100; i++)
	81	+ writel(0, &gpt->ctrl); /* We have no udelay by now */
	82	+ writel(0, &gpt->pre); /* prescaler = 1 */
	83	+ /* Freerun Mode, 32KHz input */
	84	+ writel(readl(&gpt->ctrl) \| GPTCR_CLKSOURCE_32 \| GPTCR_FRR,
	85	+ &gpt->ctrl);
	86	+ writel(readl(&gpt->ctrl) \| GPTCR_TEN, &gpt->ctrl);
	87	+
78	88	return 0;
79	89	}
80	90
...	...	@@ -101,7 +111,7 @@
101	111	{
102	112	/*
103	113	* get_ticks() returns a long long (64 bit), it wraps in
104		- * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
	114	+ * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
105	115	* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
106	116	* 5 * 10^6 days - long enough.
107	117	*/
...	...	@@ -132,6 +142,6 @@
132	142	*/
133	143	ulong get_tbclk(void)
134	144	{
135		- return TIMER_FREQ_HZ;
	145	+ return MXC_CLK32;
136	146	}
...	...	@@ -64,7 +64,7 @@
64	64	static ulong imx_get_mpllclk(void)
65	65	{
66	66	struct ccm_regs ccm = (struct ccm_regs )IMX_CCM_BASE;
67		- ulong fref = 24000000;
	67	+ ulong fref = MXC_HCLK;
68	68
69	69	return imx_decode_pll(readl(&ccm->mpctl), fref);
70	70	}
...	...	@@ -40,6 +40,7 @@
40	40	#include <div64.h>
41	41	#include <asm/io.h>
42	42	#include <asm/arch/imx-regs.h>
	43	+#include <asm/arch/clock.h>
43	44
44	45	DECLARE_GLOBAL_DATA_PTR;
45	46
46	47
47	48
48	49
...	...	@@ -55,28 +56,27 @@
55	56	static inline unsigned long long tick_to_time(unsigned long long tick)
56	57	{
57	58	tick *= CONFIG_SYS_HZ;
58		- do_div(tick, CONFIG_MX25_CLK32);
	59	+ do_div(tick, MXC_CLK32);
59	60	return tick;
60	61	}
61	62
62	63	static inline unsigned long long time_to_tick(unsigned long long time)
63	64	{
64		- time *= CONFIG_MX25_CLK32;
	65	+ time *= MXC_CLK32;
65	66	do_div(time, CONFIG_SYS_HZ);
66	67	return time;
67	68	}
68	69
69	70	static inline unsigned long long us_to_tick(unsigned long long us)
70	71	{
71		- us = us * CONFIG_MX25_CLK32 + 999999;
	72	+ us = us * MXC_CLK32 + 999999;
72	73	do_div(us, 1000000);
73	74	return us;
74	75	}
75	76	#else
76	77	/* ~2% error */
77		-#define TICK_PER_TIME ((CONFIG_MX25_CLK32 + CONFIG_SYS_HZ / 2) / \
78		- CONFIG_SYS_HZ)
79		-#define US_PER_TICK (1000000 / CONFIG_MX25_CLK32)
	78	+#define TICK_PER_TIME ((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
	79	+#define US_PER_TICK (1000000 / MXC_CLK32)
80	80
81	81	static inline unsigned long long tick_to_time(unsigned long long tick)
82	82	{
...	...	@@ -144,7 +144,7 @@
144	144	{
145	145	/*
146	146	* get_ticks() returns a long long (64 bit), it wraps in
147		- * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
	147	+ * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
148	148	* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
149	149	* 5 * 10^6 days - long enough.
150	150	*/
...	...	@@ -177,7 +177,7 @@
177	177	{
178	178	ulong tbclk;
179	179
180		- tbclk = CONFIG_MX25_CLK32;
	180	+ tbclk = MXC_CLK32;
181	181	return tbclk;
182	182	}
...	...	@@ -38,12 +38,14 @@
38	38	* takes a few seconds to roll. The boot doesn't take that long, so to keep the
39	39	* code simple, it doesn't take rolling into consideration.
40	40	*/
41		-#define HW_DIGCTRL_MICROSECONDS 0x8001c0c0
42	41	void early_delay(int delay)
43	42	{
44		- uint32_t st = readl(HW_DIGCTRL_MICROSECONDS);
	43	+ struct mxs_digctl_regs *digctl_regs =
	44	+ (struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
	45	+
	46	+ uint32_t st = readl(&digctl_regs->hw_digctl_microseconds);
45	47	st += delay;
46		- while (st > readl(HW_DIGCTRL_MICROSECONDS))
	48	+ while (st > readl(&digctl_regs->hw_digctl_microseconds))
47	49	;
48	50	}
49	51
1		-#
2		-# (C) Copyright 2000-2006
3		-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4		-#
5		-# (C) Copyright 2011 Freescale Semiconductor, Inc.
6		-#
7		-# See file CREDITS for list of people who contributed to this
8		-# project.
9		-#
10		-# This program is free software; you can redistribute it and/or
11		-# modify it under the terms of the GNU General Public License as
12		-# published by the Free Software Foundation; either version 2 of
13		-# the License, or (at your option) any later version.
14		-#
15		-# This program is distributed in the hope that it will be useful,
16		-# but WITHOUT ANY WARRANTY; without even the implied warranty of
17		-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18		-# GNU General Public License for more details.
19		-#
20		-# You should have received a copy of the GNU General Public License
21		-# along with this program; if not, write to the Free Software
22		-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23		-# MA 02111-1307 USA
24		-#
25		-
26		-include $(TOPDIR)/config.mk
27		-
28		-LIB = $(obj)libimx-common.o
29		-
30		-COBJS-y = iomux-v3.o timer.o cpu.o speed.o
31		-COBJS-$(CONFIG_I2C_MXC) += i2c.o
32		-COBJS-$(CONFIG_CMD_BMODE) += cmd_bmode.o
33		-COBJS := $(sort $(COBJS-y))
34		-
35		-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
36		-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
37		-
38		-all: $(obj).depend $(LIB)
39		-
40		-$(LIB): $(OBJS)
41		- $(call cmd_link_o_target, $(OBJS))
42		-
43		-#########################################################################
44		-
45		-# defines $(obj).depend target
46		-include $(SRCTREE)/rules.mk
47		-
48		-sinclude $(obj).depend
49		-
50		-#########################################################################
1		-/*
2		- * Copyright (C) 2012 Boundary Devices Inc.
3		- *
4		- * See file CREDITS for list of people who contributed to this
5		- * project.
6		- *
7		- * This program is free software; you can redistribute it and/or
8		- * modify it under the terms of the GNU General Public License as
9		- * published by the Free Software Foundation; either version 2 of
10		- * the License, or (at your option) any later version.
11		- *
12		- * This program is distributed in the hope that it will be useful,
13		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
14		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15		- * GNU General Public License for more details.
16		- *
17		- * You should have received a copy of the GNU General Public License
18		- * along with this program; if not, write to the Free Software
19		- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20		- * MA 02111-1307 USA
21		- */
22		-#include <common.h>
23		-#include <asm/errno.h>
24		-#include <asm/io.h>
25		-#include <asm/imx-common/boot_mode.h>
26		-#include <malloc.h>
27		-
28		-static const struct boot_mode *modes[2];
29		-
30		-static const struct boot_mode search_modes(char arg)
31		-{
32		- int i;
33		-
34		- for (i = 0; i < ARRAY_SIZE(modes); i++) {
35		- const struct boot_mode *p = modes[i];
36		- if (p) {
37		- while (p->name) {
38		- if (!strcmp(p->name, arg))
39		- return p;
40		- p++;
41		- }
42		- }
43		- }
44		- return NULL;
45		-}
46		-
47		-static int create_usage(char *dest)
48		-{
49		- int i;
50		- int size = 0;
51		-
52		- for (i = 0; i < ARRAY_SIZE(modes); i++) {
53		- const struct boot_mode *p = modes[i];
54		- if (p) {
55		- while (p->name) {
56		- int len = strlen(p->name);
57		- if (dest) {
58		- memcpy(dest, p->name, len);
59		- dest += len;
60		- *dest++ = '\|';
61		- }
62		- size += len + 1;
63		- p++;
64		- }
65		- }
66		- }
67		- if (dest)
68		- memcpy(dest - 1, " [noreset]", 11); /* include trailing 0 */
69		- size += 10;
70		- return size;
71		-}
72		-
73		-static int do_boot_mode(cmd_tbl_t *cmdtp, int flag, int argc,
74		- char * const argv[])
75		-{
76		- const struct boot_mode *p;
77		- int reset_requested = 1;
78		-
79		- if (argc < 2)
80		- return CMD_RET_USAGE;
81		- p = search_modes(argv[1]);
82		- if (!p)
83		- return CMD_RET_USAGE;
84		- if (argc == 3) {
85		- if (strcmp(argv[2], "noreset"))
86		- return CMD_RET_USAGE;
87		- reset_requested = 0;
88		- }
89		-
90		- boot_mode_apply(p->cfg_val);
91		- if (reset_requested && p->cfg_val)
92		- do_reset(NULL, 0, 0, NULL);
93		- return 0;
94		-}
95		-
96		-U_BOOT_CMD(
97		- bmode, 3, 0, do_boot_mode,
98		- NULL,
99		- "");
100		-
101		-void add_board_boot_modes(const struct boot_mode *p)
102		-{
103		- int size;
104		- char *dest;
105		-
106		- if (__u_boot_cmd_bmode.usage) {
107		- free(__u_boot_cmd_bmode.usage);
108		- __u_boot_cmd_bmode.usage = NULL;
109		- }
110		-
111		- modes[0] = p;
112		- modes[1] = soc_boot_modes;
113		- size = create_usage(NULL);
114		- dest = malloc(size);
115		- if (dest) {
116		- create_usage(dest);
117		- __u_boot_cmd_bmode.usage = dest;
118		- }
119		-}