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Commit d228710f518af3fc90c1d6c28b012c932c69fa41

Authored by Macpaul Lin
Committed by Albert ARIBAUD
1 parent caddb8e41e
Exists in master and in 57 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf-6.6.52-2.2.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ftpmu010.h: add asm support used by lowlevel_init 

Add asm support which is ususally used in lowlevel_init to set
power related parameters to sdram controller and static memory controller.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>

Showing 1 changed file with 62 additions and 0 deletions Inline Diff

include/faraday/ftpmu010.h
Diff comments   View file @ d228710
1 /* 1 /*
2 * (C) Copyright 2009 Faraday Technology 2 * (C) Copyright 2009 Faraday Technology
3 * Po-Yu Chuang <ratbert@faraday-tech.com> 3 * Po-Yu Chuang <ratbert@faraday-tech.com>
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify 5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by 6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or 7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version. 8 * (at your option) any later version.
9 * 9 *
10 * This program is distributed in the hope that it will be useful, 10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 * 14 *
15 * You should have received a copy of the GNU General Public License 15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software 16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */ 18 */
19 19
20 /* 20 /*
21 * Power Management Unit 21 * Power Management Unit
22 */ 22 */
23 #ifndef __FTPMU010_H 23 #ifndef __FTPMU010_H
24 #define __FTPMU010_H 24 #define __FTPMU010_H
25 25
26 #ifndef __ASSEMBLY__
26 struct ftpmu010 { 27 struct ftpmu010 {
27 unsigned int IDNMBR0; /* 0x00 */ 28 unsigned int IDNMBR0; /* 0x00 */
28 unsigned int reserved0; /* 0x04 */ 29 unsigned int reserved0; /* 0x04 */
29 unsigned int OSCC; /* 0x08 */ 30 unsigned int OSCC; /* 0x08 */
30 unsigned int PMODE; /* 0x0C */ 31 unsigned int PMODE; /* 0x0C */
31 unsigned int PMCR; /* 0x10 */ 32 unsigned int PMCR; /* 0x10 */
32 unsigned int PED; /* 0x14 */ 33 unsigned int PED; /* 0x14 */
33 unsigned int PEDSR; /* 0x18 */ 34 unsigned int PEDSR; /* 0x18 */
34 unsigned int reserved1; /* 0x1C */ 35 unsigned int reserved1; /* 0x1C */
35 unsigned int PMSR; /* 0x20 */ 36 unsigned int PMSR; /* 0x20 */
36 unsigned int PGSR; /* 0x24 */ 37 unsigned int PGSR; /* 0x24 */
37 unsigned int MFPSR; /* 0x28 */ 38 unsigned int MFPSR; /* 0x28 */
38 unsigned int MISC; /* 0x2C */ 39 unsigned int MISC; /* 0x2C */
39 unsigned int PDLLCR0; /* 0x30 */ 40 unsigned int PDLLCR0; /* 0x30 */
40 unsigned int PDLLCR1; /* 0x34 */ 41 unsigned int PDLLCR1; /* 0x34 */
41 unsigned int AHBMCLKOFF; /* 0x38 */ 42 unsigned int AHBMCLKOFF; /* 0x38 */
42 unsigned int APBMCLKOFF; /* 0x3C */ 43 unsigned int APBMCLKOFF; /* 0x3C */
43 unsigned int DCSRCR0; /* 0x40 */ 44 unsigned int DCSRCR0; /* 0x40 */
44 unsigned int DCSRCR1; /* 0x44 */ 45 unsigned int DCSRCR1; /* 0x44 */
45 unsigned int DCSRCR2; /* 0x48 */ 46 unsigned int DCSRCR2; /* 0x48 */
46 unsigned int SDRAMHTC; /* 0x4C */ 47 unsigned int SDRAMHTC; /* 0x4C */
47 unsigned int PSPR0; /* 0x50 */ 48 unsigned int PSPR0; /* 0x50 */
48 unsigned int PSPR1; /* 0x54 */ 49 unsigned int PSPR1; /* 0x54 */
49 unsigned int PSPR2; /* 0x58 */ 50 unsigned int PSPR2; /* 0x58 */
50 unsigned int PSPR3; /* 0x5C */ 51 unsigned int PSPR3; /* 0x5C */
51 unsigned int PSPR4; /* 0x60 */ 52 unsigned int PSPR4; /* 0x60 */
52 unsigned int PSPR5; /* 0x64 */ 53 unsigned int PSPR5; /* 0x64 */
53 unsigned int PSPR6; /* 0x68 */ 54 unsigned int PSPR6; /* 0x68 */
54 unsigned int PSPR7; /* 0x6C */ 55 unsigned int PSPR7; /* 0x6C */
55 unsigned int PSPR8; /* 0x70 */ 56 unsigned int PSPR8; /* 0x70 */
56 unsigned int PSPR9; /* 0x74 */ 57 unsigned int PSPR9; /* 0x74 */
57 unsigned int PSPR10; /* 0x78 */ 58 unsigned int PSPR10; /* 0x78 */
58 unsigned int PSPR11; /* 0x7C */ 59 unsigned int PSPR11; /* 0x7C */
59 unsigned int PSPR12; /* 0x80 */ 60 unsigned int PSPR12; /* 0x80 */
60 unsigned int PSPR13; /* 0x84 */ 61 unsigned int PSPR13; /* 0x84 */
61 unsigned int PSPR14; /* 0x88 */ 62 unsigned int PSPR14; /* 0x88 */
62 unsigned int PSPR15; /* 0x8C */ 63 unsigned int PSPR15; /* 0x8C */
63 unsigned int AHBDMA_RACCS; /* 0x90 */ 64 unsigned int AHBDMA_RACCS; /* 0x90 */
64 unsigned int reserved2; /* 0x94 */ 65 unsigned int reserved2; /* 0x94 */
65 unsigned int reserved3; /* 0x98 */ 66 unsigned int reserved3; /* 0x98 */
66 unsigned int JSS; /* 0x9C */ 67 unsigned int JSS; /* 0x9C */
67 unsigned int CFC_RACC; /* 0xA0 */ 68 unsigned int CFC_RACC; /* 0xA0 */
68 unsigned int SSP1_RACC; /* 0xA4 */ 69 unsigned int SSP1_RACC; /* 0xA4 */
69 unsigned int UART1TX_RACC; /* 0xA8 */ 70 unsigned int UART1TX_RACC; /* 0xA8 */
70 unsigned int UART1RX_RACC; /* 0xAC */ 71 unsigned int UART1RX_RACC; /* 0xAC */
71 unsigned int UART2TX_RACC; /* 0xB0 */ 72 unsigned int UART2TX_RACC; /* 0xB0 */
72 unsigned int UART2RX_RACC; /* 0xB4 */ 73 unsigned int UART2RX_RACC; /* 0xB4 */
73 unsigned int SDC_RACC; /* 0xB8 */ 74 unsigned int SDC_RACC; /* 0xB8 */
74 unsigned int I2SAC97_RACC; /* 0xBC */ 75 unsigned int I2SAC97_RACC; /* 0xBC */
75 unsigned int IRDATX_RACC; /* 0xC0 */ 76 unsigned int IRDATX_RACC; /* 0xC0 */
76 unsigned int reserved4; /* 0xC4 */ 77 unsigned int reserved4; /* 0xC4 */
77 unsigned int USBD_RACC; /* 0xC8 */ 78 unsigned int USBD_RACC; /* 0xC8 */
78 unsigned int IRDARX_RACC; /* 0xCC */ 79 unsigned int IRDARX_RACC; /* 0xCC */
79 unsigned int IRDA_RACC; /* 0xD0 */ 80 unsigned int IRDA_RACC; /* 0xD0 */
80 unsigned int ED0_RACC; /* 0xD4 */ 81 unsigned int ED0_RACC; /* 0xD4 */
81 unsigned int ED1_RACC; /* 0xD8 */ 82 unsigned int ED1_RACC; /* 0xD8 */
82 }; 83 };
84 #endif /* __ASSEMBLY__ */
83 85
84 /* 86 /*
85 * ID Number 0 Register 87 * ID Number 0 Register
86 */ 88 */
87 #define FTPMU010_ID_A320A 0x03200000 89 #define FTPMU010_ID_A320A 0x03200000
88 #define FTPMU010_ID_A320C 0x03200010 90 #define FTPMU010_ID_A320C 0x03200010
89 #define FTPMU010_ID_A320D 0x03200030 91 #define FTPMU010_ID_A320D 0x03200030
90 92
91 /* 93 /*
92 * OSC Control Register 94 * OSC Control Register
93 */ 95 */
94 #define FTPMU010_OSCC_OSCH_TRI (1 << 11) 96 #define FTPMU010_OSCC_OSCH_TRI (1 << 11)
95 #define FTPMU010_OSCC_OSCH_STABLE (1 << 9) 97 #define FTPMU010_OSCC_OSCH_STABLE (1 << 9)
96 #define FTPMU010_OSCC_OSCH_OFF (1 << 8) 98 #define FTPMU010_OSCC_OSCH_OFF (1 << 8)
97 99
98 #define FTPMU010_OSCC_OSCL_TRI (1 << 3) 100 #define FTPMU010_OSCC_OSCL_TRI (1 << 3)
99 #define FTPMU010_OSCC_OSCL_RTCLSEL (1 << 2) 101 #define FTPMU010_OSCC_OSCL_RTCLSEL (1 << 2)
100 #define FTPMU010_OSCC_OSCL_STABLE (1 << 1) 102 #define FTPMU010_OSCC_OSCL_STABLE (1 << 1)
101 #define FTPMU010_OSCC_OSCL_OFF (1 << 0) 103 #define FTPMU010_OSCC_OSCL_OFF (1 << 0)
102 104
103 /* 105 /*
104 * Power Mode Register 106 * Power Mode Register
105 */ 107 */
106 #define FTPMU010_PMODE_DIVAHBCLK_MASK (0x7 << 4) 108 #define FTPMU010_PMODE_DIVAHBCLK_MASK (0x7 << 4)
107 #define FTPMU010_PMODE_DIVAHBCLK_2 (0x0 << 4) 109 #define FTPMU010_PMODE_DIVAHBCLK_2 (0x0 << 4)
108 #define FTPMU010_PMODE_DIVAHBCLK_3 (0x1 << 4) 110 #define FTPMU010_PMODE_DIVAHBCLK_3 (0x1 << 4)
109 #define FTPMU010_PMODE_DIVAHBCLK_4 (0x2 << 4) 111 #define FTPMU010_PMODE_DIVAHBCLK_4 (0x2 << 4)
110 #define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4) 112 #define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4)
111 #define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4) 113 #define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4)
112 #define FTPMU010_PMODE_DIVAHBCLK(pmode) (((pmode) >> 4) & 0x7) 114 #define FTPMU010_PMODE_DIVAHBCLK(pmode) (((pmode) >> 4) & 0x7)
113 #define FTPMU010_PMODE_FCS (1 << 2) 115 #define FTPMU010_PMODE_FCS (1 << 2)
114 #define FTPMU010_PMODE_TURBO (1 << 1) 116 #define FTPMU010_PMODE_TURBO (1 << 1)
115 #define FTPMU010_PMODE_SLEEP (1 << 0) 117 #define FTPMU010_PMODE_SLEEP (1 << 0)
116 118
117 /* 119 /*
118 * Power Manager Status Register 120 * Power Manager Status Register
119 */ 121 */
120 #define FTPMU010_PMSR_SMR (1 << 10) 122 #define FTPMU010_PMSR_SMR (1 << 10)
121 123
122 #define FTPMU010_PMSR_RDH (1 << 2) 124 #define FTPMU010_PMSR_RDH (1 << 2)
123 #define FTPMU010_PMSR_PH (1 << 1) 125 #define FTPMU010_PMSR_PH (1 << 1)
124 #define FTPMU010_PMSR_CKEHLOW (1 << 0) 126 #define FTPMU010_PMSR_CKEHLOW (1 << 0)
125 127
126 /* 128 /*
127 * Multi-Function Port Setting Register 129 * Multi-Function Port Setting Register
128 */ 130 */
129 #define FTPMU010_MFPSR_DEBUGSEL (1 << 17) 131 #define FTPMU010_MFPSR_DEBUGSEL (1 << 17)
130 #define FTPMU010_MFPSR_DMA0PINSEL (1 << 16) 132 #define FTPMU010_MFPSR_DMA0PINSEL (1 << 16)
131 #define FTPMU010_MFPSR_DMA1PINSEL (1 << 15) 133 #define FTPMU010_MFPSR_DMA1PINSEL (1 << 15)
132 #define FTPMU010_MFPSR_MODEMPINSEL (1 << 14) 134 #define FTPMU010_MFPSR_MODEMPINSEL (1 << 14)
133 #define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13) 135 #define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13)
134 #define FTPMU010_MFPSR_PWM1PINSEL (1 << 11) 136 #define FTPMU010_MFPSR_PWM1PINSEL (1 << 11)
135 #define FTPMU010_MFPSR_PWM0PINSEL (1 << 10) 137 #define FTPMU010_MFPSR_PWM0PINSEL (1 << 10)
136 #define FTPMU010_MFPSR_IRDACLKSEL (1 << 9) 138 #define FTPMU010_MFPSR_IRDACLKSEL (1 << 9)
137 #define FTPMU010_MFPSR_UARTCLKSEL (1 << 8) 139 #define FTPMU010_MFPSR_UARTCLKSEL (1 << 8)
138 #define FTPMU010_MFPSR_SSPCLKSEL (1 << 6) 140 #define FTPMU010_MFPSR_SSPCLKSEL (1 << 6)
139 #define FTPMU010_MFPSR_I2SCLKSEL (1 << 5) 141 #define FTPMU010_MFPSR_I2SCLKSEL (1 << 5)
140 #define FTPMU010_MFPSR_AC97CLKSEL (1 << 4) 142 #define FTPMU010_MFPSR_AC97CLKSEL (1 << 4)
141 #define FTPMU010_MFPSR_AC97PINSEL (1 << 3) 143 #define FTPMU010_MFPSR_AC97PINSEL (1 << 3)
142 #define FTPMU010_MFPSR_TRIAHBDIS (1 << 1) 144 #define FTPMU010_MFPSR_TRIAHBDIS (1 << 1)
143 #define FTPMU010_MFPSR_TRIAHBDBG (1 << 0) 145 #define FTPMU010_MFPSR_TRIAHBDBG (1 << 0)
144 146
145 /* 147 /*
146 * PLL/DLL Control Register 0 148 * PLL/DLL Control Register 0
147 * Note: 149 * Note:
148 * 1. FTPMU010_PDLLCR0_HCLKOUTDIS: 150 * 1. FTPMU010_PDLLCR0_HCLKOUTDIS:
149 * Datasheet indicated it starts at bit #21 which was wrong. 151 * Datasheet indicated it starts at bit #21 which was wrong.
150 * 2. FTPMU010_PDLLCR0_DLLFRAG: 152 * 2. FTPMU010_PDLLCR0_DLLFRAG:
151 * Datasheet indicated it has 2 bit which was wrong. 153 * Datasheet indicated it has 2 bit which was wrong.
152 */ 154 */
153 #define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) & 0xf) << 20) 155 #define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) & 0xf) << 20)
154 #define FTPMU010_PDLLCR0_DLLFRAG(cr0) (1 << 19) 156 #define FTPMU010_PDLLCR0_DLLFRAG(cr0) (1 << 19)
155 #define FTPMU010_PDLLCR0_DLLSTSEL (1 << 18) 157 #define FTPMU010_PDLLCR0_DLLSTSEL (1 << 18)
156 #define FTPMU010_PDLLCR0_DLLSTABLE (1 << 17) 158 #define FTPMU010_PDLLCR0_DLLSTABLE (1 << 17)
157 #define FTPMU010_PDLLCR0_DLLDIS (1 << 16) 159 #define FTPMU010_PDLLCR0_DLLDIS (1 << 16)
158 #define FTPMU010_PDLLCR0_PLL1FRANG(cr0) (((cr0) & 0x3) << 12) 160 #define FTPMU010_PDLLCR0_PLL1FRANG(cr0) (((cr0) & 0x3) << 12)
159 #define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) & 0x1ff) << 3) 161 #define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) & 0x1ff) << 3)
160 #define FTPMU010_PDLLCR0_PLL1STSEL (1 << 2) 162 #define FTPMU010_PDLLCR0_PLL1STSEL (1 << 2)
161 #define FTPMU010_PDLLCR0_PLL1STABLE (1 << 1) 163 #define FTPMU010_PDLLCR0_PLL1STABLE (1 << 1)
162 #define FTPMU010_PDLLCR0_PLL1DIS (1 << 0) 164 #define FTPMU010_PDLLCR0_PLL1DIS (1 << 0)
163 165
164 /* 166 /*
165 * SDRAM Signal Hold Time Control Register 167 * SDRAM Signal Hold Time Control Register
166 */ 168 */
167 #define FTPMU010_SDRAMHTC_RCLK_DLY(x) (((x) & 0xf) << 28) 169 #define FTPMU010_SDRAMHTC_RCLK_DLY(x) (((x) & 0xf) << 28)
168 #define FTPMU010_SDRAMHTC_CTL_WCLK_DLY(x) (((x) & 0xf) << 24) 170 #define FTPMU010_SDRAMHTC_CTL_WCLK_DLY(x) (((x) & 0xf) << 24)
169 #define FTPMU010_SDRAMHTC_DAT_WCLK_DLY(x) (((x) & 0xf) << 20) 171 #define FTPMU010_SDRAMHTC_DAT_WCLK_DLY(x) (((x) & 0xf) << 20)
170 #define FTPMU010_SDRAMHTC_EBICTRL_DCSR (1 << 18) 172 #define FTPMU010_SDRAMHTC_EBICTRL_DCSR (1 << 18)
171 #define FTPMU010_SDRAMHTC_EBIDATA_DCSR (1 << 17) 173 #define FTPMU010_SDRAMHTC_EBIDATA_DCSR (1 << 17)
172 #define FTPMU010_SDRAMHTC_SDRAMCS_DCSR (1 << 16) 174 #define FTPMU010_SDRAMHTC_SDRAMCS_DCSR (1 << 16)
173 #define FTPMU010_SDRAMHTC_SDRAMCTL_DCSR (1 << 15) 175 #define FTPMU010_SDRAMHTC_SDRAMCTL_DCSR (1 << 15)
174 #define FTPMU010_SDRAMHTC_CKE_DCSR (1 << 14) 176 #define FTPMU010_SDRAMHTC_CKE_DCSR (1 << 14)
175 #define FTPMU010_SDRAMHTC_DQM_DCSR (1 << 13) 177 #define FTPMU010_SDRAMHTC_DQM_DCSR (1 << 13)
176 #define FTPMU010_SDRAMHTC_SDCLK_DCSR (1 << 12) 178 #define FTPMU010_SDRAMHTC_SDCLK_DCSR (1 << 12)
177 179
180 #ifndef __ASSEMBLY__
178 void ftpmu010_32768osc_enable(void); 181 void ftpmu010_32768osc_enable(void);
179 void ftpmu010_dlldis_disable(void); 182 void ftpmu010_dlldis_disable(void);
180 void ftpmu010_sdram_clk_disable(unsigned int cr0); 183 void ftpmu010_sdram_clk_disable(unsigned int cr0);
184 #endif
185
186 #ifdef __ASSEMBLY__
187 #define FTPMU010_IDNMBR0 0x00
188 #define FTPMU010_reserved0 0x04
189 #define FTPMU010_OSCC 0x08
190 #define FTPMU010_PMODE 0x0C
191 #define FTPMU010_PMCR 0x10
192 #define FTPMU010_PED 0x14
193 #define FTPMU010_PEDSR 0x18
194 #define FTPMU010_reserved1 0x1C
195 #define FTPMU010_PMSR 0x20
196 #define FTPMU010_PGSR 0x24
197 #define FTPMU010_MFPSR 0x28
198 #define FTPMU010_MISC 0x2C
199 #define FTPMU010_PDLLCR0 0x30
200 #define FTPMU010_PDLLCR1 0x34
201 #define FTPMU010_AHBMCLKOFF 0x38
202 #define FTPMU010_APBMCLKOFF 0x3C
203 #define FTPMU010_DCSRCR0 0x40
204 #define FTPMU010_DCSRCR1 0x44
205 #define FTPMU010_DCSRCR2 0x48
206 #define FTPMU010_SDRAMHTC 0x4C
207 #define FTPMU010_PSPR0 0x50
208 #define FTPMU010_PSPR1 0x54
209 #define FTPMU010_PSPR2 0x58
210 #define FTPMU010_PSPR3 0x5C
211 #define FTPMU010_PSPR4 0x60
212 #define FTPMU010_PSPR5 0x64
213 #define FTPMU010_PSPR6 0x68
214 #define FTPMU010_PSPR7 0x6C
215 #define FTPMU010_PSPR8 0x70
216 #define FTPMU010_PSPR9 0x74
217 #define FTPMU010_PSPR10 0x78
218 #define FTPMU010_PSPR11 0x7C
219 #define FTPMU010_PSPR12 0x80
220 #define FTPMU010_PSPR13 0x84
221 #define FTPMU010_PSPR14 0x88
222 #define FTPMU010_PSPR15 0x8C
223 #define FTPMU010_AHBDMA_RACCS 0x90
224 #define FTPMU010_reserved2 0x94
225 #define FTPMU010_reserved3 0x98
226 #define FTPMU010_JSS 0x9C
227 #define FTPMU010_CFC_RACC 0xA0
228 #define FTPMU010_SSP1_RACC 0xA4
229 #define FTPMU010_UART1TX_RACC 0xA8
230 #define FTPMU010_UART1RX_RACC 0xAC
231 #define FTPMU010_UART2TX_RACC 0xB0
232 #define FTPMU010_UART2RX_RACC 0xB4
233 #define FTPMU010_SDC_RACC 0xB8
234 #define FTPMU010_I2SAC97_RACC 0xBC
235 #define FTPMU010_IRDATX_RACC 0xC0
236 #define FTPMU010_reserved4 0xC4
237 #define FTPMU010_USBD_RACC 0xC8
238 #define FTPMU010_IRDARX_RACC 0xCC
239 #define FTPMU010_IRDA_RACC 0xD0
240 #define FTPMU010_ED0_RACC 0xD4
241 #define FTPMU010_ED1_RACC 0xD8
242 #endif /* __ASSEMBLY__ */
181 243
182 #endif /* __FTPMU010_H */ 244 #endif /* __FTPMU010_H */
183 245