Eric Lee / smarc-uboot

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Commit d275c40c69cad09a139f4a1df874e68c086df7a7

Authored by Albert ARIBAUD \(3ADEV\)
Committed by Tom Rini
1 parent 5bd15b7a50
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

omap3: add support for QUIPOS Cairo board. 

This patch extends OMAP3 support for AM/DM37xx and
introduces the AM3703-based Quipos Cairo board.

Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Reviewed-by: Simon Glass <sjg@chromium.org>

Showing 7 changed files with 744 additions and 0 deletions Side-by-side Diff

arch/arm/cpu/armv7/omap3/Kconfig
Diff comments   View file @ d275c40
... ... @@ -91,6 +91,10 @@
91 91 bool "Twister"
92 92 select SUPPORT_SPL
93 93  
  94 +config TARGET_OMAP3_CAIRO
  95 + bool "QUIPOS CAIRO"
  96 + select SUPPORT_SPL
  97 +
94 98 endchoice
95 99  
96 100 config DM
... ... @@ -133,6 +137,7 @@
133 137 source "board/nokia/rx51/Kconfig"
134 138 source "board/technexion/tao3530/Kconfig"
135 139 source "board/technexion/twister/Kconfig"
  140 +source "board/quipos/cairo/Kconfig"
136 141  
137 142 endif
board/quipos/cairo/Kconfig
Diff comments   View file @ d275c40
  1 +if TARGET_OMAP3_CAIRO
  2 +
  3 +config SYS_BOARD
  4 + default "cairo"
  5 +
  6 +config SYS_VENDOR
  7 + default "quipos"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "omap3_cairo"
  11 +
  12 +endif
board/quipos/cairo/Makefile
Diff comments   View file @ d275c40
  1 +#
  2 +# (C) Copyright 2014 DENX Software Engineering
  3 +# Written-By: Albert ARIBAUD <albert.aribaud@3adev.fr>
  4 +#
  5 +# SPDX-License-Identifier: GPL-2.0+
  6 +#
  7 +
  8 +obj-y := cairo.o
board/quipos/cairo/cairo.c
Diff comments   View file @ d275c40
  1 +/*
  2 + * Copyright (c) 2014 DENX
  3 + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
  4 + *
  5 + * Derived from code written by Robert Aigner (ra@spiid.net)
  6 + *
  7 + * Itself derived from Beagle Board and 3430 SDP code by
  8 + * Richard Woodruff <r-woodruff2@ti.com>
  9 + * Syed Mohammed Khasim <khasim@ti.com>
  10 + *
  11 + * SPDX-License-Identifier: GPL-2.0+
  12 + */
  13 +#include <common.h>
  14 +#include <dm.h>
  15 +#include <netdev.h>
  16 +#include <ns16550.h>
  17 +#include <asm/io.h>
  18 +#include <asm/arch/mem.h>
  19 +#include <asm/arch/mux.h>
  20 +#include <asm/arch/sys_proto.h>
  21 +#include <i2c.h>
  22 +#include <asm/mach-types.h>
  23 +#include <asm/omap_mmc.h>
  24 +#include "cairo.h"
  25 +
  26 +DECLARE_GLOBAL_DATA_PTR;
  27 +
  28 +/*
  29 + * MUSB port on OMAP3EVM Rev >= E requires extvbus programming.
  30 + */
  31 +u8 omap3_evm_need_extvbus(void)
  32 +{
  33 + u8 retval = 0;
  34 +
  35 + /* TODO: verify if cairo handheld platform needs extvbus programming */
  36 +
  37 + return retval;
  38 +}
  39 +
  40 +/*
  41 + * Routine: board_init
  42 + * Description: Early hardware init.
  43 + */
  44 +int board_init(void)
  45 +{
  46 + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
  47 + /* board id for Linux */
  48 + gd->bd->bi_arch_number = MACH_TYPE_OMAP3_CAIRO;
  49 + /* boot param addr */
  50 + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
  51 + return 0;
  52 +}
  53 +
  54 +/*
  55 + * Routine: set_muxconf_regs
  56 + * Description: Setting up the configuration Mux registers specific to the
  57 + * hardware. Many pins need to be moved from protect to primary
  58 + * mode.
  59 + */
  60 +void set_muxconf_regs(void)
  61 +{
  62 + MUX_CAIRO();
  63 +}
  64 +
  65 +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
  66 +int board_mmc_init(bd_t *bis)
  67 +{
  68 + return omap_mmc_init(0, 0, 0, -1, -1);
  69 +}
  70 +#endif
  71 +
  72 +#ifdef CONFIG_SPL_BUILD
  73 +/*
  74 + * Routine: get_board_mem_timings
  75 + * Description: If we use SPL then there is no x-loader nor config header
  76 + * so we have to setup the DDR timings ourself on the first bank. This
  77 + * provides the timing values back to the function that configures
  78 + * the memory.
  79 + *
  80 + * The Cairo board uses SAMSUNG DDR - K4X51163PG-FGC6
  81 + */
  82 +void get_board_mem_timings(struct board_sdrc_timings *timings)
  83 +{
  84 + timings->sharing = SAMSUNG_SHARING;
  85 + timings->mcfg = SAMSUNG_V_MCFG_165(128 << 20);
  86 + timings->ctrla = SAMSUNG_V_ACTIMA_165;
  87 + timings->ctrlb = SAMSUNG_V_ACTIMB_165;
  88 + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
  89 + timings->mr = SAMSUNG_V_MR_165;
  90 +}
  91 +#endif
  92 +
  93 +static const struct ns16550_platdata cairo_serial = {
  94 + OMAP34XX_UART2,
  95 + 2,
  96 + V_NS16550_CLK
  97 +};
  98 +
  99 +U_BOOT_DEVICE(cairo_uart) = {
  100 + "serial_omap",
  101 + &cairo_serial
  102 +};
  103 +
  104 +/* force SPL booting into U-Boot, not Linux */
  105 +#ifdef CONFIG_SPL_OS_BOOT
  106 +int spl_start_uboot(void)
  107 +{
  108 + return 1;
  109 +}
  110 +#endif
board/quipos/cairo/cairo.h
Diff comments   View file @ d275c40
  1 +/*
  2 + * Copyright (C) DENX
  3 + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
  4 + *
  5 + * Original code (C) Copyright 2010
  6 + * Robert Aigner (ra@spiid.net)
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +#ifndef _EVM_H_
  11 +#define _EVM_H_
  12 +
  13 +
  14 +const omap3_sysinfo sysinfo = {
  15 + DDR_DISCRETE,
  16 + "OMAP3 Cairo board",
  17 + "NAND",
  18 +};
  19 +
  20 +/*
  21 + * OMAP3 Cairo handheld hardware revision
  22 + */
  23 +enum {
  24 + OMAP3_CAIRO_BOARD_GEN_1 = 0, /* Cairo handheld V01 */
  25 + OMAP3_CAIRO_BOARD_GEN_2,
  26 +};
  27 +
  28 +#define MUX_CAIRO() \
  29 +MUX_VAL(CONTROL_PADCONF_GPIO112, (IEN | PTD | EN | M7)) \
  30 +MUX_VAL(CONTROL_PADCONF_GPIO113, (IEN | PTD | EN | M7)) \
  31 +MUX_VAL(CONTROL_PADCONF_GPIO114, (IEN | PTD | EN | M7)) \
  32 +MUX_VAL(CONTROL_PADCONF_GPIO115, (IEN | PTD | EN | M7)) \
  33 +MUX_VAL(CONTROL_PADCONF_GPIO126, (IEN | PTD | EN | M7)) \
  34 +MUX_VAL(CONTROL_PADCONF_GPIO127, (IEN | PTD | EN | M7)) \
  35 +MUX_VAL(CONTROL_PADCONF_GPIO128, (IEN | PTD | EN | M7)) \
  36 +MUX_VAL(CONTROL_PADCONF_GPIO129, (IEN | PTD | EN | M7)) \
  37 +MUX_VAL(CONTROL_PADCONF_CAM_D0, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
  38 +MUX_VAL(CONTROL_PADCONF_CAM_D1, (IEN | DIS | SB_HIZ | M4)) \
  39 +MUX_VAL(CONTROL_PADCONF_CAM_D2, (IEN | DIS | SB_HIZ | M7)) \
  40 +MUX_VAL(CONTROL_PADCONF_CAM_D3, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
  41 +MUX_VAL(CONTROL_PADCONF_CAM_D4, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
  42 +MUX_VAL(CONTROL_PADCONF_CAM_D5, (IEN | PTD | EN | M7)) \
  43 +MUX_VAL(CONTROL_PADCONF_CAM_D6, (IEN | PTD | EN | SB_HIZ | SB_PD | M7)) \
  44 +MUX_VAL(CONTROL_PADCONF_CAM_D7, (IEN | PTD | EN | M7)) \
  45 +MUX_VAL(CONTROL_PADCONF_CAM_D8, (IEN | DIS | SB_HIZ | M7)) \
  46 +MUX_VAL(CONTROL_PADCONF_CAM_D9, (IEN | DIS | SB_HIZ | M4)) \
  47 +MUX_VAL(CONTROL_PADCONF_CAM_D10, (IEN | PTD | EN | M7)) \
  48 +MUX_VAL(CONTROL_PADCONF_CAM_D11, (IEN | PTD | EN | SB_LOW | SB_PD | M4)) \
  49 +MUX_VAL(CONTROL_PADCONF_CAM_FLD, (IEN | DIS | SB_HIZ | M4)) \
  50 +MUX_VAL(CONTROL_PADCONF_CAM_HS, (IEN | PTD | EN | SB_LOW | SB_PD | M4)) \
  51 +MUX_VAL(CONTROL_PADCONF_CAM_PCLK, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
  52 +MUX_VAL(CONTROL_PADCONF_CAM_STROBE, (IDIS | PTU | EN | SB_HI | SB_PU | M4)) \
  53 +MUX_VAL(CONTROL_PADCONF_CAM_VS, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
  54 +MUX_VAL(CONTROL_PADCONF_CAM_WEN, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
  55 +MUX_VAL(CONTROL_PADCONF_CAM_XCLKA, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
  56 +MUX_VAL(CONTROL_PADCONF_CAM_XCLKB, (IEN | DIS | SB_HIZ | SB_PD | M7)) \
  57 +MUX_VAL(CONTROL_PADCONF_DSS_ACBIAS, (IDIS | PTD | EN | SB_HIZ | SB_PD | M0)) \
  58 +MUX_VAL(CONTROL_PADCONF_DSS_DATA0, (IDIS | PTD | EN | M0)) \
  59 +MUX_VAL(CONTROL_PADCONF_DSS_DATA1, (IDIS | PTD | EN | M0)) \
  60 +MUX_VAL(CONTROL_PADCONF_DSS_DATA2, (IDIS | PTD | EN | M0)) \
  61 +MUX_VAL(CONTROL_PADCONF_DSS_DATA3, (IDIS | PTD | EN | M0)) \
  62 +MUX_VAL(CONTROL_PADCONF_DSS_DATA4, (IDIS | PTD | EN | M0)) \
  63 +MUX_VAL(CONTROL_PADCONF_DSS_DATA5, (IDIS | PTD | EN | M0)) \
  64 +MUX_VAL(CONTROL_PADCONF_DSS_DATA6, (IDIS | PTD | EN | M0)) \
  65 +MUX_VAL(CONTROL_PADCONF_DSS_DATA7, (IDIS | PTD | EN | M0)) \
  66 +MUX_VAL(CONTROL_PADCONF_DSS_DATA8, (IDIS | PTD | EN | M0)) \
  67 +MUX_VAL(CONTROL_PADCONF_DSS_DATA9, (IDIS | PTD | EN | M0)) \
  68 +MUX_VAL(CONTROL_PADCONF_DSS_DATA10, (IDIS | PTD | EN | M0)) \
  69 +MUX_VAL(CONTROL_PADCONF_DSS_DATA11, (IDIS | PTD | EN | M0)) \
  70 +MUX_VAL(CONTROL_PADCONF_DSS_DATA12, (IDIS | PTD | EN | M0)) \
  71 +MUX_VAL(CONTROL_PADCONF_DSS_DATA13, (IDIS | PTD | EN | M0)) \
  72 +MUX_VAL(CONTROL_PADCONF_DSS_DATA14, (IDIS | PTD | EN | M0)) \
  73 +MUX_VAL(CONTROL_PADCONF_DSS_DATA15, (IDIS | PTD | EN | M0)) \
  74 +MUX_VAL(CONTROL_PADCONF_DSS_DATA16, (IDIS | PTD | EN | M0)) \
  75 +MUX_VAL(CONTROL_PADCONF_DSS_DATA17, (IDIS | PTD | EN | M0)) \
  76 +MUX_VAL(CONTROL_PADCONF_DSS_DATA18, (IDIS | PTD | EN | M0)) \
  77 +MUX_VAL(CONTROL_PADCONF_DSS_DATA19, (IDIS | PTD | EN | M0)) \
  78 +MUX_VAL(CONTROL_PADCONF_DSS_DATA20, (IDIS | PTU | EN | M0)) \
  79 +MUX_VAL(CONTROL_PADCONF_DSS_DATA21, (IDIS | PTD | EN | M0)) \
  80 +MUX_VAL(CONTROL_PADCONF_DSS_DATA22, (IDIS | PTD | EN | M0)) \
  81 +MUX_VAL(CONTROL_PADCONF_DSS_DATA23, (IDIS | PTD | EN | M0)) \
  82 +MUX_VAL(CONTROL_PADCONF_DSS_HSYNC, (IDIS | PTU | EN | M0)) \
  83 +MUX_VAL(CONTROL_PADCONF_DSS_PCLK, (IDIS | PTU | EN | M0)) \
  84 +MUX_VAL(CONTROL_PADCONF_DSS_VSYNC, (IDIS | PTU | EN | M0)) \
  85 +MUX_VAL(CONTROL_PADCONF_ETK_CLK_ES2, (IDIS | PTU | EN | M3)) \
  86 +MUX_VAL(CONTROL_PADCONF_ETK_CTL_ES2, (IDIS | PTU | EN | M3)) \
  87 +MUX_VAL(CONTROL_PADCONF_ETK_D0_ES2, (IEN | PTU | EN | M3)) \
  88 +MUX_VAL(CONTROL_PADCONF_ETK_D1_ES2, (IEN | PTU | EN | M3)) \
  89 +MUX_VAL(CONTROL_PADCONF_ETK_D2_ES2, (IEN | PTU | EN | M3)) \
  90 +MUX_VAL(CONTROL_PADCONF_ETK_D3_ES2, (IEN | PTU | EN | M3)) \
  91 +MUX_VAL(CONTROL_PADCONF_ETK_D4_ES2, (IEN | PTD | EN | M3)) \
  92 +MUX_VAL(CONTROL_PADCONF_ETK_D5_ES2, (IEN | PTD | EN | M3)) \
  93 +MUX_VAL(CONTROL_PADCONF_ETK_D6_ES2, (IEN | PTD | EN | M3)) \
  94 +MUX_VAL(CONTROL_PADCONF_ETK_D7_ES2, (IEN | PTD | EN | M3)) \
  95 +MUX_VAL(CONTROL_PADCONF_ETK_D8_ES2, (IEN | PTD | EN | M3)) \
  96 +MUX_VAL(CONTROL_PADCONF_ETK_D9_ES2, (IEN | PTD | EN | M3)) \
  97 +MUX_VAL(CONTROL_PADCONF_ETK_D10_ES2, (IDIS | PTD | EN | M3)) \
  98 +MUX_VAL(CONTROL_PADCONF_ETK_D11_ES2, (IDIS | PTD | EN | M3)) \
  99 +MUX_VAL(CONTROL_PADCONF_ETK_D12_ES2, (IEN | PTD | EN | M3)) \
  100 +MUX_VAL(CONTROL_PADCONF_ETK_D13_ES2, (IEN | PTD | EN | M3)) \
  101 +MUX_VAL(CONTROL_PADCONF_ETK_D14_ES2, (IEN | PTD | EN | M3)) \
  102 +MUX_VAL(CONTROL_PADCONF_ETK_D15_ES2, (IEN | PTD | EN | M3)) \
  103 +MUX_VAL(CONTROL_PADCONF_GPMC_A1, (IEN | PTD | EN | M7)) \
  104 +MUX_VAL(CONTROL_PADCONF_GPMC_A2, (IEN | PTD | EN | M7)) \
  105 +MUX_VAL(CONTROL_PADCONF_GPMC_A3, (IEN | PTD | EN | M7)) \
  106 +MUX_VAL(CONTROL_PADCONF_GPMC_A4, (IEN | PTD | EN | M7)) \
  107 +MUX_VAL(CONTROL_PADCONF_GPMC_A5, (IEN | PTD | EN | M7)) \
  108 +MUX_VAL(CONTROL_PADCONF_GPMC_A6, (IEN | PTU | EN | M7)) \
  109 +MUX_VAL(CONTROL_PADCONF_GPMC_A7, (IEN | PTU | EN | M7)) \
  110 +MUX_VAL(CONTROL_PADCONF_GPMC_A8, (IEN | PTU | EN | M7)) \
  111 +MUX_VAL(CONTROL_PADCONF_GPMC_A9, (IEN | PTU | EN | M7)) \
  112 +MUX_VAL(CONTROL_PADCONF_GPMC_A10, (IEN | PTU | EN | M7)) \
  113 +MUX_VAL(CONTROL_PADCONF_GPMC_A11, (IEN | PTD | EN | M7)) \
  114 +MUX_VAL(CONTROL_PADCONF_GPMC_CLK, (IEN | DIS | M7)) \
  115 +MUX_VAL(CONTROL_PADCONF_GPMC_D0, (IEN | PTU | EN | M0)) \
  116 +MUX_VAL(CONTROL_PADCONF_GPMC_D1, (IEN | PTU | EN | M0)) \
  117 +MUX_VAL(CONTROL_PADCONF_GPMC_D2, (IEN | PTU | EN | M0)) \
  118 +MUX_VAL(CONTROL_PADCONF_GPMC_D3, (IEN | PTU | EN | M0)) \
  119 +MUX_VAL(CONTROL_PADCONF_GPMC_D4, (IEN | PTU | EN | M0)) \
  120 +MUX_VAL(CONTROL_PADCONF_GPMC_D5, (IEN | PTU | EN | M0)) \
  121 +MUX_VAL(CONTROL_PADCONF_GPMC_D6, (IEN | PTU | EN | M0)) \
  122 +MUX_VAL(CONTROL_PADCONF_GPMC_D7, (IEN | PTU | EN | M0)) \
  123 +MUX_VAL(CONTROL_PADCONF_GPMC_D8, (IEN | PTU | EN | M7)) \
  124 +MUX_VAL(CONTROL_PADCONF_GPMC_D9, (IEN | PTU | EN | M7)) \
  125 +MUX_VAL(CONTROL_PADCONF_GPMC_D10, (IEN | PTU | EN | M7)) \
  126 +MUX_VAL(CONTROL_PADCONF_GPMC_D11, (IEN | PTU | EN | M7)) \
  127 +MUX_VAL(CONTROL_PADCONF_GPMC_D12, (IEN | PTU | EN | M7)) \
  128 +MUX_VAL(CONTROL_PADCONF_GPMC_D13, (IEN | PTU | EN | M7)) \
  129 +MUX_VAL(CONTROL_PADCONF_GPMC_D14, (IEN | PTU | EN | M7)) \
  130 +MUX_VAL(CONTROL_PADCONF_GPMC_D15, (IEN | PTU | EN | M7)) \
  131 +MUX_VAL(CONTROL_PADCONF_GPMC_NADV_ALE, (IDIS | DIS | M0)) \
  132 +MUX_VAL(CONTROL_PADCONF_GPMC_NBE0_CLE, (IDIS | DIS | M0)) \
  133 +MUX_VAL(CONTROL_PADCONF_GPMC_NBE1, (IEN | PTD | EN | M7)) \
  134 +MUX_VAL(CONTROL_PADCONF_GPMC_NCS0, (IDIS | DIS | SB_HIZ | SB_PD | M0)) \
  135 +MUX_VAL(CONTROL_PADCONF_GPMC_NCS1, (IEN | DIS | M7)) \
  136 +MUX_VAL(CONTROL_PADCONF_GPMC_NCS2, (IEN | PTU | EN | M7)) \
  137 +MUX_VAL(CONTROL_PADCONF_GPMC_NCS3, (IEN | PTU | EN | M7)) \
  138 +MUX_VAL(CONTROL_PADCONF_GPMC_NCS4, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \
  139 +MUX_VAL(CONTROL_PADCONF_GPMC_NCS5, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \
  140 +MUX_VAL(CONTROL_PADCONF_GPMC_NCS6, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \
  141 +MUX_VAL(CONTROL_PADCONF_GPMC_NCS7, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \
  142 +MUX_VAL(CONTROL_PADCONF_GPMC_NOE, (IDIS | DIS | M0)) \
  143 +MUX_VAL(CONTROL_PADCONF_GPMC_NWE, (IDIS | DIS | M0)) \
  144 +MUX_VAL(CONTROL_PADCONF_GPMC_NWP, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
  145 +MUX_VAL(CONTROL_PADCONF_GPMC_WAIT0, (IEN | DIS | SB_HIZ | M0)) \
  146 +MUX_VAL(CONTROL_PADCONF_GPMC_WAIT1, (IEN | PTU | EN | M7)) \
  147 +MUX_VAL(CONTROL_PADCONF_GPMC_WAIT2, (IEN | PTU | EN | M7)) \
  148 +MUX_VAL(CONTROL_PADCONF_GPMC_WAIT3, (IEN | PTU | EN | M7)) \
  149 +MUX_VAL(CONTROL_PADCONF_HDQ_SIO, (IEN | DIS | SB_HIZ | M4)) \
  150 +MUX_VAL(CONTROL_PADCONF_HSUSB0_CLK, (IEN | PTD | EN | M0)) \
  151 +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA0, (IEN | PTD | EN | M0)) \
  152 +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA1, (IEN | PTD | EN | M0)) \
  153 +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA2, (IEN | PTD | EN | M0)) \
  154 +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA3, (IEN | PTD | EN | M0)) \
  155 +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA4, (IEN | PTD | EN | M0)) \
  156 +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA5, (IEN | PTD | EN | M0)) \
  157 +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA6, (IEN | PTD | EN | M0)) \
  158 +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA7, (IEN | PTD | EN | M0)) \
  159 +MUX_VAL(CONTROL_PADCONF_HSUSB0_DIR, (IEN | PTD | EN | M0)) \
  160 +MUX_VAL(CONTROL_PADCONF_HSUSB0_NXT, (IEN | PTD | EN | M0)) \
  161 +MUX_VAL(CONTROL_PADCONF_HSUSB0_STP, (IDIS | PTU | EN | M0)) \
  162 +MUX_VAL(CONTROL_PADCONF_I2C1_SCL, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
  163 +MUX_VAL(CONTROL_PADCONF_I2C1_SDA, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
  164 +MUX_VAL(CONTROL_PADCONF_I2C2_SCL, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
  165 +MUX_VAL(CONTROL_PADCONF_I2C2_SDA, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
  166 +MUX_VAL(CONTROL_PADCONF_I2C3_SCL, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
  167 +MUX_VAL(CONTROL_PADCONF_I2C3_SDA, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
  168 +MUX_VAL(CONTROL_PADCONF_I2C4_SCL, (IEN | PTU | EN | M7)) \
  169 +MUX_VAL(CONTROL_PADCONF_I2C4_SDA, (IEN | PTU | EN | M7)) \
  170 +MUX_VAL(CONTROL_PADCONF_JTAG_EMU0, (IEN | PTU | EN | M0)) \
  171 +MUX_VAL(CONTROL_PADCONF_JTAG_EMU1, (IEN | PTU | EN | M0)) \
  172 +MUX_VAL(CONTROL_PADCONF_JTAG_NTRST, (IEN | PTD | EN | M0)) \
  173 +MUX_VAL(CONTROL_PADCONF_JTAG_RTCK, (IDIS | DIS | M0)) \
  174 +MUX_VAL(CONTROL_PADCONF_JTAG_TCK, (IEN | PTD | EN | M0)) \
  175 +MUX_VAL(CONTROL_PADCONF_JTAG_TDI, (IEN | PTU | EN | M0)) \
  176 +MUX_VAL(CONTROL_PADCONF_JTAG_TDO, (IDIS | DIS | M0)) \
  177 +MUX_VAL(CONTROL_PADCONF_JTAG_TMS, (IEN | PTU | EN | M0)) \
  178 +MUX_VAL(CONTROL_PADCONF_MCBSP_CLKS, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
  179 +MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKR, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
  180 +MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKX, (IEN | DIS | SB_HIZ | M4)) \
  181 +MUX_VAL(CONTROL_PADCONF_MCBSP1_DR, (IEN | DIS | SB_HIZ | M4)) \
  182 +MUX_VAL(CONTROL_PADCONF_MCBSP1_DX, (IEN | DIS | SB_HIZ | SB_PD | M7)) \
  183 +MUX_VAL(CONTROL_PADCONF_MCBSP1_FSR, (IEN | PTD | EN | M7)) \
  184 +MUX_VAL(CONTROL_PADCONF_MCBSP1_FSX, (IEN | DIS | SB_HIZ | M4)) \
  185 +MUX_VAL(CONTROL_PADCONF_MCBSP2_CLKX, (IEN | PTD | EN | M7)) \
  186 +MUX_VAL(CONTROL_PADCONF_MCBSP2_DR, (IEN | PTD | EN | M7)) \
  187 +MUX_VAL(CONTROL_PADCONF_MCBSP2_DX, (IEN | PTD | EN | M7)) \
  188 +MUX_VAL(CONTROL_PADCONF_MCBSP2_FSX, (IEN | PTD | EN | M7)) \
  189 +MUX_VAL(CONTROL_PADCONF_MCBSP3_CLKX, (IDIS | DIS | SB_HIZ | SB_PU | M1)) \
  190 +MUX_VAL(CONTROL_PADCONF_MCBSP3_DR, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
  191 +MUX_VAL(CONTROL_PADCONF_MCBSP3_DX, (IEN | PTD | EN | M7)) \
  192 +MUX_VAL(CONTROL_PADCONF_MCBSP3_FSX, (IEN | PTU | EN | SB_HIZ | SB_PU | M1)) \
  193 +MUX_VAL(CONTROL_PADCONF_MCBSP4_CLKX, (IEN | PTD | EN | M7)) \
  194 +MUX_VAL(CONTROL_PADCONF_MCBSP4_DR, (IEN | PTD | EN | M7)) \
  195 +MUX_VAL(CONTROL_PADCONF_MCBSP4_DX, (IEN | PTD | EN | M7)) \
  196 +MUX_VAL(CONTROL_PADCONF_MCBSP4_FSX, (IEN | PTD | EN | M7)) \
  197 +MUX_VAL(CONTROL_PADCONF_MCSPI1_CLK, (IEN | PTD | EN | M0)) \
  198 +MUX_VAL(CONTROL_PADCONF_MCSPI1_CS0, (IEN | PTU | EN | SB_HIZ | SB_PD | M0)) \
  199 +MUX_VAL(CONTROL_PADCONF_MCSPI1_CS1, (IEN | PTU | EN | M7)) \
  200 +MUX_VAL(CONTROL_PADCONF_MCSPI1_CS2, (IEN | PTU | EN | M7)) \
  201 +MUX_VAL(CONTROL_PADCONF_MCSPI1_CS3, (IEN | PTU | EN | M3)) \
  202 +MUX_VAL(CONTROL_PADCONF_MCSPI1_SIMO, (IEN | PTD | EN | M0)) \
  203 +MUX_VAL(CONTROL_PADCONF_MCSPI1_SOMI, (IEN | PTD | EN | M0)) \
  204 +MUX_VAL(CONTROL_PADCONF_MCSPI2_CLK, (IEN | PTD | EN | M3)) \
  205 +MUX_VAL(CONTROL_PADCONF_MCSPI2_CS0, (IEN | PTU | EN | M3)) \
  206 +MUX_VAL(CONTROL_PADCONF_MCSPI2_CS1, (IEN | PTD | EN | M3)) \
  207 +MUX_VAL(CONTROL_PADCONF_MCSPI2_SIMO, (IEN | PTD | EN | M3)) \
  208 +MUX_VAL(CONTROL_PADCONF_MCSPI2_SOMI, (IEN | PTD | EN | M3)) \
  209 +MUX_VAL(CONTROL_PADCONF_MMC1_CLK, (IDIS | PTU | EN | SB_HIZ | SB_PU | M0)) \
  210 +MUX_VAL(CONTROL_PADCONF_MMC1_CMD, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
  211 +MUX_VAL(CONTROL_PADCONF_MMC1_DAT0, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
  212 +MUX_VAL(CONTROL_PADCONF_MMC1_DAT1, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
  213 +MUX_VAL(CONTROL_PADCONF_MMC1_DAT2, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
  214 +MUX_VAL(CONTROL_PADCONF_MMC1_DAT3, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
  215 +MUX_VAL(CONTROL_PADCONF_MMC2_CLK, (IEN | PTD | EN | SB_HIZ | SB_PU | M0)) \
  216 +MUX_VAL(CONTROL_PADCONF_MMC2_CMD, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
  217 +MUX_VAL(CONTROL_PADCONF_MMC2_DAT0, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
  218 +MUX_VAL(CONTROL_PADCONF_MMC2_DAT1, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
  219 +MUX_VAL(CONTROL_PADCONF_MMC2_DAT2, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
  220 +MUX_VAL(CONTROL_PADCONF_MMC2_DAT3, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
  221 +MUX_VAL(CONTROL_PADCONF_MMC2_DAT4, (IDIS | DIS | SB_HIZ | M0)) \
  222 +MUX_VAL(CONTROL_PADCONF_MMC2_DAT5, (IDIS | DIS | SB_HIZ | M0)) \
  223 +MUX_VAL(CONTROL_PADCONF_MMC2_DAT6, (IDIS | DIS | SB_HIZ | M0)) \
  224 +MUX_VAL(CONTROL_PADCONF_MMC2_DAT7, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
  225 +MUX_VAL(CONTROL_PADCONF_SDRC_A0, (IDIS | DIS | M0)) \
  226 +MUX_VAL(CONTROL_PADCONF_SDRC_A1, (IDIS | DIS | M0)) \
  227 +MUX_VAL(CONTROL_PADCONF_SDRC_A2, (IDIS | DIS | M0)) \
  228 +MUX_VAL(CONTROL_PADCONF_SDRC_A3, (IDIS | DIS | M0)) \
  229 +MUX_VAL(CONTROL_PADCONF_SDRC_A4, (IDIS | DIS | M0)) \
  230 +MUX_VAL(CONTROL_PADCONF_SDRC_A5, (IDIS | DIS | M0)) \
  231 +MUX_VAL(CONTROL_PADCONF_SDRC_A6, (IDIS | DIS | M0)) \
  232 +MUX_VAL(CONTROL_PADCONF_SDRC_A7, (IDIS | DIS | M0)) \
  233 +MUX_VAL(CONTROL_PADCONF_SDRC_A8, (IDIS | DIS | M0)) \
  234 +MUX_VAL(CONTROL_PADCONF_SDRC_A9, (IDIS | DIS | M0)) \
  235 +MUX_VAL(CONTROL_PADCONF_SDRC_A10, (IDIS | DIS | M0)) \
  236 +MUX_VAL(CONTROL_PADCONF_SDRC_A11, (IDIS | DIS | M0)) \
  237 +MUX_VAL(CONTROL_PADCONF_SDRC_A12, (IDIS | DIS | M0)) \
  238 +MUX_VAL(CONTROL_PADCONF_SDRC_A13, (IDIS | DIS | M0)) \
  239 +MUX_VAL(CONTROL_PADCONF_SDRC_A14, (IDIS | DIS | M0)) \
  240 +MUX_VAL(CONTROL_PADCONF_SDRC_BA0, (IDIS | DIS | M0)) \
  241 +MUX_VAL(CONTROL_PADCONF_SDRC_BA1, (IDIS | DIS | M0)) \
  242 +MUX_VAL(CONTROL_PADCONF_SDRC_CKE0, (IDIS | DIS | M0)) \
  243 +MUX_VAL(CONTROL_PADCONF_SDRC_CKE1, (IDIS | DIS | M7)) \
  244 +MUX_VAL(CONTROL_PADCONF_SDRC_CLK, (IEN | DIS | M0)) \
  245 +MUX_VAL(CONTROL_PADCONF_SDRC_D0, (IEN | DIS | M0)) \
  246 +MUX_VAL(CONTROL_PADCONF_SDRC_D1, (IEN | DIS | M0)) \
  247 +MUX_VAL(CONTROL_PADCONF_SDRC_D2, (IEN | DIS | M0)) \
  248 +MUX_VAL(CONTROL_PADCONF_SDRC_D3, (IEN | DIS | M0)) \
  249 +MUX_VAL(CONTROL_PADCONF_SDRC_D4, (IEN | DIS | M0)) \
  250 +MUX_VAL(CONTROL_PADCONF_SDRC_D5, (IEN | DIS | M0)) \
  251 +MUX_VAL(CONTROL_PADCONF_SDRC_D6, (IEN | DIS | M0)) \
  252 +MUX_VAL(CONTROL_PADCONF_SDRC_D7, (IEN | DIS | M0)) \
  253 +MUX_VAL(CONTROL_PADCONF_SDRC_D8, (IEN | DIS | M0)) \
  254 +MUX_VAL(CONTROL_PADCONF_SDRC_D9, (IEN | DIS | M0)) \
  255 +MUX_VAL(CONTROL_PADCONF_SDRC_D10, (IEN | DIS | M0)) \
  256 +MUX_VAL(CONTROL_PADCONF_SDRC_D11, (IEN | DIS | M0)) \
  257 +MUX_VAL(CONTROL_PADCONF_SDRC_D12, (IEN | DIS | M0)) \
  258 +MUX_VAL(CONTROL_PADCONF_SDRC_D13, (IEN | DIS | M0)) \
  259 +MUX_VAL(CONTROL_PADCONF_SDRC_D14, (IEN | DIS | M0)) \
  260 +MUX_VAL(CONTROL_PADCONF_SDRC_D15, (IEN | DIS | M0)) \
  261 +MUX_VAL(CONTROL_PADCONF_SDRC_D16, (IEN | DIS | M0)) \
  262 +MUX_VAL(CONTROL_PADCONF_SDRC_D17, (IEN | DIS | M0)) \
  263 +MUX_VAL(CONTROL_PADCONF_SDRC_D18, (IEN | DIS | M0)) \
  264 +MUX_VAL(CONTROL_PADCONF_SDRC_D19, (IEN | DIS | M0)) \
  265 +MUX_VAL(CONTROL_PADCONF_SDRC_D20, (IEN | DIS | M0)) \
  266 +MUX_VAL(CONTROL_PADCONF_SDRC_D21, (IEN | DIS | M0)) \
  267 +MUX_VAL(CONTROL_PADCONF_SDRC_D22, (IEN | DIS | M0)) \
  268 +MUX_VAL(CONTROL_PADCONF_SDRC_D23, (IEN | DIS | M0)) \
  269 +MUX_VAL(CONTROL_PADCONF_SDRC_D24, (IEN | DIS | M0)) \
  270 +MUX_VAL(CONTROL_PADCONF_SDRC_D25, (IEN | DIS | M0)) \
  271 +MUX_VAL(CONTROL_PADCONF_SDRC_D26, (IEN | DIS | M0)) \
  272 +MUX_VAL(CONTROL_PADCONF_SDRC_D27, (IEN | DIS | M0)) \
  273 +MUX_VAL(CONTROL_PADCONF_SDRC_D28, (IEN | DIS | M0)) \
  274 +MUX_VAL(CONTROL_PADCONF_SDRC_D29, (IEN | DIS | M0)) \
  275 +MUX_VAL(CONTROL_PADCONF_SDRC_D30, (IEN | DIS | M0)) \
  276 +MUX_VAL(CONTROL_PADCONF_SDRC_D31, (IEN | DIS | M0)) \
  277 +MUX_VAL(CONTROL_PADCONF_SDRC_DM0, (IDIS | DIS | M0)) \
  278 +MUX_VAL(CONTROL_PADCONF_SDRC_DM1, (IDIS | DIS | M0)) \
  279 +MUX_VAL(CONTROL_PADCONF_SDRC_DM2, (IDIS | DIS | M0)) \
  280 +MUX_VAL(CONTROL_PADCONF_SDRC_DM3, (IDIS | DIS | M0)) \
  281 +MUX_VAL(CONTROL_PADCONF_SDRC_DQS0, (IEN | DIS | M0)) \
  282 +MUX_VAL(CONTROL_PADCONF_SDRC_DQS1, (IEN | DIS | M0)) \
  283 +MUX_VAL(CONTROL_PADCONF_SDRC_DQS2, (IEN | DIS | M0)) \
  284 +MUX_VAL(CONTROL_PADCONF_SDRC_DQS3, (IEN | DIS | M0)) \
  285 +MUX_VAL(CONTROL_PADCONF_SDRC_NCAS, (IDIS | DIS | M0)) \
  286 +MUX_VAL(CONTROL_PADCONF_SDRC_NCLK, (IDIS | DIS | M0)) \
  287 +MUX_VAL(CONTROL_PADCONF_SDRC_NCS0, (IDIS | DIS | M0)) \
  288 +MUX_VAL(CONTROL_PADCONF_SDRC_NCS1, (IDIS | DIS | M0)) \
  289 +MUX_VAL(CONTROL_PADCONF_SDRC_NRAS, (IDIS | DIS | M0)) \
  290 +MUX_VAL(CONTROL_PADCONF_SDRC_NWE, (IDIS | DIS | M0)) \
  291 +MUX_VAL(CONTROL_PADCONF_SYS_32K, (IEN | DIS | M0)) \
  292 +MUX_VAL(CONTROL_PADCONF_SYS_BOOT0, (IEN | DIS | M0)) \
  293 +MUX_VAL(CONTROL_PADCONF_SYS_BOOT1, (IEN | DIS | M0)) \
  294 +MUX_VAL(CONTROL_PADCONF_SYS_BOOT2, (IEN | DIS | M0)) \
  295 +MUX_VAL(CONTROL_PADCONF_SYS_BOOT3, (IEN | DIS | M0)) \
  296 +MUX_VAL(CONTROL_PADCONF_SYS_BOOT4, (IEN | DIS | M0)) \
  297 +MUX_VAL(CONTROL_PADCONF_SYS_BOOT5, (IEN | DIS | M0)) \
  298 +MUX_VAL(CONTROL_PADCONF_SYS_BOOT6, (IEN | DIS | M0)) \
  299 +MUX_VAL(CONTROL_PADCONF_SYS_CLKOUT1, (IDIS | PTD | EN | M0)) \
  300 +MUX_VAL(CONTROL_PADCONF_SYS_CLKOUT2, (IDIS | PTD | EN | M0)) \
  301 +MUX_VAL(CONTROL_PADCONF_SYS_CLKREQ, (IEN | DIS | M0)) \
  302 +MUX_VAL(CONTROL_PADCONF_SYS_NIRQ, (IEN | PTU | EN | M0)) \
  303 +MUX_VAL(CONTROL_PADCONF_SYS_NRESWARM, (IEN | PTU | EN | M0)) \
  304 +MUX_VAL(CONTROL_PADCONF_SYS_OFF_MODE, (IDIS | PTD | EN | M0)) \
  305 +MUX_VAL(CONTROL_PADCONF_UART1_CTS, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
  306 +MUX_VAL(CONTROL_PADCONF_UART1_RTS, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
  307 +MUX_VAL(CONTROL_PADCONF_UART1_RX, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
  308 +MUX_VAL(CONTROL_PADCONF_UART1_TX, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
  309 +MUX_VAL(CONTROL_PADCONF_UART2_CTS, (IEN | PTU | EN | M7)) \
  310 +MUX_VAL(CONTROL_PADCONF_UART2_RTS, (IEN | PTU | EN | M7)) \
  311 +MUX_VAL(CONTROL_PADCONF_UART2_RX, (IEN | PTU | EN | M7)) \
  312 +MUX_VAL(CONTROL_PADCONF_UART2_TX, (IEN | PTU | EN | M7)) \
  313 +MUX_VAL(CONTROL_PADCONF_UART3_CTS_RCTX, \
  314 + (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
  315 +MUX_VAL(CONTROL_PADCONF_UART3_RTS_SD, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
  316 +MUX_VAL(CONTROL_PADCONF_UART3_RX_IRRX, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
  317 +MUX_VAL(CONTROL_PADCONF_UART3_TX_IRTX, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
  318 +
  319 +#endif
configs/cairo_defconfig
Diff comments   View file @ d275c40
  1 +CONFIG_SPL=y
  2 ++S:CONFIG_ARM=y
  3 ++S:CONFIG_OMAP34XX=y
  4 ++S:CONFIG_TARGET_OMAP3_CAIRO=y
include/configs/omap3_cairo.h
Diff comments   View file @ d275c40
  1 +/*
  2 + * Configuration settings for the QUIPOS Cairo board.
  3 + *
  4 + * Copyright (C) DENX GmbH
  5 + *
  6 + * Author :
  7 + * Albert ARIBAUD <albert.aribaud@3adev.fr>
  8 + *
  9 + * Derived from EVM code by
  10 + * Manikandan Pillai <mani.pillai@ti.com>
  11 + * Itself derived from Beagle Board and 3430 SDP code by
  12 + * Richard Woodruff <r-woodruff2@ti.com>
  13 + * Syed Mohammed Khasim <khasim@ti.com>
  14 + *
  15 + * Also derived from include/configs/omap3_beagle.h
  16 + *
  17 + * SPDX-License-Identifier: GPL-2.0+
  18 + */
  19 +
  20 +#ifndef __OMAP3_CAIRO_CONFIG_H
  21 +#define __OMAP3_CAIRO_CONFIG_H
  22 +
  23 +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
  24 +
  25 +/*
  26 + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
  27 + * 64 bytes before this address should be set aside for u-boot.img's
  28 + * header. That is 0x800FFFC0--0x80100000 should not be used for any
  29 + * other needs. We use this rather than the inherited defines from
  30 + * ti_armv7_common.h for backwards compatibility.
  31 + */
  32 +#define CONFIG_SYS_TEXT_BASE 0x80100000
  33 +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
  34 +#define CONFIG_SPL_BSS_START_ADDR 0x80000000
  35 +#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */
  36 +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
  37 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  38 +
  39 +#define CONFIG_NAND
  40 +
  41 +#include <configs/ti_omap3_common.h>
  42 +
  43 +/*
  44 + * Display CPU and Board information
  45 + */
  46 +#define CONFIG_DISPLAY_CPUINFO 1
  47 +#define CONFIG_DISPLAY_BOARDINFO 1
  48 +
  49 +#define CONFIG_MISC_INIT_R
  50 +
  51 +#define CONFIG_REVISION_TAG 1
  52 +#define CONFIG_ENV_OVERWRITE
  53 +
  54 +/* Enable Multi Bus support for I2C */
  55 +#define CONFIG_I2C_MULTI_BUS 1
  56 +
  57 +/* Probe all devices */
  58 +#define CONFIG_SYS_I2C_NOPROBES { {0x0, 0x0} }
  59 +
  60 +#define CONFIG_NAND
  61 +
  62 +/* commands to include */
  63 +#include <config_cmd_default.h>
  64 +
  65 +#define CONFIG_CMD_SETEXPR /* Evaluate expressions */
  66 +#define CONFIG_CMD_NAND_LOCK_UNLOCK
  67 +
  68 +/* Disable some commands */
  69 +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
  70 +#undef CONFIG_CMD_IMI /* iminfo */
  71 +#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
  72 +
  73 +/*
  74 + * TWL4030
  75 + */
  76 +#define CONFIG_TWL4030_LED 1
  77 +
  78 +/*
  79 + * Board NAND Info.
  80 + */
  81 +#define CONFIG_SYS_NAND_QUIET_TEST 1
  82 +#define CONFIG_NAND_OMAP_GPMC
  83 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
  84 + /* devices */
  85 +/* override default CONFIG_BOOTDELAY */
  86 +#undef CONFIG_BOOTDELAY
  87 +#define CONFIG_BOOTDELAY 0
  88 +
  89 +#define CONFIG_EXTRA_ENV_SETTINGS \
  90 + "machid=ffffffff\0" \
  91 + "fdt_high=0x87000000\0" \
  92 + "baudrate=115200\0" \
  93 + "ethaddr=00:50:C2:7E:90:F0\0" \
  94 + "fec_addr=00:50:C2:7E:90:F0\0" \
  95 + "netmask=255.255.255.0\0" \
  96 + "ipaddr=192.168.2.9\0" \
  97 + "gateway=192.168.2.1\0" \
  98 + "serverip=192.168.2.10\0" \
  99 + "nfshost=192.168.2.10\0" \
  100 + "stdin=serial\0" \
  101 + "stdout=serial\0" \
  102 + "stderr=serial\0" \
  103 + "bootargs_mmc_ramdisk=mem=128M " \
  104 + "console=ttyO1,115200n8 " \
  105 + "root=/dev/ram0 rw " \
  106 + "initrd=0x81600000,16M " \
  107 + "mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \
  108 + "omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \
  109 + "mmcboot=mmc init; " \
  110 + "fatload mmc 0 0x80000000 uImage; " \
  111 + "fatload mmc 0 0x81600000 ramdisk.gz; " \
  112 + "setenv bootargs ${bootargs_mmc_ramdisk}; " \
  113 + "bootm 0x80000000\0" \
  114 + "bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \
  115 + "root=/dev/nfs " \
  116 + "nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \
  117 + "mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \
  118 + "omap_vout.vid1_static_vrfb_alloc=y\0" \
  119 + "boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \
  120 + "bootm 0x80000000\0" \
  121 + "bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \
  122 + "root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \
  123 + "omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \
  124 + "omapfb.rotate_type=1\0" \
  125 + "boot_nand=nand read.i 0x80000000 280000 300000; setenv " \
  126 + "bootargs ${bootargs_nand}; bootm 0x80000000\0" \
  127 + "ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
  128 + "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
  129 + "i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \
  130 + "ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
  131 + "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \
  132 + "mw 60 09 00 1; i2c mw 60 06 10 1\0" \
  133 + "ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
  134 + "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
  135 + "i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \
  136 + "ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
  137 + "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
  138 + "i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \
  139 + "flash_xloader=mw.b 0x81600000 0xff 0x20000; " \
  140 + "nand erase 0 20000; " \
  141 + "fatload mmc 0 0x81600000 MLO; " \
  142 + "nandecc hw; " \
  143 + "nand write.i 0x81600000 0 20000;\0" \
  144 + "flash_uboot=mw.b 0x81600000 0xff 0x40000; " \
  145 + "nand erase 80000 40000; " \
  146 + "fatload mmc 0 0x81600000 u-boot.bin; " \
  147 + "nandecc sw; " \
  148 + "nand write.i 0x81600000 80000 40000;\0" \
  149 + "flash_kernel=mw.b 0x81600000 0xff 0x300000; " \
  150 + "nand erase 280000 300000; " \
  151 + "fatload mmc 0 0x81600000 uImage; " \
  152 + "nandecc sw; " \
  153 + "nand write.i 0x81600000 280000 300000;\0" \
  154 + "flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \
  155 + "nandecc sw; " \
  156 + "nand write.jffs2 0x680000 0xFF ${filesize}; " \
  157 + "nand erase 680000 ${filesize}; " \
  158 + "nand write.jffs2 81600000 680000 ${filesize};\0" \
  159 + "flash_scrub=nand scrub; " \
  160 + "run flash_xloader; " \
  161 + "run flash_uboot; " \
  162 + "run flash_kernel; " \
  163 + "run flash_rootfs;\0" \
  164 + "flash_all=run ledred; " \
  165 + "nand erase.chip; " \
  166 + "run ledorange; " \
  167 + "run flash_xloader; " \
  168 + "run flash_uboot; " \
  169 + "run flash_kernel; " \
  170 + "run flash_rootfs; " \
  171 + "run ledgreen; " \
  172 + "run boot_nand; \0" \
  173 +
  174 +#define CONFIG_BOOTCOMMAND \
  175 + "if fatload mmc 0 0x81600000 MLO; then run flash_all; " \
  176 + "else run boot_nand; fi"
  177 +
  178 +/*
  179 + * OMAP3 has 12 GP timers, they can be driven by the system clock
  180 + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
  181 + * This rate is divided by a local divisor.
  182 + */
  183 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
  184 +
  185 +/*-----------------------------------------------------------------------
  186 + * FLASH and environment organization
  187 + */
  188 +
  189 +/* **** PISMO SUPPORT *** */
  190 +#if defined(CONFIG_CMD_NAND)
  191 +#define CONFIG_SYS_FLASH_BASE NAND_BASE
  192 +#endif
  193 +
  194 +/* Monitor at start of flash */
  195 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  196 +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
  197 +
  198 +#define CONFIG_ENV_IS_IN_NAND 1
  199 +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
  200 +#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
  201 +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
  202 +
  203 +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
  204 +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
  205 +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
  206 +
  207 +#define CONFIG_OMAP3_SPI
  208 +
  209 +#define CONFIG_SYS_CACHELINE_SIZE 64
  210 +
  211 +/* Defines for SPL */
  212 +#define CONFIG_SPL_OMAP3_ID_NAND
  213 +
  214 +/* NAND boot config */
  215 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
  216 +#define CONFIG_SYS_NAND_PAGE_COUNT 64
  217 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048
  218 +#define CONFIG_SYS_NAND_OOBSIZE 64
  219 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
  220 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
  221 +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
  222 + 10, 11, 12, 13}
  223 +#define CONFIG_SYS_NAND_ECCSIZE 512
  224 +#define CONFIG_SYS_NAND_ECCBYTES 3
  225 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
  226 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
  227 +/* NAND: SPL falcon mode configs */
  228 +#ifdef CONFIG_SPL_OS_BOOT
  229 +#define CONFIG_CMD_SPL_NAND_OFS 0x240000
  230 +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
  231 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
  232 +#endif
  233 +
  234 +/* env defaults */
  235 +#define CONFIG_BOOTFILE "uImage"
  236 +
  237 +/* Override OMAP3 common serial console configuration from UART3
  238 + * to UART2.
  239 + *
  240 + * Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3)
  241 + * are needed and peripheral clocks for UART2 must be enabled in
  242 + * function per_clocks_enable().
  243 + */
  244 +#undef CONFIG_CONS_INDEX
  245 +#define CONFIG_CONS_INDEX 2
  246 +#ifdef CONFIG_SPL_BUILD
  247 +#undef CONFIG_SYS_NS16550_COM3
  248 +#define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2
  249 +#undef CONFIG_SERIAL3
  250 +#define CONFIG_SERIAL2
  251 +#endif
  252 +
  253 +/* Keep old prompt in case some existing script depends on it */
  254 +#undef CONFIG_SYS_PROMPT
  255 +#define CONFIG_SYS_PROMPT "Cairo # "
  256 +
  257 +/* Provide MACH_TYPE for compatibility with non-DT kernels */
  258 +#define MACH_TYPE_OMAP3_CAIRO 3063
  259 +#define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CAIRO
  260 +
  261 +/*-----------------------------------------------------------------------
  262 + * FLASH and environment organization
  263 + */
  264 +
  265 +/* **** PISMO SUPPORT *** */
  266 +
  267 +#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
  268 + /* on one chip */
  269 +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
  270 +
  271 +/*-----------------------------------------------------------------------
  272 + * CFI FLASH driver setup
  273 + */
  274 +/* timeout values are in ticks */
  275 +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
  276 +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
  277 +
  278 +/* Flash banks JFFS2 should use */
  279 +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
  280 + CONFIG_SYS_MAX_NAND_DEVICE)
  281 +#define CONFIG_SYS_JFFS2_MEM_NAND
  282 +/* use flash_info[2] */
  283 +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
  284 +#define CONFIG_SYS_JFFS2_NUM_BANKS 1
  285 +
  286 +#endif /* __OMAP3_CAIRO_CONFIG_H */