Eric Lee / smarc-uboot

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Commit d27ca2cade7f6460ea8c248d3aa55b5337c9f411

Authored by Bai Ping
Committed by Ye Li
1 parent 95e018dc7e
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 5 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

MLK-18367 imx8mm: change the GIC clock source 

The GIC clock rate has some limitation, it should be
set to higher than 100MHz when NOC frequency is set to
the highest frequency. So switch the GIC clock source
to sys_pll2_100mhz.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit bd4cfcb391389287894bb5cd715be0a67f6332cf)

Showing 1 changed file with 6 additions and 2 deletions Side-by-side Diff

arch/arm/mach-imx/imx8m/clock_imx8mm.c
Diff comments   View file @ d27ca2c
... ... @@ -488,8 +488,6 @@
488 488 {
489 489 uint32_t val_cfg0;
490 490  
491   - clock_enable(CCGR_GIC, 1);
492   -
493 491 /* Configure ARM at 1GHz */
494 492 clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON | \
495 493 CLK_ROOT_SOURCE_SEL(0));
... ... @@ -523,6 +521,12 @@
523 521 writel(val_cfg0, SYS_PLL2_GNRL_CTL);
524 522  
525 523 intpll_configure(ANATOP_SYSTEM_PLL3, INTPLL_OUT_800M);
  524 +
  525 + /* config GIC to sys_pll2_100m */
  526 + clock_enable(CCGR_GIC, 0);
  527 + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(3));
  528 + clock_enable(CCGR_GIC, 1);
  529 +
526 530 /*
527 531 * set uart clock root
528 532 * 24M OSC