serial: pl01x: move all line control at same place

Receive line control uses same setting as transmit line control, also one lcrh write is effective for both baud rate & receive line control internal update. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Acked-by: Simon Glass <sjg@chromium.org>

serial: pl01x: move all line control at same place
Receive line control uses same setting as transmit line control, also one lcrh write is effective for both baud rate & receive line control internal update. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Acked-by: Simon Glass <sjg@chromium.org>
Vikas Manocha · Tom Rini
1 parent 2df810717e
Showing 1 changed file with 21 additions and 23 deletions Side-by-side Diff
drivers/serial/serial_pl01x.c
@@ -72,8 +72,6 @@
 static int pl01x_generic_serial_init(struct pl01x_regs *regs,
 				     enum pl01x_type type)
 {
-	unsigned int lcr;
-
 #ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
 	if (type == TYPE_PL011) {
 		/* Empty RX fifo if necessary */
  
  
@@ -87,15 +85,28 @@
 	/* First, disable everything */
 	writel(0, &regs->pl010_cr);
  
-	/* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
-	lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
-	writel(lcr, &regs->pl011_lcrh);
-
 	switch (type) {
 	case TYPE_PL010:
 		break;
-	case TYPE_PL011: {
+	case TYPE_PL011:
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int set_line_control(struct pl01x_regs *regs)
+{
+	unsigned int lcr;
+	/*
+	 * Internal update of baud rate register require line
+	 * control register write
+	 */
+	lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
 #ifdef CONFIG_PL011_SERIAL_RLCR
+	{
 		int i;
  
 		/*
  
  
@@ -107,22 +118,15 @@
 			writel(lcr, &regs->fr);
  
 		writel(lcr, &regs->pl011_rlcr);
-		/* lcrh needs to be set again for change to be effective */
-		writel(lcr, &regs->pl011_lcrh);
-#endif
-		break;
 	}
-	default:
-		return -EINVAL;
-	}
-
+#endif
+	writel(lcr, &regs->pl011_lcrh);
 	return 0;
 }
  
 static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
 				int clock, int baudrate)
 {
-	unsigned int lcr;
 	switch (type) {
 	case TYPE_PL010: {
 		unsigned int divisor;
@@ -176,13 +180,7 @@
 		writel(divider, &regs->pl011_ibrd);
 		writel(fraction, &regs->pl011_fbrd);
  
-		/*
-		 * Internal update of baud rate register require line
-		 * control register write
-		 */
-		lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
-		writel(lcr, &regs->pl011_lcrh);
-
+		set_line_control(regs);
 		/* Finally, enable the UART */
 		writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
 		       UART_PL011_CR_RXE | UART_PL011_CR_RTS, &regs->pl011_cr);
...	...	@@ -72,8 +72,6 @@
72	72	static int pl01x_generic_serial_init(struct pl01x_regs *regs,
73	73	enum pl01x_type type)
74	74	{
75		- unsigned int lcr;
76		-
77	75	#ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
78	76	if (type == TYPE_PL011) {
79	77	/* Empty RX fifo if necessary */
80	78
81	79
...	...	@@ -87,15 +85,28 @@
87	85	/* First, disable everything */
88	86	writel(0, &regs->pl010_cr);
89	87
90		- /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
91		- lcr = UART_PL011_LCRH_WLEN_8 \| UART_PL011_LCRH_FEN;
92		- writel(lcr, &regs->pl011_lcrh);
93		-
94	88	switch (type) {
95	89	case TYPE_PL010:
96	90	break;
97		- case TYPE_PL011: {
	91	+ case TYPE_PL011:
	92	+ break;
	93	+ default:
	94	+ return -EINVAL;
	95	+ }
	96	+
	97	+ return 0;
	98	+}
	99	+
	100	+static int set_line_control(struct pl01x_regs *regs)
	101	+{
	102	+ unsigned int lcr;
	103	+ /*
	104	+ * Internal update of baud rate register require line
	105	+ * control register write
	106	+ */
	107	+ lcr = UART_PL011_LCRH_WLEN_8 \| UART_PL011_LCRH_FEN;
98	108	#ifdef CONFIG_PL011_SERIAL_RLCR
	109	+ {
99	110	int i;
100	111
101	112	/*
102	113
103	114
...	...	@@ -107,22 +118,15 @@
107	118	writel(lcr, &regs->fr);
108	119
109	120	writel(lcr, &regs->pl011_rlcr);
110		- /* lcrh needs to be set again for change to be effective */
111		- writel(lcr, &regs->pl011_lcrh);
112		-#endif
113		- break;
114	121	}
115		- default:
116		- return -EINVAL;
117		- }
118		-
	122	+#endif
	123	+ writel(lcr, &regs->pl011_lcrh);
119	124	return 0;
120	125	}
121	126
122	127	static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
123	128	int clock, int baudrate)
124	129	{
125		- unsigned int lcr;
126	130	switch (type) {
127	131	case TYPE_PL010: {
128	132	unsigned int divisor;
...	...	@@ -176,13 +180,7 @@
176	180	writel(divider, &regs->pl011_ibrd);
177	181	writel(fraction, &regs->pl011_fbrd);
178	182
179		- /*
180		- * Internal update of baud rate register require line
181		- * control register write
182		- */
183		- lcr = UART_PL011_LCRH_WLEN_8 \| UART_PL011_LCRH_FEN;
184		- writel(lcr, &regs->pl011_lcrh);
185		-
	183	+ set_line_control(regs);
186	184	/* Finally, enable the UART */
187	185	writel(UART_PL011_CR_UARTEN \| UART_PL011_CR_TXE \|
188	186	UART_PL011_CR_RXE \| UART_PL011_CR_RTS, &regs->pl011_cr);