Eric Lee / smarc-uboot

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Commit d35488c7359ac5b6e20d9fe1895360aa7f3122f2

Authored by Hans de Goede
1 parent 40d0cdda3e
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

sunxi: rsb: Add sun9i (A80 support) 

Add support for the A80 to the rsb code.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

Showing 4 changed files with 25 additions and 2 deletions Side-by-side Diff

arch/arm/cpu/armv7/sunxi/Makefile
Diff comments   View file @ d35488c
... ... @@ -15,8 +15,10 @@
15 15 obj-y += usbc.o
16 16 obj-$(CONFIG_MACH_SUN6I) += prcm.o
17 17 obj-$(CONFIG_MACH_SUN8I) += prcm.o
  18 +obj-$(CONFIG_MACH_SUN9I) += prcm.o
18 19 obj-$(CONFIG_MACH_SUN6I) += p2wi.o
19 20 obj-$(CONFIG_MACH_SUN8I) += rsb.o
  21 +obj-$(CONFIG_MACH_SUN9I) += rsb.o
20 22 obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o
21 23 obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
22 24 obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o
arch/arm/cpu/armv7/sunxi/rsb.c
Diff comments   View file @ d35488c
... ... @@ -18,12 +18,23 @@
18 18  
19 19 static void rsb_cfg_io(void)
20 20 {
  21 +#ifdef CONFIG_MACH_SUN8I
21 22 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL0_R_RSB_SCK);
22 23 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL1_R_RSB_SDA);
23 24 sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
24 25 sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
25 26 sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
26 27 sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
  28 +#elif defined CONFIG_MACH_SUN9I
  29 + sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN0_R_RSB_SCK);
  30 + sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN1_R_RSB_SDA);
  31 + sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
  32 + sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
  33 + sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
  34 + sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
  35 +#else
  36 +#error unsupported MACH_SUNXI
  37 +#endif
27 38 }
28 39  
29 40 static void rsb_set_clk(void)
arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
Diff comments   View file @ d35488c
... ... @@ -73,7 +73,6 @@
73 73 #define SUNXI_CCM_BASE (REGS_APB0_BASE + 0x0000)
74 74 #define SUNXI_CCMMODULE_BASE (REGS_APB0_BASE + 0x0400)
75 75 #define SUNXI_PIO_BASE (REGS_APB0_BASE + 0x0800)
76   -#define SUNXI_R_PIO_BASE (0x08002C00)
77 76 #define SUNXI_TIMER_BASE (REGS_APB0_BASE + 0x0C00)
78 77 #define SUNXI_PWM_BASE (REGS_APB0_BASE + 0x1400)
79 78 #define SUNXI_LRADC_BASE (REGS_APB0_BASE + 0x1800)
80 79  
... ... @@ -92,8 +91,10 @@
92 91 #define SUNXI_TWI4_BASE (REGS_APB1_BASE + 0x3800)
93 92  
94 93 /* RCPUS Module */
95   -#define SUNXI_RPRCM_BASE (REGS_RCPUS_BASE + 0x1400)
  94 +#define SUNXI_PRCM_BASE (REGS_RCPUS_BASE + 0x1400)
96 95 #define SUNXI_R_UART_BASE (REGS_RCPUS_BASE + 0x2800)
  96 +#define SUNXI_R_PIO_BASE (REGS_RCPUS_BASE + 0x2c00)
  97 +#define SUNXI_RSB_BASE (REGS_RCPUS_BASE + 0x3400)
97 98  
98 99 /* Misc. */
99 100 #define SUNXI_BROM_BASE 0xFFFF0000 /* 32K */
arch/arm/include/asm/arch-sunxi/gpio.h
Diff comments   View file @ d35488c
... ... @@ -45,9 +45,13 @@
45 45 *
46 46 * sun8i has 1 bank:
47 47 * PL0 - PL11
  48 + *
  49 + * sun9i has 3 banks:
  50 + * PL0 - PL9 | PM0 - PM15 | PN0 - PN1
48 51 */
49 52 #define SUNXI_GPIO_L 11
50 53 #define SUNXI_GPIO_M 12
  54 +#define SUNXI_GPIO_N 13
51 55  
52 56 struct sunxi_gpio {
53 57 u32 cfg[4];
... ... @@ -114,6 +118,7 @@
114 118 SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H),
115 119 SUNXI_GPIO_L_START = 352,
116 120 SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),
  121 + SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M),
117 122 SUNXI_GPIO_AXP0_START = 1024,
118 123 };
119 124  
... ... @@ -129,6 +134,7 @@
129 134 #define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr))
130 135 #define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr))
131 136 #define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr))
  137 +#define SUNXI_GPN(_nr) (SUNXI_GPIO_N_START + (_nr))
132 138  
133 139 #define SUNXI_GPAXP0(_nr) (SUNXI_GPIO_AXP0_START + (_nr))
134 140  
... ... @@ -186,6 +192,9 @@
186 192 #define SUN8I_GPL1_R_RSB_SDA 2
187 193 #define SUN8I_GPL2_R_UART_TX 2
188 194 #define SUN8I_GPL3_R_UART_RX 2
  195 +
  196 +#define SUN9I_GPN0_R_RSB_SCK 3
  197 +#define SUN9I_GPN1_R_RSB_SDA 3
189 198  
190 199 /* GPIO pin pull-up/down config */
191 200 #define SUNXI_GPIO_PULL_DISABLE 0