Commit d35831f6fedbdfb0ce49814a225e854e5fa83c99
1 parent
b7ca250189
Exists in
v2017.01-smarct4x
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arm: mvebu: Move SAR register defines into header
This is preparation for the runtime bootmode detection in spl.c. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Phil Sutter <phil@nwl.cc> Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
Showing 2 changed files with 24 additions and 16 deletions Side-by-side Diff
arch/arm/mach-mvebu/cpu.c
| 1 | 1 | /* |
| 2 | - * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> | |
| 2 | + * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de> | |
| 3 | 3 | * |
| 4 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | 5 | */ |
| ... | ... | @@ -62,11 +62,7 @@ |
| 62 | 62 | #if defined(CONFIG_DISPLAY_CPUINFO) |
| 63 | 63 | |
| 64 | 64 | #if defined(CONFIG_ARMADA_38X) |
| 65 | -/* SAR values for Armada 38x */ | |
| 66 | -#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600)) | |
| 67 | -#define SAR_CPU_FREQ_OFFS 10 | |
| 68 | -#define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS) | |
| 69 | - | |
| 65 | +/* SAR frequency values for Armada 38x */ | |
| 70 | 66 | struct sar_freq_modes sar_freq_tab[] = { |
| 71 | 67 | { 0x0, 0x0, 666, 333, 333 }, |
| 72 | 68 | { 0x2, 0x0, 800, 400, 400 }, |
| ... | ... | @@ -77,16 +73,7 @@ |
| 77 | 73 | { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */ |
| 78 | 74 | }; |
| 79 | 75 | #else |
| 80 | -/* SAR values for Armada XP */ | |
| 81 | -#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) | |
| 82 | -#define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234)) | |
| 83 | -#define SAR_CPU_FREQ_OFFS 21 | |
| 84 | -#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS) | |
| 85 | -#define SAR_FFC_FREQ_OFFS 24 | |
| 86 | -#define SAR_FFC_FREQ_MASK (0xf << SAR_FFC_FREQ_OFFS) | |
| 87 | -#define SAR2_CPU_FREQ_OFFS 20 | |
| 88 | -#define SAR2_CPU_FREQ_MASK (0x1 << SAR2_CPU_FREQ_OFFS) | |
| 89 | - | |
| 76 | +/* SAR frequency values for Armada XP */ | |
| 90 | 77 | struct sar_freq_modes sar_freq_tab[] = { |
| 91 | 78 | { 0xa, 0x5, 800, 400, 400 }, |
| 92 | 79 | { 0x1, 0x5, 1066, 533, 533 }, |
arch/arm/mach-mvebu/include/mach/soc.h
| ... | ... | @@ -96,5 +96,26 @@ |
| 96 | 96 | #define MVCPU_WIN_ENABLE CPU_WIN_ENABLE |
| 97 | 97 | #define MVCPU_WIN_DISABLE CPU_WIN_DISABLE |
| 98 | 98 | |
| 99 | +#if defined(CONFIG_ARMADA_38X) | |
| 100 | +/* SAR values for Armada 38x */ | |
| 101 | +#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600)) | |
| 102 | +#define SAR_CPU_FREQ_OFFS 10 | |
| 103 | +#define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS) | |
| 104 | +#define SAR_BOOT_DEVICE_OFFS 4 | |
| 105 | +#define SAR_BOOT_DEVICE_MASK (0x1f << SAR_BOOT_DEVICE_OFFS) | |
| 106 | +#else | |
| 107 | +/* SAR values for Armada XP */ | |
| 108 | +#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) | |
| 109 | +#define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234)) | |
| 110 | +#define SAR_CPU_FREQ_OFFS 21 | |
| 111 | +#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS) | |
| 112 | +#define SAR_FFC_FREQ_OFFS 24 | |
| 113 | +#define SAR_FFC_FREQ_MASK (0xf << SAR_FFC_FREQ_OFFS) | |
| 114 | +#define SAR2_CPU_FREQ_OFFS 20 | |
| 115 | +#define SAR2_CPU_FREQ_MASK (0x1 << SAR2_CPU_FREQ_OFFS) | |
| 116 | +#define SAR_BOOT_DEVICE_OFFS 5 | |
| 117 | +#define SAR_BOOT_DEVICE_MASK (0xf << SAR_BOOT_DEVICE_OFFS) | |
| 118 | +#endif | |
| 119 | + | |
| 99 | 120 | #endif /* _MVEBU_SOC_H */ |