Eric Lee / smarc-uboot

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Commit d3c23a790fb24f9cb5cc467b81b0c3ad3eeb1f96

Authored by Haavard Skinnemoen
2 parents fcd69a1a57 33eac2b3d9
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Merge branch 'next' of git://git.denx.de/u-boot-avr32 

Conflicts:

	MAINTAINERS

Showing 30 changed files Side-by-side Diff

... ... @@ -217,6 +217,10 @@
217 217 E: r.ireland@computer.org
218 218 D: FPGA device configuration driver
219 219  
  220 +H: Mark Jackson
  221 +E: mpfj@mimc.co.uk
  222 +D: Port to MIMC200 board
  223 +
220 224 N: Gary Jennejohn
221 225 E: garyj@jennejohn.org, gj@denx.de
222 226 D: Support for Samsung ARM920T S3C2400X, ARM920T "TRAB"
... ... @@ -712,7 +712,20 @@
712 712 # Board CPU #
713 713 #########################################################################
714 714  
715   -Haavard Skinnemoen <hskinnemoen@atmel.com>
  715 +Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
  716 +
  717 + FAVR-32-EZKIT AT32AP7000
  718 +
  719 +Mark Jackson <mpfj@mimc.co.uk>
  720 +
  721 + MIMC200 AT32AP7000
  722 +
  723 +Alex Raimondi <alex.raimondi@miromico.ch>
  724 +Julien May <julien.may@miromico.ch>
  725 +
  726 + HAMMERHEAD AT32AP7000
  727 +
  728 +Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
716 729  
717 730 ATSTK1000 AT32AP7xxx
718 731 ATSTK1002 AT32AP7000
... ... @@ -719,6 +719,9 @@
719 719 atstk1004 \
720 720 atstk1006 \
721 721 atngw100 \
  722 + favr-32-ezkit \
  723 + hammerhead \
  724 + mimc200 \
722 725 "
723 726  
724 727 #########################################################################
... ... @@ -2973,6 +2973,15 @@
2973 2973 atstk1006_config : unconfig
2974 2974 @$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x
2975 2975  
  2976 +favr-32-ezkit_config : unconfig
  2977 + @$(MKCONFIG) $(@:_config=) avr32 at32ap favr-32-ezkit earthlcd at32ap700x
  2978 +
  2979 +hammerhead_config : unconfig
  2980 + @$(MKCONFIG) $(@:_config=) avr32 at32ap hammerhead miromico at32ap700x
  2981 +
  2982 +mimc200_config : unconfig
  2983 + @$(MKCONFIG) $(@:_config=) avr32 at32ap mimc200 mimc at32ap700x
  2984 +
2976 2985 #========================================================================
2977 2986 # SH3 (SuperH)
2978 2987 #========================================================================
board/atmel/atngw100/Makefile
Diff comments   View file @ d3c23a7
... ... @@ -22,7 +22,7 @@
22 22  
23 23 LIB := $(obj)lib$(BOARD).a
24 24  
25   -COBJS := $(BOARD).o eth.o
  25 +COBJS := $(BOARD).o
26 26  
27 27 SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
28 28 OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
board/atmel/atngw100/atngw100.c
Diff comments   View file @ d3c23a7
... ... @@ -93,6 +93,17 @@
93 93 gd->bd->bi_phy_id[1] = 0x03;
94 94 }
95 95  
  96 +extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
  97 +
  98 +#ifdef CONFIG_CMD_NET
  99 +int board_eth_init(bd_t *bi)
  100 +{
  101 + macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]);
  102 + macb_eth_initialize(1, (void *)MACB1_BASE, bi->bi_phy_id[1]);
  103 + return 0;
  104 +}
  105 +#endif
  106 +
96 107 /* SPI chip select control */
97 108 #ifdef CONFIG_ATMEL_SPI
98 109 #include <spi.h>
board/atmel/atngw100/eth.c
View file @ d3c23a7
1   -/*
2   - * Copyright (C) 2006 Atmel Corporation
3   - *
4   - * Ethernet initialization for the AVR32 Network Gateway
5   - *
6   - * See file CREDITS for list of people who contributed to this
7   - * project.
8   - *
9   - * This program is free software; you can redistribute it and/or
10   - * modify it under the terms of the GNU General Public License as
11   - * published by the Free Software Foundation; either version 2 of
12   - * the License, or (at your option) any later version.
13   - *
14   - * This program is distributed in the hope that it will be useful,
15   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
16   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17   - * GNU General Public License for more details.
18   - *
19   - * You should have received a copy of the GNU General Public License
20   - * along with this program; if not, write to the Free Software
21   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22   - * MA 02111-1307 USA
23   - */
24   -#include <common.h>
25   -
26   -#include <asm/arch/memory-map.h>
27   -
28   -extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
29   -
30   -#ifdef CONFIG_CMD_NET
31   -void atngw100_eth_initialize(bd_t *bi)
32   -{
33   - macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]);
34   - macb_eth_initialize(1, (void *)MACB1_BASE, bi->bi_phy_id[1]);
35   -}
36   -#endif
board/atmel/atstk1000/Makefile
Diff comments   View file @ d3c23a7
... ... @@ -26,7 +26,7 @@
26 26  
27 27 LIB := $(obj)lib$(BOARD).a
28 28  
29   -COBJS := $(BOARD).o flash.o eth.o
  29 +COBJS := $(BOARD).o flash.o
30 30  
31 31 SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
32 32 OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
board/atmel/atstk1000/atstk1000.c
Diff comments   View file @ d3c23a7
... ... @@ -115,4 +115,15 @@
115 115 gd->bd->bi_phy_id[0] = 0x10;
116 116 gd->bd->bi_phy_id[1] = 0x11;
117 117 }
  118 +
  119 +extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
  120 +
  121 +#ifdef CONFIG_CMD_NET
  122 +int board_eth_init(bd_t *bi)
  123 +{
  124 + macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]);
  125 + macb_eth_initialize(1, (void *)MACB1_BASE, bi->bi_phy_id[1]);
  126 + return 0;
  127 +}
  128 +#endif
board/atmel/atstk1000/eth.c
View file @ d3c23a7
1   -/*
2   - * Copyright (C) 2005-2006 Atmel Corporation
3   - *
4   - * Ethernet initialization for the ATSTK1000 starterkit
5   - *
6   - * See file CREDITS for list of people who contributed to this
7   - * project.
8   - *
9   - * This program is free software; you can redistribute it and/or
10   - * modify it under the terms of the GNU General Public License as
11   - * published by the Free Software Foundation; either version 2 of
12   - * the License, or (at your option) any later version.
13   - *
14   - * This program is distributed in the hope that it will be useful,
15   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
16   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17   - * GNU General Public License for more details.
18   - *
19   - * You should have received a copy of the GNU General Public License
20   - * along with this program; if not, write to the Free Software
21   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22   - * MA 02111-1307 USA
23   - */
24   -#include <common.h>
25   -
26   -#include <asm/arch/memory-map.h>
27   -
28   -extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
29   -
30   -#if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET)
31   -void atstk1000_eth_initialize(bd_t *bi)
32   -{
33   - int id = 0;
34   -
35   - macb_eth_initialize(id++, (void *)MACB0_BASE, bi->bi_phy_id[0]);
36   - macb_eth_initialize(id++, (void *)MACB1_BASE, bi->bi_phy_id[1]);
37   -}
38   -#endif
board/earthlcd/favr-32-ezkit/Makefile
Diff comments   View file @ d3c23a7
  1 +#
  2 +# (C) Copyright 2001-2006
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# Copyright (C) 2008 Atmel Corporation
  6 +#
  7 +# See file CREDITS for list of people who contributed to this project.
  8 +#
  9 +# This program is free software; you can redistribute it and/or modify it under
  10 +# the terms of the GNU General Public License as published by the Free Software
  11 +# Foundation; either version 2 of the License, or (at your option) any later
  12 +# version.
  13 +#
  14 +# This program is distributed in the hope that it will be useful, but WITHOUT
  15 +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
  16 +# FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
  17 +# details.
  18 +#
  19 +# You should have received a copy of the GNU General Public License along with
  20 +# this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  21 +# Place, Suite 330, Boston, MA 02111-1307 USA
  22 +
  23 +include $(TOPDIR)/config.mk
  24 +
  25 +LIB := $(obj)lib$(BOARD).a
  26 +
  27 +COBJS := $(BOARD).o flash.o
  28 +
  29 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
  30 +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
  31 +
  32 +$(LIB): $(obj).depend $(OBJS)
  33 + $(AR) $(ARFLAGS) $@ $(OBJS)
  34 +
  35 +#########################################################################
  36 +
  37 +# defines $(obj).depend target
  38 +include $(SRCTREE)/rules.mk
  39 +
  40 +sinclude $(obj).depend
  41 +
  42 +#########################################################################
board/earthlcd/favr-32-ezkit/config.mk
Diff comments   View file @ d3c23a7
  1 +PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
  2 +PLATFORM_LDFLAGS += --gc-sections
  3 +TEXT_BASE = 0x00000000
  4 +LDSCRIPT = $(obj)board/earthlcd/favr-32-ezkit/u-boot.lds
board/earthlcd/favr-32-ezkit/favr-32-ezkit.c
Diff comments   View file @ d3c23a7
  1 +/*
  2 + * Copyright (C) 2008 Atmel Corporation
  3 + *
  4 + * See file CREDITS for list of people who contributed to this project.
  5 + *
  6 + * This program is free software; you can redistribute it and/or modify it
  7 + * under the terms of the GNU General Public License as published by the Free
  8 + * Software Foundation; either version 2 of the License, or (at your option)
  9 + * any later version.
  10 + *
  11 + * This program is distributed in the hope that it will be useful, but WITHOUT
  12 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14 + * more details.
  15 + *
  16 + * You should have received a copy of the GNU General Public License along with
  17 + * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  18 + * Place, Suite 330, Boston, MA 02111-1307 USA
  19 + */
  20 +#include <common.h>
  21 +
  22 +#include <asm/io.h>
  23 +#include <asm/sdram.h>
  24 +#include <asm/arch/clk.h>
  25 +#include <asm/arch/gpio.h>
  26 +#include <asm/arch/hmatrix.h>
  27 +
  28 +DECLARE_GLOBAL_DATA_PTR;
  29 +
  30 +static const struct sdram_config sdram_config = {
  31 + /* MT48LC4M32B2P-6 (16 MB) */
  32 + .data_bits = SDRAM_DATA_32BIT,
  33 + .row_bits = 12,
  34 + .col_bits = 8,
  35 + .bank_bits = 2,
  36 + .cas = 3,
  37 + .twr = 2,
  38 + .trc = 7,
  39 + .trp = 2,
  40 + .trcd = 2,
  41 + .tras = 5,
  42 + .txsr = 5,
  43 + /* 15.6 us */
  44 + .refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
  45 +};
  46 +
  47 +int board_early_init_f(void)
  48 +{
  49 + /* Enable SDRAM in the EBI mux */
  50 + hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
  51 +
  52 + gpio_enable_ebi();
  53 + gpio_enable_usart3();
  54 +#if defined(CONFIG_MACB)
  55 + gpio_enable_macb0();
  56 +#endif
  57 +#if defined(CONFIG_MMC)
  58 + gpio_enable_mmci();
  59 +#endif
  60 +
  61 + return 0;
  62 +}
  63 +
  64 +phys_size_t initdram(int board_type)
  65 +{
  66 + unsigned long expected_size;
  67 + unsigned long actual_size;
  68 + void *sdram_base;
  69 +
  70 + sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
  71 +
  72 + expected_size = sdram_init(sdram_base, &sdram_config);
  73 + actual_size = get_ram_size(sdram_base, expected_size);
  74 +
  75 + unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
  76 +
  77 + if (expected_size != actual_size)
  78 + printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
  79 + actual_size >> 20, expected_size >> 20);
  80 +
  81 + return actual_size;
  82 +}
  83 +
  84 +void board_init_info(void)
  85 +{
  86 + gd->bd->bi_phy_id[0] = 0x01;
  87 +}
  88 +
  89 +#if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET)
  90 +extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
  91 +
  92 +int board_eth_init(bd_t *bi)
  93 +{
  94 + return macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]);
  95 +}
  96 +#endif
board/earthlcd/favr-32-ezkit/flash.c
Diff comments   View file @ d3c23a7
  1 +/*
  2 + * Copyright (C) 2008 Atmel Corporation
  3 + *
  4 + * See file CREDITS for list of people who contributed to this project.
  5 + *
  6 + * This program is free software; you can redistribute it and/or modify it
  7 + * under the terms of the GNU General Public License as published by the Free
  8 + * Software Foundation; either version 2 of the License, or (at your option)
  9 + * any later version.
  10 + *
  11 + * This program is distributed in the hope that it will be useful, but WITHOUT
  12 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14 + * more details.
  15 + *
  16 + * You should have received a copy of the GNU General Public License along with
  17 + * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  18 + * Place, Suite 330, Boston, MA 02111-1307 USA
  19 + */
  20 +#include <common.h>
  21 +
  22 +#ifdef CONFIG_FAVR32_EZKIT_EXT_FLASH
  23 +#include <asm/cacheflush.h>
  24 +#include <asm/io.h>
  25 +#include <asm/sections.h>
  26 +
  27 +DECLARE_GLOBAL_DATA_PTR;
  28 +
  29 +flash_info_t flash_info[1];
  30 +
  31 +static void flash_identify(uint16_t *flash, flash_info_t *info)
  32 +{
  33 + unsigned long flags;
  34 +
  35 + flags = disable_interrupts();
  36 +
  37 + dcache_flush_unlocked();
  38 +
  39 + writew(0xaa, flash + 0x555);
  40 + writew(0x55, flash + 0xaaa);
  41 + writew(0x90, flash + 0x555);
  42 + info->flash_id = readl(flash);
  43 + writew(0xff, flash);
  44 +
  45 + readw(flash);
  46 +
  47 + if (flags)
  48 + enable_interrupts();
  49 +}
  50 +
  51 +unsigned long flash_init(void)
  52 +{
  53 + unsigned long addr;
  54 + unsigned int i;
  55 +
  56 + flash_info[0].size = CFG_FLASH_SIZE;
  57 + flash_info[0].sector_count = 135;
  58 +
  59 + flash_identify(uncached((void *)CFG_FLASH_BASE), &flash_info[0]);
  60 +
  61 + for (i = 0, addr = 0; i < 8; i++, addr += 0x2000)
  62 + flash_info[0].start[i] = addr;
  63 + for (; i < flash_info[0].sector_count; i++, addr += 0x10000)
  64 + flash_info[0].start[i] = addr;
  65 +
  66 + return CFG_FLASH_SIZE;
  67 +}
  68 +
  69 +void flash_print_info(flash_info_t *info)
  70 +{
  71 + printf("Flash: Vendor ID: 0x%02lx, Product ID: 0x%02lx\n",
  72 + info->flash_id >> 16, info->flash_id & 0xffff);
  73 + printf("Size: %ld MB in %d sectors\n",
  74 + info->size >> 10, info->sector_count);
  75 +}
  76 +
  77 +int flash_erase(flash_info_t *info, int s_first, int s_last)
  78 +{
  79 + unsigned long flags;
  80 + unsigned long start_time;
  81 + uint16_t *fb, *sb;
  82 + unsigned int i;
  83 + int ret;
  84 + uint16_t status;
  85 +
  86 + if ((s_first < 0) || (s_first > s_last)
  87 + || (s_last >= info->sector_count)) {
  88 + puts("Error: first and/or last sector out of range\n");
  89 + return ERR_INVAL;
  90 + }
  91 +
  92 + for (i = s_first; i < s_last; i++)
  93 + if (info->protect[i]) {
  94 + printf("Error: sector %d is protected\n", i);
  95 + return ERR_PROTECTED;
  96 + }
  97 +
  98 + fb = (uint16_t *)uncached(info->start[0]);
  99 +
  100 + dcache_flush_unlocked();
  101 +
  102 + for (i = s_first; (i <= s_last) && !ctrlc(); i++) {
  103 + printf("Erasing sector %3d...", i);
  104 +
  105 + sb = (uint16_t *)uncached(info->start[i]);
  106 +
  107 + flags = disable_interrupts();
  108 +
  109 + start_time = get_timer(0);
  110 +
  111 + /* Unlock sector */
  112 + writew(0xaa, fb + 0x555);
  113 + writew(0x70, sb);
  114 +
  115 + /* Erase sector */
  116 + writew(0xaa, fb + 0x555);
  117 + writew(0x55, fb + 0xaaa);
  118 + writew(0x80, fb + 0x555);
  119 + writew(0xaa, fb + 0x555);
  120 + writew(0x55, fb + 0xaaa);
  121 + writew(0x30, sb);
  122 +
  123 + /* Wait for completion */
  124 + ret = ERR_OK;
  125 + do {
  126 + /* TODO: Timeout */
  127 + status = readw(sb);
  128 + } while ((status != 0xffff) && !(status & 0x28));
  129 +
  130 + writew(0xf0, fb);
  131 +
  132 + /*
  133 + * Make sure the command actually makes it to the bus
  134 + * before we re-enable interrupts.
  135 + */
  136 + readw(fb);
  137 +
  138 + if (flags)
  139 + enable_interrupts();
  140 +
  141 + if (status != 0xffff) {
  142 + printf("Flash erase error at address 0x%p: 0x%02x\n",
  143 + sb, status);
  144 + ret = ERR_PROG_ERROR;
  145 + break;
  146 + }
  147 + }
  148 +
  149 + if (ctrlc())
  150 + printf("User interrupt!\n");
  151 +
  152 + return ERR_OK;
  153 +}
  154 +
  155 +int write_buff(flash_info_t *info, uchar *src,
  156 + ulong addr, ulong count)
  157 +{
  158 + unsigned long flags;
  159 + uint16_t *base, *p, *s, *end;
  160 + uint16_t word, status, status1;
  161 + int ret = ERR_OK;
  162 +
  163 + if (addr < info->start[0]
  164 + || (addr + count) > (info->start[0] + info->size)
  165 + || (addr + count) < addr) {
  166 + puts("Error: invalid address range\n");
  167 + return ERR_INVAL;
  168 + }
  169 +
  170 + if (addr & 1 || count & 1 || (unsigned int)src & 1) {
  171 + puts("Error: misaligned source, destination or count\n");
  172 + return ERR_ALIGN;
  173 + }
  174 +
  175 + base = (uint16_t *)uncached(info->start[0]);
  176 + end = (uint16_t *)uncached(addr + count);
  177 +
  178 + flags = disable_interrupts();
  179 +
  180 + dcache_flush_unlocked();
  181 + sync_write_buffer();
  182 +
  183 + for (p = (uint16_t *)uncached(addr), s = (uint16_t *)src;
  184 + p < end && !ctrlc(); p++, s++) {
  185 + word = *s;
  186 +
  187 + writew(0xaa, base + 0x555);
  188 + writew(0x55, base + 0xaaa);
  189 + writew(0xa0, base + 0x555);
  190 + writew(word, p);
  191 +
  192 + sync_write_buffer();
  193 +
  194 + /* Wait for completion */
  195 + status1 = readw(p);
  196 + do {
  197 + /* TODO: Timeout */
  198 + status = status1;
  199 + status1 = readw(p);
  200 + } while (((status ^ status1) & 0x40) /* toggled */
  201 + && !(status1 & 0x28)); /* error bits */
  202 +
  203 + /*
  204 + * We'll need to check once again for toggle bit
  205 + * because the toggle bit may stop toggling as I/O5
  206 + * changes to "1" (ref at49bv642.pdf p9)
  207 + */
  208 + status1 = readw(p);
  209 + status = readw(p);
  210 + if ((status ^ status1) & 0x40) {
  211 + printf("Flash write error at address 0x%p: "
  212 + "0x%02x != 0x%02x\n",
  213 + p, status,word);
  214 + ret = ERR_PROG_ERROR;
  215 + writew(0xf0, base);
  216 + readw(base);
  217 + break;
  218 + }
  219 +
  220 + writew(0xf0, base);
  221 + readw(base);
  222 + }
  223 +
  224 + if (flags)
  225 + enable_interrupts();
  226 +
  227 + return ret;
  228 +}
  229 +
  230 +#endif /* CONFIG_FAVR32_EZKIT_EXT_FLASH */
board/earthlcd/favr-32-ezkit/u-boot.lds
Diff comments   View file @ d3c23a7
  1 +/* -*- Fundamental -*-
  2 + *
  3 + * Copyright (C) 2008 Atmel Corporation
  4 + *
  5 + * See file CREDITS for list of people who contributed to this project.
  6 + *
  7 + * This program is free software; you can redistribute it and/or modify it
  8 + * under the terms of the GNU General Public License as published by the Free
  9 + * Software Foundation; either version 2 of the License, or (at your option)
  10 + * any later version.
  11 + *
  12 + * This program is distributed in the hope that it will be useful, but WITHOUT
  13 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15 + * more details.
  16 + *
  17 + * You should have received a copy of the GNU General Public License along with
  18 + * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  19 + * Place, Suite 330, Boston, MA 02111-1307 USA
  20 + */
  21 +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
  22 +OUTPUT_ARCH(avr32)
  23 +ENTRY(_start)
  24 +
  25 +SECTIONS
  26 +{
  27 + . = 0;
  28 + _text = .;
  29 + .text : {
  30 + *(.exception.text)
  31 + *(.text)
  32 + *(.text.*)
  33 + }
  34 + _etext = .;
  35 +
  36 + .rodata : {
  37 + *(.rodata)
  38 + *(.rodata.*)
  39 + }
  40 +
  41 + . = ALIGN(8);
  42 + _data = .;
  43 + .data : {
  44 + *(.data)
  45 + *(.data.*)
  46 + }
  47 +
  48 + . = ALIGN(4);
  49 + __u_boot_cmd_start = .;
  50 + .u_boot_cmd : {
  51 + KEEP(*(.u_boot_cmd))
  52 + }
  53 + __u_boot_cmd_end = .;
  54 +
  55 + . = ALIGN(4);
  56 + _got = .;
  57 + .got : {
  58 + *(.got)
  59 + }
  60 + _egot = .;
  61 +
  62 + . = ALIGN(8);
  63 + _edata = .;
  64 +
  65 + .bss (NOLOAD) : {
  66 + *(.bss)
  67 + *(.bss.*)
  68 + }
  69 + . = ALIGN(8);
  70 + _end = .;
  71 +}
board/mimc/mimc200/Makefile
Diff comments   View file @ d3c23a7
  1 +#
  2 +# Copyright (C) 2005-2006 Atmel Corporation
  3 +#
  4 +# See file CREDITS for list of people who contributed to this project.
  5 +#
  6 +# This program is free software; you can redistribute it and/or
  7 +# modify it under the terms of the GNU General Public License as
  8 +# published by the Free Software Foundation; either version 2 of
  9 +# the License, or (at your option) any later version.
  10 +#
  11 +# This program is distributed in the hope that it will be useful,
  12 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14 +# GNU General Public License for more details.
  15 +#
  16 +# You should have received a copy of the GNU General Public License
  17 +# along with this program; if not, write to the Free Software
  18 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19 +# MA 02111-1307 USA
  20 +
  21 +include $(TOPDIR)/config.mk
  22 +
  23 +LIB := $(obj)lib$(BOARD).a
  24 +
  25 +COBJS := $(BOARD).o
  26 +
  27 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
  28 +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
  29 +
  30 +$(LIB): $(obj).depend $(OBJS)
  31 + $(AR) $(ARFLAGS) $@ $(OBJS)
  32 +
  33 +#########################################################################
  34 +
  35 +# defines $(obj).depend target
  36 +include $(SRCTREE)/rules.mk
  37 +
  38 +sinclude $(obj).depend
  39 +
  40 +#########################################################################
board/mimc/mimc200/config.mk
Diff comments   View file @ d3c23a7
  1 +TEXT_BASE = 0x00000000
  2 +PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
  3 +PLATFORM_LDFLAGS += --gc-sections
board/mimc/mimc200/mimc200.c
Diff comments   View file @ d3c23a7
  1 +/*
  2 + * Copyright (C) 2006 Atmel Corporation
  3 + *
  4 + * See file CREDITS for list of people who contributed to this
  5 + * project.
  6 + *
  7 + * This program is free software; you can redistribute it and/or
  8 + * modify it under the terms of the GNU General Public License as
  9 + * published by the Free Software Foundation; either version 2 of
  10 + * the License, or (at your option) any later version.
  11 + *
  12 + * This program is distributed in the hope that it will be useful,
  13 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * GNU General Public License for more details.
  16 + *
  17 + * You should have received a copy of the GNU General Public License
  18 + * along with this program; if not, write to the Free Software
  19 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 + * MA 02111-1307 USA
  21 + */
  22 +#include <common.h>
  23 +
  24 +#include <asm/io.h>
  25 +#include <asm/sdram.h>
  26 +#include <asm/arch/clk.h>
  27 +#include <asm/arch/gpio.h>
  28 +#include <asm/arch/hmatrix.h>
  29 +#include <lcd.h>
  30 +
  31 +#define SM_PM_GCCTRL 0x0060
  32 +
  33 +DECLARE_GLOBAL_DATA_PTR;
  34 +
  35 +static const struct sdram_config sdram_config = {
  36 + .data_bits = SDRAM_DATA_16BIT,
  37 + .row_bits = 13,
  38 + .col_bits = 9,
  39 + .bank_bits = 2,
  40 + .cas = 3,
  41 + .twr = 2,
  42 + .trc = 6,
  43 + .trp = 2,
  44 + .trcd = 2,
  45 + .tras = 6,
  46 + .txsr = 6,
  47 + /* 15.6 us */
  48 + .refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
  49 +};
  50 +
  51 +int board_early_init_f(void)
  52 +{
  53 + /* Enable SDRAM in the EBI mux */
  54 + hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
  55 +
  56 + gpio_enable_ebi();
  57 + gpio_enable_usart1();
  58 +
  59 + /* enable higher address lines for larger flash devices */
  60 + gpio_select_periph_A(GPIO_PIN_PE16, 0); /* ADDR23 */
  61 + gpio_select_periph_A(GPIO_PIN_PE17, 0); /* ADDR24 */
  62 + gpio_select_periph_A(GPIO_PIN_PE18, 0); /* ADDR25 */
  63 +
  64 + /* enable data flash chip select */
  65 + gpio_select_periph_A(GPIO_PIN_PE25, 0); /* NCS2 */
  66 +
  67 + /* de-assert "force sys reset" pin */
  68 + gpio_set_value(GPIO_PIN_PD15, 1); /* FORCE RESET */
  69 + gpio_select_pio(GPIO_PIN_PD15, GPIOF_OUTPUT);
  70 +
  71 + /* init custom i/o */
  72 + /* cpu type inputs */
  73 + gpio_select_pio(GPIO_PIN_PE19, 0);
  74 + gpio_select_pio(GPIO_PIN_PE20, 0);
  75 + gpio_select_pio(GPIO_PIN_PE23, 0);
  76 + /* main board type inputs */
  77 + gpio_select_pio(GPIO_PIN_PB19, 0);
  78 + gpio_select_pio(GPIO_PIN_PB29, 0);
  79 + /* DEBUG input (use weak pullup) */
  80 + gpio_select_pio(GPIO_PIN_PE21, GPIOF_PULLUP);
  81 +
  82 + /* are we suppressing the console ? */
  83 + if (gpio_get_value(GPIO_PIN_PE21) == 1)
  84 + gd->flags |= GD_FLG_SILENT;
  85 +
  86 + /* reset phys */
  87 + gpio_select_pio(GPIO_PIN_PE24, 0);
  88 + gpio_set_value(GPIO_PIN_PC18, 1); /* PHY RESET */
  89 + gpio_select_pio(GPIO_PIN_PC18, GPIOF_OUTPUT);
  90 +
  91 + /* GCLK0 - 10MHz clock */
  92 + writel(0x00000004, (void *)SM_BASE + SM_PM_GCCTRL);
  93 + gpio_select_periph_A(GPIO_PIN_PA30, 0);
  94 +
  95 + udelay(5000);
  96 +
  97 + /* release phys reset */
  98 + gpio_set_value(GPIO_PIN_PC18, 0); /* PHY RESET (Release) */
  99 +
  100 +#if defined(CONFIG_MACB)
  101 + /* init macb0 pins */
  102 + gpio_select_periph_A(GPIO_PIN_PC3, 0); /* TXD0 */
  103 + gpio_select_periph_A(GPIO_PIN_PC4, 0); /* TXD1 */
  104 + gpio_select_periph_A(GPIO_PIN_PC7, 0); /* TXEN */
  105 + gpio_select_periph_A(GPIO_PIN_PC8, 0); /* TXCK */
  106 + gpio_select_periph_A(GPIO_PIN_PC9, 0); /* RXD0 */
  107 + gpio_select_periph_A(GPIO_PIN_PC10, 0); /* RXD1 */
  108 + gpio_select_periph_A(GPIO_PIN_PC13, 0); /* RXER */
  109 + gpio_select_periph_A(GPIO_PIN_PC15, 0); /* RXDV */
  110 + gpio_select_periph_A(GPIO_PIN_PC16, 0); /* MDC */
  111 + gpio_select_periph_A(GPIO_PIN_PC17, 0); /* MDIO */
  112 +#if !defined(CONFIG_RMII)
  113 + gpio_select_periph_A(GPIO_PIN_PC0, 0); /* COL */
  114 + gpio_select_periph_A(GPIO_PIN_PC1, 0); /* CRS */
  115 + gpio_select_periph_A(GPIO_PIN_PC2, 0); /* TXER */
  116 + gpio_select_periph_A(GPIO_PIN_PC5, 0); /* TXD2 */
  117 + gpio_select_periph_A(GPIO_PIN_PC6, 0); /* TXD3 */
  118 + gpio_select_periph_A(GPIO_PIN_PC11, 0); /* RXD2 */
  119 + gpio_select_periph_A(GPIO_PIN_PC12, 0); /* RXD3 */
  120 + gpio_select_periph_A(GPIO_PIN_PC14, 0); /* RXCK */
  121 +#endif
  122 +
  123 + /* init macb1 pins */
  124 + gpio_select_periph_B(GPIO_PIN_PD13, 0); /* TXD0 */
  125 + gpio_select_periph_B(GPIO_PIN_PD14, 0); /* TXD1 */
  126 + gpio_select_periph_B(GPIO_PIN_PD11, 0); /* TXEN */
  127 + gpio_select_periph_B(GPIO_PIN_PD12, 0); /* TXCK */
  128 + gpio_select_periph_B(GPIO_PIN_PD10, 0); /* RXD0 */
  129 + gpio_select_periph_B(GPIO_PIN_PD6, 0); /* RXD1 */
  130 + gpio_select_periph_B(GPIO_PIN_PD5, 0); /* RXER */
  131 + gpio_select_periph_B(GPIO_PIN_PD4, 0); /* RXDV */
  132 + gpio_select_periph_B(GPIO_PIN_PD3, 0); /* MDC */
  133 + gpio_select_periph_B(GPIO_PIN_PD2, 0); /* MDIO */
  134 +#if !defined(CONFIG_RMII)
  135 + gpio_select_periph_B(GPIO_PIN_PC19, 0); /* COL */
  136 + gpio_select_periph_B(GPIO_PIN_PC23, 0); /* CRS */
  137 + gpio_select_periph_B(GPIO_PIN_PC26, 0); /* TXER */
  138 + gpio_select_periph_B(GPIO_PIN_PC27, 0); /* TXD2 */
  139 + gpio_select_periph_B(GPIO_PIN_PC28, 0); /* TXD3 */
  140 + gpio_select_periph_B(GPIO_PIN_PC29, 0); /* RXD2 */
  141 + gpio_select_periph_B(GPIO_PIN_PC30, 0); /* RXD3 */
  142 + gpio_select_periph_B(GPIO_PIN_PC24, 0); /* RXCK */
  143 +#endif
  144 +#endif
  145 +
  146 +#if defined(CONFIG_MMC)
  147 + gpio_enable_mmci();
  148 +#endif
  149 +
  150 + return 0;
  151 +}
  152 +
  153 +phys_size_t initdram(int board_type)
  154 +{
  155 + unsigned long expected_size;
  156 + unsigned long actual_size;
  157 + void *sdram_base;
  158 +
  159 + sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
  160 +
  161 + expected_size = sdram_init(sdram_base, &sdram_config);
  162 + actual_size = get_ram_size(sdram_base, expected_size);
  163 +
  164 + unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
  165 +
  166 + if (expected_size != actual_size)
  167 + printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
  168 + actual_size >> 20, expected_size >> 20);
  169 +
  170 + return actual_size;
  171 +}
  172 +
  173 +void board_init_info(void)
  174 +{
  175 + gd->bd->bi_phy_id[0] = 0x01;
  176 + gd->bd->bi_phy_id[1] = 0x03;
  177 +}
  178 +
  179 +/* SPI chip select control */
  180 +#ifdef CONFIG_ATMEL_SPI
  181 +#include <spi.h>
  182 +
  183 +int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  184 +{
  185 + return (bus == 0) && (cs == 0);
  186 +}
  187 +
  188 +void spi_cs_activate(struct spi_slave *slave)
  189 +{
  190 +}
  191 +
  192 +void spi_cs_deactivate(struct spi_slave *slave)
  193 +{
  194 +}
  195 +#endif /* CONFIG_ATMEL_SPI */
  196 +
  197 +#ifdef CONFIG_CMD_NET
  198 +extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
  199 +
  200 +int board_eth_init(bd_t *bi)
  201 +{
  202 + macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]);
  203 + macb_eth_initialize(1, (void *)MACB1_BASE, bi->bi_phy_id[1]);
  204 +
  205 + return 0;
  206 +}
  207 +#endif
board/mimc/mimc200/u-boot.lds
Diff comments   View file @ d3c23a7
  1 +/* -*- Fundamental -*-
  2 + *
  3 + * Copyright (C) 2005-2006 Atmel Corporation
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
  24 +OUTPUT_ARCH(avr32)
  25 +ENTRY(_start)
  26 +
  27 +SECTIONS
  28 +{
  29 + . = 0;
  30 + _text = .;
  31 + .text : {
  32 + *(.exception.text)
  33 + *(.text)
  34 + *(.text.*)
  35 + }
  36 + _etext = .;
  37 +
  38 + .rodata : {
  39 + *(.rodata)
  40 + *(.rodata.*)
  41 + }
  42 +
  43 + . = ALIGN(8);
  44 + _data = .;
  45 + .data : {
  46 + *(.data)
  47 + *(.data.*)
  48 + }
  49 +
  50 + . = ALIGN(4);
  51 + __u_boot_cmd_start = .;
  52 + .u_boot_cmd : {
  53 + KEEP(*(.u_boot_cmd))
  54 + }
  55 + __u_boot_cmd_end = .;
  56 +
  57 + . = ALIGN(4);
  58 + _got = .;
  59 + .got : {
  60 + *(.got)
  61 + }
  62 + _egot = .;
  63 +
  64 + . = ALIGN(8);
  65 + _edata = .;
  66 +
  67 + .bss : {
  68 + *(.bss)
  69 + *(.bss.*)
  70 + }
  71 + . = ALIGN(8);
  72 + _end = .;
  73 +}
board/miromico/hammerhead/Makefile
Diff comments   View file @ d3c23a7
  1 +#
  2 +# Copyright (C) 2008 Miromico AG
  3 +#
  4 +# See file CREDITS for list of people who contributed to this project.
  5 +#
  6 +# This program is free software; you can redistribute it and/or
  7 +# modify it under the terms of the GNU General Public License as
  8 +# published by the Free Software Foundation; either version 2 of
  9 +# the License, or (at your option) any later version.
  10 +#
  11 +# This program is distributed in the hope that it will be useful,
  12 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14 +# GNU General Public License for more details.
  15 +#
  16 +# You should have received a copy of the GNU General Public License
  17 +# along with this program; if not, write to the Free Software
  18 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19 +# MA 02111-1307 USA
  20 +
  21 +include $(TOPDIR)/config.mk
  22 +
  23 +LIB := $(obj)lib$(BOARD).a
  24 +
  25 +COBJS := $(BOARD).o
  26 +
  27 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
  28 +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
  29 +
  30 +$(LIB): $(obj).depend $(OBJS)
  31 + $(AR) $(ARFLAGS) $@ $(OBJS)
  32 +
  33 +#########################################################################
  34 +
  35 +# defines $(obj).depend target
  36 +include $(SRCTREE)/rules.mk
  37 +
  38 +sinclude $(obj).depend
  39 +
  40 +#########################################################################
board/miromico/hammerhead/config.mk
Diff comments   View file @ d3c23a7
  1 +TEXT_BASE = 0x00000000
  2 +PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
  3 +PLATFORM_LDFLAGS += --gc-sections
board/miromico/hammerhead/hammerhead.c
Diff comments   View file @ d3c23a7
  1 +/*
  2 + * Copyright (C) 2008 Miromico AG
  3 + *
  4 + * Mostly copied form atmel ATNGW100 sources
  5 + *
  6 + * See file CREDITS for list of people who contributed to this
  7 + * project.
  8 + *
  9 + * This program is free software; you can redistribute it and/or
  10 + * modify it under the terms of the GNU General Public License as
  11 + * published by the Free Software Foundation; either version 2 of
  12 + * the License, or (at your option) any later version.
  13 + *
  14 + * This program is distributed in the hope that it will be useful,
  15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 + * GNU General Public License for more details.
  18 + *
  19 + * You should have received a copy of the GNU General Public License
  20 + * along with this program; if not, write to the Free Software
  21 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 + * MA 02111-1307 USA
  23 + */
  24 +
  25 +#include "../cpu/at32ap/at32ap700x/sm.h"
  26 +
  27 +#include <common.h>
  28 +
  29 +#include <asm/io.h>
  30 +#include <asm/sdram.h>
  31 +#include <asm/arch/clk.h>
  32 +#include <asm/arch/gpio.h>
  33 +#include <asm/arch/hmatrix.h>
  34 +#include <asm/arch/memory-map.h>
  35 +
  36 +DECLARE_GLOBAL_DATA_PTR;
  37 +
  38 +static const struct sdram_config sdram_config = {
  39 + .data_bits = SDRAM_DATA_32BIT,
  40 + .row_bits = 13,
  41 + .col_bits = 9,
  42 + .bank_bits = 2,
  43 + .cas = 3,
  44 + .twr = 2,
  45 + .trc = 7,
  46 + .trp = 2,
  47 + .trcd = 2,
  48 + .tras = 5,
  49 + .txsr = 5,
  50 + /* 7.81 us */
  51 + .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
  52 +};
  53 +
  54 +extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
  55 +
  56 +#ifdef CONFIG_CMD_NET
  57 +int board_eth_init(bd_t *bis)
  58 +{
  59 + return macb_eth_initialize(0, (void *)MACB0_BASE, bis->bi_phy_id[0]);
  60 +}
  61 +#endif
  62 +
  63 +int board_early_init_f(void)
  64 +{
  65 + /* Enable SDRAM in the EBI mux */
  66 + hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
  67 +
  68 + gpio_enable_ebi();
  69 + gpio_enable_usart1();
  70 +
  71 +#if defined(CONFIG_MACB)
  72 + gpio_enable_macb0();
  73 +#endif
  74 +#if defined(CONFIG_MMC)
  75 + gpio_enable_mmci();
  76 +#endif
  77 + return 0;
  78 +}
  79 +
  80 +phys_size_t initdram(int board_type)
  81 +{
  82 + unsigned long expected_size;
  83 + unsigned long actual_size;
  84 + void *sdram_base;
  85 +
  86 + sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
  87 +
  88 + expected_size = sdram_init(sdram_base, &sdram_config);
  89 + actual_size = get_ram_size(sdram_base, expected_size);
  90 +
  91 + unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
  92 +
  93 + if (expected_size != actual_size)
  94 + printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
  95 + actual_size >> 20, expected_size >> 20);
  96 +
  97 + return actual_size;
  98 +}
  99 +
  100 +void board_init_info(void)
  101 +{
  102 + gd->bd->bi_phy_id[0] = 0x01;
  103 +}
  104 +
  105 +void gclk_init(void)
  106 +{
  107 + /* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */
  108 +
  109 + /* Select GCLK3 peripheral function */
  110 + gpio_select_periph_A(GPIO_PIN_PB29, 0);
  111 +
  112 + /* Enable GCLK3 with no input divider, from OSC0 (crystal) */
  113 + sm_writel(PM_GCCTRL(3), SM_BIT(CEN));
  114 +}
board/miromico/hammerhead/u-boot.lds
Diff comments   View file @ d3c23a7
  1 +/* -*- Fundamental -*-
  2 + *
  3 + * Copyright (C) 2005-2006 Atmel Corporation
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
  24 +OUTPUT_ARCH(avr32)
  25 +ENTRY(_start)
  26 +
  27 +SECTIONS
  28 +{
  29 + . = 0;
  30 + _text = .;
  31 + .text : {
  32 + *(.exception.text)
  33 + *(.text)
  34 + *(.text.*)
  35 + }
  36 + _etext = .;
  37 +
  38 + .rodata : {
  39 + *(.rodata)
  40 + *(.rodata.*)
  41 + }
  42 +
  43 + . = ALIGN(8);
  44 + _data = .;
  45 + .data : {
  46 + *(.data)
  47 + *(.data.*)
  48 + }
  49 +
  50 + . = ALIGN(4);
  51 + __u_boot_cmd_start = .;
  52 + .u_boot_cmd : {
  53 + KEEP(*(.u_boot_cmd))
  54 + }
  55 + __u_boot_cmd_end = .;
  56 +
  57 + . = ALIGN(4);
  58 + _got = .;
  59 + .got : {
  60 + *(.got)
  61 + }
  62 + _egot = .;
  63 +
  64 + . = ALIGN(8);
  65 + _edata = .;
  66 +
  67 + .bss : {
  68 + *(.bss)
  69 + *(.bss.*)
  70 + }
  71 + . = ALIGN(8);
  72 + _end = .;
  73 +}
cpu/at32ap/at32ap700x/sm.h
Diff comments   View file @ d3c23a7
... ... @@ -21,7 +21,7 @@
21 21 #define SM_PM_IMR 0x0048
22 22 #define SM_PM_ISR 0x004c
23 23 #define SM_PM_ICR 0x0050
24   -#define SM_PM_GCCTRL 0x0060
  24 +#define SM_PM_GCCTRL(x) (0x0060 + 4 * x)
25 25 #define SM_RTC_CTRL 0x0080
26 26 #define SM_RTC_VAL 0x0084
27 27 #define SM_RTC_TOP 0x0088
... ... @@ -65,6 +65,9 @@
65 65 sysreg_write(EVBA, (unsigned long)&_evba);
66 66 asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET));
67 67  
  68 + if(gclk_init)
  69 + gclk_init();
  70 +
68 71 return 0;
69 72 }
70 73  
include/asm-avr32/arch-at32ap700x/clk.h
Diff comments   View file @ d3c23a7
... ... @@ -82,6 +82,7 @@
82 82 #endif
83 83  
84 84 extern void clk_init(void);
  85 +extern void gclk_init(void) __attribute__((weak));
85 86  
86 87 /* Board code may need the SDRAM base clock as a compile-time constant */
87 88 #define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CFG_CLKDIV_HSB)
include/configs/favr-32-ezkit.h
Diff comments   View file @ d3c23a7
  1 +/*
  2 + * Copyright (C) 2008 Atmel Corporation
  3 + *
  4 + * Configuration settings for the Favr-32 EarthLCD LCD kit.
  5 + *
  6 + * See file CREDITS for list of people who contributed to this project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or modify it
  9 + * under the terms of the GNU General Public License as published by the Free
  10 + * Software Foundation; either version 2 of the License, or (at your option)
  11 + * any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful, but WITHOUT
  14 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  16 + * more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License along with
  19 + * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  20 + * Place, Suite 330, Boston, MA 02111-1307 USA
  21 + */
  22 +#ifndef __CONFIG_H
  23 +#define __CONFIG_H
  24 +
  25 +#include <asm/arch/memory-map.h>
  26 +
  27 +#define CONFIG_AVR32 1
  28 +#define CONFIG_AT32AP 1
  29 +#define CONFIG_AT32AP7000 1
  30 +#define CONFIG_FAVR32_EZKIT 1
  31 +
  32 +#define CONFIG_FAVR32_EZKIT_EXT_FLASH 1
  33 +
  34 +/*
  35 + * Timer clock frequency. We're using the CPU-internal COUNT register
  36 + * for this, so this is equivalent to the CPU core clock frequency
  37 + */
  38 +#define CFG_HZ 1000
  39 +
  40 +/*
  41 + * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
  42 + * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
  43 + * PLL frequency.
  44 + * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz
  45 + */
  46 +#define CONFIG_PLL 1
  47 +#define CFG_POWER_MANAGER 1
  48 +#define CFG_OSC0_HZ 20000000
  49 +#define CFG_PLL0_DIV 1
  50 +#define CFG_PLL0_MUL 7
  51 +#define CFG_PLL0_SUPPRESS_CYCLES 16
  52 +/*
  53 + * Set the CPU running at:
  54 + * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz
  55 + */
  56 +#define CFG_CLKDIV_CPU 0
  57 +/*
  58 + * Set the HSB running at:
  59 + * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz
  60 + */
  61 +#define CFG_CLKDIV_HSB 1
  62 +/*
  63 + * Set the PBA running at:
  64 + * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz
  65 + */
  66 +#define CFG_CLKDIV_PBA 2
  67 +/*
  68 + * Set the PBB running at:
  69 + * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz
  70 + */
  71 +#define CFG_CLKDIV_PBB 1
  72 +
  73 +/*
  74 + * The PLLOPT register controls the PLL like this:
  75 + * icp = PLLOPT<2>
  76 + * ivco = PLLOPT<1:0>
  77 + *
  78 + * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
  79 + */
  80 +#define CFG_PLL0_OPT 0x04
  81 +
  82 +#undef CONFIG_USART0
  83 +#undef CONFIG_USART1
  84 +#undef CONFIG_USART2
  85 +#define CONFIG_USART3 1
  86 +
  87 +/* User serviceable stuff */
  88 +#define CONFIG_DOS_PARTITION 1
  89 +
  90 +#define CONFIG_CMDLINE_TAG 1
  91 +#define CONFIG_SETUP_MEMORY_TAGS 1
  92 +#define CONFIG_INITRD_TAG 1
  93 +
  94 +#define CONFIG_STACKSIZE (2048)
  95 +
  96 +#define CONFIG_BAUDRATE 115200
  97 +#define CONFIG_BOOTARGS \
  98 + "root=/dev/mtdblock1 rootfstype=jffs fbmem=1800k"
  99 +
  100 +#define CONFIG_BOOTCOMMAND \
  101 + "fsload; bootm $(fileaddr)"
  102 +
  103 +/*
  104 + * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
  105 + * data on the serial line may interrupt the boot sequence.
  106 + */
  107 +#define CONFIG_BOOTDELAY 1
  108 +#define CONFIG_AUTOBOOT 1
  109 +#define CONFIG_AUTOBOOT_KEYED 1
  110 +#define CONFIG_AUTOBOOT_PROMPT \
  111 + "Press SPACE to abort autoboot in %d seconds\n", bootdelay
  112 +#define CONFIG_AUTOBOOT_DELAY_STR "d"
  113 +#define CONFIG_AUTOBOOT_STOP_STR " "
  114 +
  115 +/*
  116 + * After booting the board for the first time, new ethernet addresses
  117 + * should be generated and assigned to the environment variables
  118 + * "ethaddr" and "eth1addr". This is normally done during production.
  119 + */
  120 +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
  121 +#define CONFIG_NET_MULTI 1
  122 +
  123 +/*
  124 + * BOOTP options
  125 + */
  126 +#define CONFIG_BOOTP_SUBNETMASK
  127 +#define CONFIG_BOOTP_GATEWAY
  128 +
  129 +
  130 +/*
  131 + * Command line configuration.
  132 + */
  133 +#include <config_cmd_default.h>
  134 +
  135 +#define CONFIG_CMD_ASKENV
  136 +#define CONFIG_CMD_DHCP
  137 +#define CONFIG_CMD_EXT2
  138 +#define CONFIG_CMD_FAT
  139 +#define CONFIG_CMD_JFFS2
  140 +#define CONFIG_CMD_MMC
  141 +
  142 +#undef CONFIG_CMD_AUTOSCRIPT
  143 +#undef CONFIG_CMD_FPGA
  144 +#undef CONFIG_CMD_SETGETDCR
  145 +#undef CONFIG_CMD_XIMG
  146 +
  147 +#define CONFIG_ATMEL_USART 1
  148 +#define CONFIG_MACB 1
  149 +#define CONFIG_PIO2 1
  150 +#define CFG_NR_PIOS 5
  151 +#define CFG_HSDRAMC 1
  152 +#define CONFIG_MMC 1
  153 +#define CONFIG_ATMEL_MCI 1
  154 +
  155 +#define CFG_DCACHE_LINESZ 32
  156 +#define CFG_ICACHE_LINESZ 32
  157 +
  158 +#define CONFIG_NR_DRAM_BANKS 1
  159 +
  160 +/* External flash on Favr-32 */
  161 +#if 0
  162 +#define CFG_FLASH_CFI 1
  163 +#define CFG_FLASH_CFI_DRIVER 1
  164 +#endif
  165 +
  166 +#define CFG_FLASH_BASE 0x00000000
  167 +#define CFG_FLASH_SIZE 0x800000
  168 +#define CFG_MAX_FLASH_BANKS 1
  169 +#define CFG_MAX_FLASH_SECT 135
  170 +
  171 +#define CFG_MONITOR_BASE CFG_FLASH_BASE
  172 +
  173 +#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE
  174 +#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE
  175 +#define CFG_SDRAM_BASE EBI_SDRAM_BASE
  176 +
  177 +#define CFG_ENV_IS_IN_FLASH 1
  178 +#define CFG_ENV_SIZE 65536
  179 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE)
  180 +
  181 +#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
  182 +
  183 +#define CFG_MALLOC_LEN (256*1024)
  184 +#define CFG_DMA_ALLOC_LEN (16384)
  185 +
  186 +/* Allow 4MB for the kernel run-time image */
  187 +#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
  188 +#define CFG_BOOTPARAMS_LEN (16 * 1024)
  189 +
  190 +/* Other configuration settings that shouldn't have to change all that often */
  191 +#define CFG_PROMPT "U-Boot> "
  192 +#define CFG_CBSIZE 256
  193 +#define CFG_MAXARGS 16
  194 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
  195 +#define CFG_LONGHELP 1
  196 +
  197 +#define CFG_MEMTEST_START EBI_SDRAM_BASE
  198 +#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000)
  199 +#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
  200 +
  201 +#endif /* __CONFIG_H */
include/configs/hammerhead.h
Diff comments   View file @ d3c23a7
  1 +/*
  2 + * Copyright (C) 2008 Miromico AG
  3 + *
  4 + * Configuration settings for the Miromico Hammerhead AVR32 board
  5 + *
  6 + * See file CREDITS for list of people who contributed to this
  7 + * project.
  8 + *
  9 + * This program is free software; you can redistribute it and/or
  10 + * modify it under the terms of the GNU General Public License as
  11 + * published by the Free Software Foundation; either version 2 of
  12 + * the License, or (at your option) any later version.
  13 + *
  14 + * This program is distributed in the hope that it will be useful,
  15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 + * GNU General Public License for more details.
  18 + *
  19 + * You should have received a copy of the GNU General Public License
  20 + * along with this program; if not, write to the Free Software
  21 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 + * MA 02111-1307 USA
  23 + */
  24 +#ifndef __CONFIG_H
  25 +#define __CONFIG_H
  26 +
  27 +#define CONFIG_AVR32 1
  28 +#define CONFIG_AT32AP 1
  29 +#define CONFIG_AT32AP7000 1
  30 +#define CONFIG_HAMMERHEAD 1
  31 +
  32 +#define CFG_HZ 1000
  33 +
  34 +/*
  35 + * Set up the PLL to run at 125 MHz, the CPU to run at the PLL
  36 + * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
  37 + * and the PBA bus to run at 1/4 the PLL frequency.
  38 + */
  39 +#define CONFIG_PLL 1
  40 +#define CFG_POWER_MANAGER 1
  41 +#define CFG_OSC0_HZ 25000000
  42 +#define CFG_PLL0_DIV 1
  43 +#define CFG_PLL0_MUL 5
  44 +#define CFG_PLL0_SUPPRESS_CYCLES 16
  45 +#define CFG_CLKDIV_CPU 0
  46 +#define CFG_CLKDIV_HSB 1
  47 +#define CFG_CLKDIV_PBA 2
  48 +#define CFG_CLKDIV_PBB 1
  49 +
  50 +/*
  51 + * The PLLOPT register controls the PLL like this:
  52 + * icp = PLLOPT<2>
  53 + * ivco = PLLOPT<1:0>
  54 + *
  55 + * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
  56 + */
  57 +#define CFG_PLL0_OPT 0x04
  58 +
  59 +#define CONFIG_USART1 1
  60 +
  61 +#define CONFIG_HOSTNAME hammerhead
  62 +
  63 +/* User serviceable stuff */
  64 +#define CONFIG_DOS_PARTITION 1
  65 +
  66 +#define CONFIG_CMDLINE_TAG 1
  67 +#define CONFIG_SETUP_MEMORY_TAGS 1
  68 +#define CONFIG_INITRD_TAG 1
  69 +
  70 +#define CONFIG_STACKSIZE (2048)
  71 +
  72 +#define CONFIG_BAUDRATE 115200
  73 +#define CONFIG_BOOTARGS \
  74 + "console=ttyS0 root=mtd1 rootfstype=jffs2"
  75 +#define CONFIG_BOOTCOMMAND \
  76 + "fsload; bootm"
  77 +
  78 +/*
  79 + * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
  80 + * data on the serial line may interrupt the boot sequence.
  81 + */
  82 +#define CONFIG_BOOTDELAY 1
  83 +#define CONFIG_AUTOBOOT 1
  84 +#define CONFIG_AUTOBOOT_KEYED 1
  85 +#define CONFIG_AUTOBOOT_PROMPT \
  86 + "Press SPACE to abort autoboot in %d seconds\n", bootdelay
  87 +#define CONFIG_AUTOBOOT_DELAY_STR "d"
  88 +#define CONFIG_AUTOBOOT_STOP_STR " "
  89 +
  90 +/*
  91 + * After booting the board for the first time, new ethernet address
  92 + * should be generated and assigned to the environment variables
  93 + * "ethaddr". This is normally done during production.
  94 + */
  95 +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
  96 +#define CONFIG_NET_MULTI 1
  97 +
  98 +/*
  99 + * BOOTP/DHCP options
  100 + */
  101 +#define CONFIG_BOOTP_SUBNETMASK
  102 +#define CONFIG_BOOTP_GATEWAY
  103 +
  104 +/*
  105 + * Command line configuration.
  106 + */
  107 +#include <config_cmd_default.h>
  108 +
  109 +#define CONFIG_CMD_ASKENV
  110 +#define CONFIG_CMD_DHCP
  111 +#define CONFIG_CMD_EXT2
  112 +#define CONFIG_CMD_FAT
  113 +#define CONFIG_CMD_JFFS2
  114 +#define CONFIG_CMD_MMC
  115 +#undef CONFIG_CMD_FPGA
  116 +#undef CONFIG_CMD_SETGETDCR
  117 +
  118 +#define CONFIG_ATMEL_USART 1
  119 +#define CONFIG_MACB 1
  120 +#define CONFIG_PIO2 1
  121 +#define CFG_NR_PIOS 5
  122 +#define CFG_HSDRAMC 1
  123 +#define CONFIG_MMC 1
  124 +#define CONFIG_ATMEL_MCI 1
  125 +
  126 +#define CFG_DCACHE_LINESZ 32
  127 +#define CFG_ICACHE_LINESZ 32
  128 +
  129 +#define CONFIG_NR_DRAM_BANKS 1
  130 +
  131 +#define CFG_FLASH_CFI 1
  132 +#define CFG_FLASH_CFI_DRIVER 1
  133 +
  134 +#define CFG_FLASH_BASE 0x00000000
  135 +#define CFG_FLASH_SIZE 0x800000
  136 +#define CFG_MAX_FLASH_BANKS 1
  137 +#define CFG_MAX_FLASH_SECT 135
  138 +
  139 +#define CFG_MONITOR_BASE CFG_FLASH_BASE
  140 +
  141 +#define CFG_INTRAM_BASE 0x24000000
  142 +#define CFG_INTRAM_SIZE 0x8000
  143 +
  144 +#define CFG_SDRAM_BASE 0x10000000
  145 +
  146 +#define CFG_ENV_IS_IN_FLASH 1
  147 +#define CFG_ENV_SIZE 65536
  148 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE)
  149 +
  150 +#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
  151 +
  152 +#define CFG_MALLOC_LEN (256*1024)
  153 +
  154 +#define CFG_DMA_ALLOC_LEN (16384)
  155 +
  156 +/* Allow 4MB for the kernel run-time image */
  157 +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000)
  158 +#define CFG_BOOTPARAMS_LEN (16 * 1024)
  159 +
  160 +/* Other configuration settings that shouldn't have to change all that often */
  161 +#define CFG_PROMPT "Hammerhead> "
  162 +#define CFG_CBSIZE 256
  163 +#define CFG_MAXARGS 16
  164 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
  165 +#define CFG_LONGHELP 1
  166 +
  167 +#define CFG_MEMTEST_START CFG_SDRAM_BASE
  168 +#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x1f00000)
  169 +
  170 +#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
  171 +
  172 +#endif /* __CONFIG_H */
include/configs/mimc200.h
Diff comments   View file @ d3c23a7
  1 +/*
  2 + * Copyright (C) 2006 Atmel Corporation
  3 + *
  4 + * Configuration settings for the AVR32 Network Gateway
  5 + *
  6 + * See file CREDITS for list of people who contributed to this
  7 + * project.
  8 + *
  9 + * This program is free software; you can redistribute it and/or
  10 + * modify it under the terms of the GNU General Public License as
  11 + * published by the Free Software Foundation; either version 2 of
  12 + * the License, or (at your option) any later version.
  13 + *
  14 + * This program is distributed in the hope that it will be useful,
  15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 + * GNU General Public License for more details.
  18 + *
  19 + * You should have received a copy of the GNU General Public License
  20 + * along with this program; if not, write to the Free Software
  21 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 + * MA 02111-1307 USA
  23 + */
  24 +#ifndef __CONFIG_H
  25 +#define __CONFIG_H
  26 +
  27 +#include <asm/arch/memory-map.h>
  28 +
  29 +#define CONFIG_AVR32 1
  30 +#define CONFIG_AT32AP 1
  31 +#define CONFIG_AT32AP7000 1
  32 +#define CONFIG_MIMC200 1
  33 +
  34 +#define CONFIG_MIMC200_EXT_FLASH 1
  35 +
  36 +#define CFG_HZ 1000
  37 +
  38 +/*
  39 + * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
  40 + * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
  41 + * and the PBA bus to run at 1/4 the PLL frequency.
  42 + */
  43 +#define CONFIG_PLL 1
  44 +#define CFG_POWER_MANAGER 1
  45 +#define CFG_OSC0_HZ 10000000
  46 +#define CFG_PLL0_DIV 1
  47 +#define CFG_PLL0_MUL 15
  48 +#define CFG_PLL0_SUPPRESS_CYCLES 16
  49 +#define CFG_CLKDIV_CPU 0
  50 +#define CFG_CLKDIV_HSB 1
  51 +#define CFG_CLKDIV_PBA 2
  52 +#define CFG_CLKDIV_PBB 1
  53 +
  54 +/*
  55 + * The PLLOPT register controls the PLL like this:
  56 + * icp = PLLOPT<2>
  57 + * ivco = PLLOPT<1:0>
  58 + *
  59 + * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
  60 + */
  61 +#define CFG_PLL0_OPT 0x04
  62 +
  63 +#define CONFIG_USART1 1
  64 +#define CONFIG_MIMC200_DBGLINK 1
  65 +
  66 +/* User serviceable stuff */
  67 +#define CONFIG_DOS_PARTITION 1
  68 +
  69 +#define CONFIG_CMDLINE_TAG 1
  70 +#define CONFIG_SETUP_MEMORY_TAGS 1
  71 +#define CONFIG_INITRD_TAG 1
  72 +
  73 +#define CONFIG_STACKSIZE (2048)
  74 +
  75 +#define CONFIG_BAUDRATE 115200
  76 +#define CONFIG_BOOTARGS \
  77 + "console=ttyS0 root=/dev/mtdblock1 fbmem=600k rootfstype=jffs2"
  78 +#define CONFIG_BOOTCOMMAND \
  79 + "fsload; bootm"
  80 +
  81 +#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
  82 +#define CONFIG_SILENT_CONSOLE_INPUT 1 /* disable console inputs */
  83 +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
  84 +
  85 +/*
  86 + * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
  87 + * data on the serial line may interrupt the boot sequence.
  88 + */
  89 +#define CONFIG_BOOTDELAY 0
  90 +#define CONFIG_ZERO_BOOTDELAY_CHECK 1
  91 +#define CONFIG_AUTOBOOT 1
  92 +
  93 +/*
  94 + * After booting the board for the first time, new ethernet addresses
  95 + * should be generated and assigned to the environment variables
  96 + * "ethaddr" and "eth1addr". This is normally done during production.
  97 + */
  98 +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
  99 +#define CONFIG_NET_MULTI 1
  100 +
  101 +/*
  102 + * BOOTP/DHCP options
  103 + */
  104 +#define CONFIG_BOOTP_SUBNETMASK
  105 +#define CONFIG_BOOTP_GATEWAY
  106 +
  107 +#define CONFIG_DOS_PARTITION 1
  108 +
  109 +/*
  110 + * Command line configuration.
  111 + */
  112 +#include <config_cmd_default.h>
  113 +
  114 +#define CONFIG_CMD_ASKENV
  115 +#define CONFIG_CMD_DHCP
  116 +#define CONFIG_CMD_EXT2
  117 +#define CONFIG_CMD_FAT
  118 +#define CONFIG_CMD_JFFS2
  119 +#define CONFIG_CMD_MMC
  120 +#define CONFIG_CMD_NET
  121 +
  122 +#define CONFIG_ATMEL_USART 1
  123 +#define CONFIG_MACB 1
  124 +#define CONFIG_PIO2 1
  125 +#define CFG_NR_PIOS 5
  126 +#define CFG_HSDRAMC 1
  127 +#define CONFIG_MMC 1
  128 +#define CONFIG_ATMEL_MCI 1
  129 +
  130 +#define CFG_DCACHE_LINESZ 32
  131 +#define CFG_ICACHE_LINESZ 32
  132 +
  133 +#define CONFIG_NR_DRAM_BANKS 1
  134 +
  135 +#define CFG_FLASH_CFI 1
  136 +#define CFG_FLASH_CFI_DRIVER 1
  137 +
  138 +#define CFG_FLASH_BASE 0x00000000
  139 +#define CFG_FLASH_SIZE 0x800000
  140 +#define CFG_MAX_FLASH_BANKS 1
  141 +#define CFG_MAX_FLASH_SECT 135
  142 +
  143 +#define CFG_MONITOR_BASE CFG_FLASH_BASE
  144 +
  145 +#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE
  146 +#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE
  147 +#define CFG_SDRAM_BASE EBI_SDRAM_BASE
  148 +
  149 +#define CFG_FRAM_BASE 0x08000000
  150 +#define CFG_FRAM_SIZE 0x20000
  151 +
  152 +#define CFG_ENV_IS_IN_FLASH 1
  153 +#define CFG_ENV_SIZE 65536
  154 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE)
  155 +
  156 +#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
  157 +
  158 +#define CFG_MALLOC_LEN (1024*1024)
  159 +#define CFG_DMA_ALLOC_LEN (16384)
  160 +
  161 +/* Allow 4MB for the kernel run-time image */
  162 +#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
  163 +#define CFG_BOOTPARAMS_LEN (16 * 1024)
  164 +
  165 +/* Other configuration settings that shouldn't have to change all that often */
  166 +#define CFG_PROMPT "U-Boot> "
  167 +#define CFG_CBSIZE 256
  168 +#define CFG_MAXARGS 16
  169 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
  170 +#define CFG_LONGHELP 1
  171 +
  172 +#define CFG_MEMTEST_START EBI_SDRAM_BASE
  173 +#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x1f00000)
  174 +
  175 +#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
  176 +
  177 +#endif /* __CONFIG_H */
... ... @@ -69,9 +69,7 @@
69 69 extern int npe_initialize(bd_t *);
70 70 extern int uec_initialize(int);
71 71 extern int bfin_EMAC_initialize(bd_t *);
72   -extern int atstk1000_eth_initialize(bd_t *);
73 72 extern int greth_initialize(bd_t *);
74   -extern int atngw100_eth_initialize(bd_t *);
75 73 extern int mcffec_initialize(bd_t*);
76 74 extern int mcdmafec_initialize(bd_t*);
77 75 extern int at91sam9_eth_initialize(bd_t *);
78 76  
... ... @@ -271,14 +269,8 @@
271 269 #if defined(CONFIG_BF537)
272 270 bfin_EMAC_initialize(bis);
273 271 #endif
274   -#if defined(CONFIG_ATSTK1000)
275   - atstk1000_eth_initialize(bis);
276   -#endif
277 272 #if defined(CONFIG_GRETH)
278 273 greth_initialize(bis);
279   -#endif
280   -#if defined(CONFIG_ATNGW100)
281   - atngw100_eth_initialize(bis);
282 274 #endif
283 275 #if defined(CONFIG_MCFFEC)
284 276 mcffec_initialize(bis);