Eric Lee / smarc-uboot | Embedian Git Server

Commit d47c961695dd60ed7e54dc61c16ef3f3173fe3ea

Authored by Liu Ying 2013-12-22 13:02:42 +0800

Committed by Anatolij Gustschin 2014-01-13 06:00:06 +0800

Exists in master and in 50 other branches

video: ipu reg: Correct reserved array size in struct ipu_idmac

The array reserved as a placeholder in the structure ipu_idmac
should contain 44 32bit unsigned integer entries instead of 45
ones, because the placeholder is located bewteen the register
IDMAC_SC_CORD1 and the register IDMAC_CH_BUSY_1 with the address
offsets of 0x804c and 0x8100 respectively.

Reported-by: Robin Gong <b38343@freescale.com>
Acked-by: Robin Gong <b38343@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>

Showing 1 changed file with 1 additions and 1 deletions Inline Diff

drivers/video/ipu_regs.h

drivers/video/ipu_regs.h

Diff comments View file @ d47c961

1	/*	1	/*
2	* Porting to u-boot:	2	* Porting to u-boot:
3	*	3	*
4	* (C) Copyright 2010	4	* (C) Copyright 2010
5	* Stefano Babic, DENX Software Engineering, sbabic@denx.de	5	* Stefano Babic, DENX Software Engineering, sbabic@denx.de
6	*	6	*
7	* Linux IPU driver for MX51:	7	* Linux IPU driver for MX51:
8	*	8	*
9	* (C) Copyright 2005-2009 Freescale Semiconductor, Inc.	9	* (C) Copyright 2005-2009 Freescale Semiconductor, Inc.
10	*	10	*
11	* SPDX-License-Identifier: GPL-2.0+	11	* SPDX-License-Identifier: GPL-2.0+
12	*/	12	*/
13		13
14	#ifndef __IPU_REGS_INCLUDED__	14	#ifndef __IPU_REGS_INCLUDED__
15	#define __IPU_REGS_INCLUDED__	15	#define __IPU_REGS_INCLUDED__
16		16
17	#define IPU_DISP0_BASE 0x00000000	17	#define IPU_DISP0_BASE 0x00000000
18	#define IPU_MCU_T_DEFAULT 8	18	#define IPU_MCU_T_DEFAULT 8
19	#define IPU_DISP1_BASE (IPU_MCU_T_DEFAULT << 25)	19	#define IPU_DISP1_BASE (IPU_MCU_T_DEFAULT << 25)
20	#define IPU_CM_REG_BASE 0x00000000	20	#define IPU_CM_REG_BASE 0x00000000
21	#define IPU_STAT_REG_BASE 0x00000200	21	#define IPU_STAT_REG_BASE 0x00000200
22	#define IPU_IDMAC_REG_BASE 0x00008000	22	#define IPU_IDMAC_REG_BASE 0x00008000
23	#define IPU_ISP_REG_BASE 0x00010000	23	#define IPU_ISP_REG_BASE 0x00010000
24	#define IPU_DP_REG_BASE 0x00018000	24	#define IPU_DP_REG_BASE 0x00018000
25	#define IPU_IC_REG_BASE 0x00020000	25	#define IPU_IC_REG_BASE 0x00020000
26	#define IPU_IRT_REG_BASE 0x00028000	26	#define IPU_IRT_REG_BASE 0x00028000
27	#define IPU_CSI0_REG_BASE 0x00030000	27	#define IPU_CSI0_REG_BASE 0x00030000
28	#define IPU_CSI1_REG_BASE 0x00038000	28	#define IPU_CSI1_REG_BASE 0x00038000
29	#define IPU_DI0_REG_BASE 0x00040000	29	#define IPU_DI0_REG_BASE 0x00040000
30	#define IPU_DI1_REG_BASE 0x00048000	30	#define IPU_DI1_REG_BASE 0x00048000
31	#define IPU_SMFC_REG_BASE 0x00050000	31	#define IPU_SMFC_REG_BASE 0x00050000
32	#define IPU_DC_REG_BASE 0x00058000	32	#define IPU_DC_REG_BASE 0x00058000
33	#define IPU_DMFC_REG_BASE 0x00060000	33	#define IPU_DMFC_REG_BASE 0x00060000
34	#define IPU_VDI_REG_BASE 0x00680000	34	#define IPU_VDI_REG_BASE 0x00680000
35	#if defined(CONFIG_MX51) \|\| defined(CONFIG_MX53)	35	#if defined(CONFIG_MX51) \|\| defined(CONFIG_MX53)
36	#define IPU_CPMEM_REG_BASE 0x01000000	36	#define IPU_CPMEM_REG_BASE 0x01000000
37	#define IPU_LUT_REG_BASE 0x01020000	37	#define IPU_LUT_REG_BASE 0x01020000
38	#define IPU_SRM_REG_BASE 0x01040000	38	#define IPU_SRM_REG_BASE 0x01040000
39	#define IPU_TPM_REG_BASE 0x01060000	39	#define IPU_TPM_REG_BASE 0x01060000
40	#define IPU_DC_TMPL_REG_BASE 0x01080000	40	#define IPU_DC_TMPL_REG_BASE 0x01080000
41	#define IPU_ISP_TBPR_REG_BASE 0x010C0000	41	#define IPU_ISP_TBPR_REG_BASE 0x010C0000
42	#elif defined(CONFIG_MX6)	42	#elif defined(CONFIG_MX6)
43	#define IPU_CPMEM_REG_BASE 0x00100000	43	#define IPU_CPMEM_REG_BASE 0x00100000
44	#define IPU_LUT_REG_BASE 0x00120000	44	#define IPU_LUT_REG_BASE 0x00120000
45	#define IPU_SRM_REG_BASE 0x00140000	45	#define IPU_SRM_REG_BASE 0x00140000
46	#define IPU_TPM_REG_BASE 0x00160000	46	#define IPU_TPM_REG_BASE 0x00160000
47	#define IPU_DC_TMPL_REG_BASE 0x00180000	47	#define IPU_DC_TMPL_REG_BASE 0x00180000
48	#define IPU_ISP_TBPR_REG_BASE 0x001C0000	48	#define IPU_ISP_TBPR_REG_BASE 0x001C0000
49	#endif	49	#endif
50		50
51	#define IPU_CTRL_BASE_ADDR (IPU_SOC_BASE_ADDR + IPU_SOC_OFFSET)	51	#define IPU_CTRL_BASE_ADDR (IPU_SOC_BASE_ADDR + IPU_SOC_OFFSET)
52		52
53	extern u32 *ipu_dc_tmpl_reg;	53	extern u32 *ipu_dc_tmpl_reg;
54		54
55	#define DC_EVT_NF 0	55	#define DC_EVT_NF 0
56	#define DC_EVT_NL 1	56	#define DC_EVT_NL 1
57	#define DC_EVT_EOF 2	57	#define DC_EVT_EOF 2
58	#define DC_EVT_NFIELD 3	58	#define DC_EVT_NFIELD 3
59	#define DC_EVT_EOL 4	59	#define DC_EVT_EOL 4
60	#define DC_EVT_EOFIELD 5	60	#define DC_EVT_EOFIELD 5
61	#define DC_EVT_NEW_ADDR 6	61	#define DC_EVT_NEW_ADDR 6
62	#define DC_EVT_NEW_CHAN 7	62	#define DC_EVT_NEW_CHAN 7
63	#define DC_EVT_NEW_DATA 8	63	#define DC_EVT_NEW_DATA 8
64		64
65	#define DC_EVT_NEW_ADDR_W_0 0	65	#define DC_EVT_NEW_ADDR_W_0 0
66	#define DC_EVT_NEW_ADDR_W_1 1	66	#define DC_EVT_NEW_ADDR_W_1 1
67	#define DC_EVT_NEW_CHAN_W_0 2	67	#define DC_EVT_NEW_CHAN_W_0 2
68	#define DC_EVT_NEW_CHAN_W_1 3	68	#define DC_EVT_NEW_CHAN_W_1 3
69	#define DC_EVT_NEW_DATA_W_0 4	69	#define DC_EVT_NEW_DATA_W_0 4
70	#define DC_EVT_NEW_DATA_W_1 5	70	#define DC_EVT_NEW_DATA_W_1 5
71	#define DC_EVT_NEW_ADDR_R_0 6	71	#define DC_EVT_NEW_ADDR_R_0 6
72	#define DC_EVT_NEW_ADDR_R_1 7	72	#define DC_EVT_NEW_ADDR_R_1 7
73	#define DC_EVT_NEW_CHAN_R_0 8	73	#define DC_EVT_NEW_CHAN_R_0 8
74	#define DC_EVT_NEW_CHAN_R_1 9	74	#define DC_EVT_NEW_CHAN_R_1 9
75	#define DC_EVT_NEW_DATA_R_0 10	75	#define DC_EVT_NEW_DATA_R_0 10
76	#define DC_EVT_NEW_DATA_R_1 11	76	#define DC_EVT_NEW_DATA_R_1 11
77		77
78	/* Software reset for ipu */	78	/* Software reset for ipu */
79	#define SW_IPU_RST 8	79	#define SW_IPU_RST 8
80		80
81	enum {	81	enum {
82	IPU_CONF_DP_EN = 0x00000020,	82	IPU_CONF_DP_EN = 0x00000020,
83	IPU_CONF_DI0_EN = 0x00000040,	83	IPU_CONF_DI0_EN = 0x00000040,
84	IPU_CONF_DI1_EN = 0x00000080,	84	IPU_CONF_DI1_EN = 0x00000080,
85	IPU_CONF_DMFC_EN = 0x00000400,	85	IPU_CONF_DMFC_EN = 0x00000400,
86	IPU_CONF_DC_EN = 0x00000200,	86	IPU_CONF_DC_EN = 0x00000200,
87		87
88	DI0_COUNTER_RELEASE = 0x01000000,	88	DI0_COUNTER_RELEASE = 0x01000000,
89	DI1_COUNTER_RELEASE = 0x02000000,	89	DI1_COUNTER_RELEASE = 0x02000000,
90		90
91	DI_DW_GEN_ACCESS_SIZE_OFFSET = 24,	91	DI_DW_GEN_ACCESS_SIZE_OFFSET = 24,
92	DI_DW_GEN_COMPONENT_SIZE_OFFSET = 16,	92	DI_DW_GEN_COMPONENT_SIZE_OFFSET = 16,
93		93
94	DI_GEN_DI_CLK_EXT = 0x100000,	94	DI_GEN_DI_CLK_EXT = 0x100000,
95	DI_GEN_POLARITY_1 = 0x00000001,	95	DI_GEN_POLARITY_1 = 0x00000001,
96	DI_GEN_POLARITY_2 = 0x00000002,	96	DI_GEN_POLARITY_2 = 0x00000002,
97	DI_GEN_POLARITY_3 = 0x00000004,	97	DI_GEN_POLARITY_3 = 0x00000004,
98	DI_GEN_POLARITY_4 = 0x00000008,	98	DI_GEN_POLARITY_4 = 0x00000008,
99	DI_GEN_POLARITY_5 = 0x00000010,	99	DI_GEN_POLARITY_5 = 0x00000010,
100	DI_GEN_POLARITY_6 = 0x00000020,	100	DI_GEN_POLARITY_6 = 0x00000020,
101	DI_GEN_POLARITY_7 = 0x00000040,	101	DI_GEN_POLARITY_7 = 0x00000040,
102	DI_GEN_POLARITY_8 = 0x00000080,	102	DI_GEN_POLARITY_8 = 0x00000080,
103	DI_GEN_POL_CLK = 0x20000,	103	DI_GEN_POL_CLK = 0x20000,
104		104
105	DI_POL_DRDY_DATA_POLARITY = 0x00000080,	105	DI_POL_DRDY_DATA_POLARITY = 0x00000080,
106	DI_POL_DRDY_POLARITY_15 = 0x00000010,	106	DI_POL_DRDY_POLARITY_15 = 0x00000010,
107	DI_VSYNC_SEL_OFFSET = 13,	107	DI_VSYNC_SEL_OFFSET = 13,
108		108
109	DC_WR_CH_CONF_FIELD_MODE = 0x00000200,	109	DC_WR_CH_CONF_FIELD_MODE = 0x00000200,
110	DC_WR_CH_CONF_PROG_TYPE_OFFSET = 5,	110	DC_WR_CH_CONF_PROG_TYPE_OFFSET = 5,
111	DC_WR_CH_CONF_PROG_TYPE_MASK = 0x000000E0,	111	DC_WR_CH_CONF_PROG_TYPE_MASK = 0x000000E0,
112	DC_WR_CH_CONF_PROG_DI_ID = 0x00000004,	112	DC_WR_CH_CONF_PROG_DI_ID = 0x00000004,
113	DC_WR_CH_CONF_PROG_DISP_ID_OFFSET = 3,	113	DC_WR_CH_CONF_PROG_DISP_ID_OFFSET = 3,
114	DC_WR_CH_CONF_PROG_DISP_ID_MASK = 0x00000018,	114	DC_WR_CH_CONF_PROG_DISP_ID_MASK = 0x00000018,
115		115
116	DP_COM_CONF_FG_EN = 0x00000001,	116	DP_COM_CONF_FG_EN = 0x00000001,
117	DP_COM_CONF_GWSEL = 0x00000002,	117	DP_COM_CONF_GWSEL = 0x00000002,
118	DP_COM_CONF_GWAM = 0x00000004,	118	DP_COM_CONF_GWAM = 0x00000004,
119	DP_COM_CONF_GWCKE = 0x00000008,	119	DP_COM_CONF_GWCKE = 0x00000008,
120	DP_COM_CONF_CSC_DEF_MASK = 0x00000300,	120	DP_COM_CONF_CSC_DEF_MASK = 0x00000300,
121	DP_COM_CONF_CSC_DEF_OFFSET = 8,	121	DP_COM_CONF_CSC_DEF_OFFSET = 8,
122	DP_COM_CONF_CSC_DEF_FG = 0x00000300,	122	DP_COM_CONF_CSC_DEF_FG = 0x00000300,
123	DP_COM_CONF_CSC_DEF_BG = 0x00000200,	123	DP_COM_CONF_CSC_DEF_BG = 0x00000200,
124	DP_COM_CONF_CSC_DEF_BOTH = 0x00000100,	124	DP_COM_CONF_CSC_DEF_BOTH = 0x00000100,
125	DP_COM_CONF_GAMMA_EN = 0x00001000,	125	DP_COM_CONF_GAMMA_EN = 0x00001000,
126	DP_COM_CONF_GAMMA_YUV_EN = 0x00002000,	126	DP_COM_CONF_GAMMA_YUV_EN = 0x00002000,
127	};	127	};
128		128
129	enum di_pins {	129	enum di_pins {
130	DI_PIN11 = 0,	130	DI_PIN11 = 0,
131	DI_PIN12 = 1,	131	DI_PIN12 = 1,
132	DI_PIN13 = 2,	132	DI_PIN13 = 2,
133	DI_PIN14 = 3,	133	DI_PIN14 = 3,
134	DI_PIN15 = 4,	134	DI_PIN15 = 4,
135	DI_PIN16 = 5,	135	DI_PIN16 = 5,
136	DI_PIN17 = 6,	136	DI_PIN17 = 6,
137	DI_PIN_CS = 7,	137	DI_PIN_CS = 7,
138		138
139	DI_PIN_SER_CLK = 0,	139	DI_PIN_SER_CLK = 0,
140	DI_PIN_SER_RS = 1,	140	DI_PIN_SER_RS = 1,
141	};	141	};
142		142
143	enum di_sync_wave {	143	enum di_sync_wave {
144	DI_SYNC_NONE = -1,	144	DI_SYNC_NONE = -1,
145	DI_SYNC_CLK = 0,	145	DI_SYNC_CLK = 0,
146	DI_SYNC_INT_HSYNC = 1,	146	DI_SYNC_INT_HSYNC = 1,
147	DI_SYNC_HSYNC = 2,	147	DI_SYNC_HSYNC = 2,
148	DI_SYNC_VSYNC = 3,	148	DI_SYNC_VSYNC = 3,
149	DI_SYNC_DE = 5,	149	DI_SYNC_DE = 5,
150	};	150	};
151		151
152	struct ipu_cm {	152	struct ipu_cm {
153	u32 conf;	153	u32 conf;
154	u32 sisg_ctrl0;	154	u32 sisg_ctrl0;
155	u32 sisg_ctrl1;	155	u32 sisg_ctrl1;
156	u32 sisg_set[6];	156	u32 sisg_set[6];
157	u32 sisg_clear[6];	157	u32 sisg_clear[6];
158	u32 int_ctrl[15];	158	u32 int_ctrl[15];
159	u32 sdma_event[10];	159	u32 sdma_event[10];
160	u32 srm_pri1;	160	u32 srm_pri1;
161	u32 srm_pri2;	161	u32 srm_pri2;
162	u32 fs_proc_flow[3];	162	u32 fs_proc_flow[3];
163	u32 fs_disp_flow[2];	163	u32 fs_disp_flow[2];
164	u32 skip;	164	u32 skip;
165	u32 disp_alt_conf;	165	u32 disp_alt_conf;
166	u32 disp_gen;	166	u32 disp_gen;
167	u32 disp_alt[4];	167	u32 disp_alt[4];
168	u32 snoop;	168	u32 snoop;
169	u32 mem_rst;	169	u32 mem_rst;
170	u32 pm;	170	u32 pm;
171	u32 gpr;	171	u32 gpr;
172	u32 reserved0[26];	172	u32 reserved0[26];
173	u32 ch_db_mode_sel[2];	173	u32 ch_db_mode_sel[2];
174	u32 reserved1[4];	174	u32 reserved1[4];
175	u32 alt_ch_db_mode_sel[2];	175	u32 alt_ch_db_mode_sel[2];
176	u32 reserved2[2];	176	u32 reserved2[2];
177	u32 ch_trb_mode_sel[2];	177	u32 ch_trb_mode_sel[2];
178	};	178	};
179		179
180	struct ipu_idmac {	180	struct ipu_idmac {
181	u32 conf;	181	u32 conf;
182	u32 ch_en[2];	182	u32 ch_en[2];
183	u32 sep_alpha;	183	u32 sep_alpha;
184	u32 alt_sep_alpha;	184	u32 alt_sep_alpha;
185	u32 ch_pri[2];	185	u32 ch_pri[2];
186	u32 wm_en[2];	186	u32 wm_en[2];
187	u32 lock_en[2];	187	u32 lock_en[2];
188	u32 sub_addr[5];	188	u32 sub_addr[5];
189	u32 bndm_en[2];	189	u32 bndm_en[2];
190	u32 sc_cord[2];	190	u32 sc_cord[2];
191	u32 reserved[45];	191	u32 reserved[44];
192	u32 ch_busy[2];	192	u32 ch_busy[2];
193	};	193	};
194		194
195	struct ipu_com_async {	195	struct ipu_com_async {
196	u32 com_conf_async;	196	u32 com_conf_async;
197	u32 graph_wind_ctrl_async;	197	u32 graph_wind_ctrl_async;
198	u32 fg_pos_async;	198	u32 fg_pos_async;
199	u32 cur_pos_async;	199	u32 cur_pos_async;
200	u32 cur_map_async;	200	u32 cur_map_async;
201	u32 gamma_c_async[8];	201	u32 gamma_c_async[8];
202	u32 gamma_s_async[4];	202	u32 gamma_s_async[4];
203	u32 dp_csca_async[4];	203	u32 dp_csca_async[4];
204	u32 dp_csc_async[2];	204	u32 dp_csc_async[2];
205	};	205	};
206		206
207	struct ipu_dp {	207	struct ipu_dp {
208	u32 com_conf_sync;	208	u32 com_conf_sync;
209	u32 graph_wind_ctrl_sync;	209	u32 graph_wind_ctrl_sync;
210	u32 fg_pos_sync;	210	u32 fg_pos_sync;
211	u32 cur_pos_sync;	211	u32 cur_pos_sync;
212	u32 cur_map_sync;	212	u32 cur_map_sync;
213	u32 gamma_c_sync[8];	213	u32 gamma_c_sync[8];
214	u32 gamma_s_sync[4];	214	u32 gamma_s_sync[4];
215	u32 csca_sync[4];	215	u32 csca_sync[4];
216	u32 csc_sync[2];	216	u32 csc_sync[2];
217	u32 cur_pos_alt;	217	u32 cur_pos_alt;
218	struct ipu_com_async async[2];	218	struct ipu_com_async async[2];
219	};	219	};
220		220
221	struct ipu_di {	221	struct ipu_di {
222	u32 general;	222	u32 general;
223	u32 bs_clkgen0;	223	u32 bs_clkgen0;
224	u32 bs_clkgen1;	224	u32 bs_clkgen1;
225	u32 sw_gen0[9];	225	u32 sw_gen0[9];
226	u32 sw_gen1[9];	226	u32 sw_gen1[9];
227	u32 sync_as;	227	u32 sync_as;
228	u32 dw_gen[12];	228	u32 dw_gen[12];
229	u32 dw_set[48];	229	u32 dw_set[48];
230	u32 stp_rep[4];	230	u32 stp_rep[4];
231	u32 stp_rep9;	231	u32 stp_rep9;
232	u32 ser_conf;	232	u32 ser_conf;
233	u32 ssc;	233	u32 ssc;
234	u32 pol;	234	u32 pol;
235	u32 aw0;	235	u32 aw0;
236	u32 aw1;	236	u32 aw1;
237	u32 scr_conf;	237	u32 scr_conf;
238	u32 stat;	238	u32 stat;
239	};	239	};
240		240
241	struct ipu_stat {	241	struct ipu_stat {
242	u32 int_stat[15];	242	u32 int_stat[15];
243	u32 cur_buf[2];	243	u32 cur_buf[2];
244	u32 alt_cur_buf_0;	244	u32 alt_cur_buf_0;
245	u32 alt_cur_buf_1;	245	u32 alt_cur_buf_1;
246	u32 srm_stat;	246	u32 srm_stat;
247	u32 proc_task_stat;	247	u32 proc_task_stat;
248	u32 disp_task_stat;	248	u32 disp_task_stat;
249	u32 triple_cur_buf[4];	249	u32 triple_cur_buf[4];
250	u32 ch_buf0_rdy[2];	250	u32 ch_buf0_rdy[2];
251	u32 ch_buf1_rdy[2];	251	u32 ch_buf1_rdy[2];
252	u32 alt_ch_buf0_rdy[2];	252	u32 alt_ch_buf0_rdy[2];
253	u32 alt_ch_buf1_rdy[2];	253	u32 alt_ch_buf1_rdy[2];
254	u32 ch_buf2_rdy[2];	254	u32 ch_buf2_rdy[2];
255	};	255	};
256		256
257	struct ipu_dc_ch {	257	struct ipu_dc_ch {
258	u32 wr_ch_conf;	258	u32 wr_ch_conf;
259	u32 wr_ch_addr;	259	u32 wr_ch_addr;
260	u32 rl[5];	260	u32 rl[5];
261	};	261	};
262		262
263	struct ipu_dc {	263	struct ipu_dc {
264	struct ipu_dc_ch dc_ch0_1_2[3];	264	struct ipu_dc_ch dc_ch0_1_2[3];
265	u32 cmd_ch_conf_3;	265	u32 cmd_ch_conf_3;
266	u32 cmd_ch_conf_4;	266	u32 cmd_ch_conf_4;
267	struct ipu_dc_ch dc_ch5_6[2];	267	struct ipu_dc_ch dc_ch5_6[2];
268	struct ipu_dc_ch dc_ch8;	268	struct ipu_dc_ch dc_ch8;
269	u32 rl6_ch_8;	269	u32 rl6_ch_8;
270	struct ipu_dc_ch dc_ch9;	270	struct ipu_dc_ch dc_ch9;
271	u32 rl6_ch_9;	271	u32 rl6_ch_9;
272	u32 gen;	272	u32 gen;
273	u32 disp_conf1[4];	273	u32 disp_conf1[4];
274	u32 disp_conf2[4];	274	u32 disp_conf2[4];
275	u32 di0_conf[2];	275	u32 di0_conf[2];
276	u32 di1_conf[2];	276	u32 di1_conf[2];
277	u32 dc_map_ptr[15];	277	u32 dc_map_ptr[15];
278	u32 dc_map_val[12];	278	u32 dc_map_val[12];
279	u32 udge[16];	279	u32 udge[16];
280	u32 lla[2];	280	u32 lla[2];
281	u32 r_lla[2];	281	u32 r_lla[2];
282	u32 wr_ch_addr_5_alt;	282	u32 wr_ch_addr_5_alt;
283	u32 stat;	283	u32 stat;
284	};	284	};
285		285
286	struct ipu_dmfc {	286	struct ipu_dmfc {
287	u32 rd_chan;	287	u32 rd_chan;
288	u32 wr_chan;	288	u32 wr_chan;
289	u32 wr_chan_def;	289	u32 wr_chan_def;
290	u32 dp_chan;	290	u32 dp_chan;
291	u32 dp_chan_def;	291	u32 dp_chan_def;
292	u32 general[2];	292	u32 general[2];
293	u32 ic_ctrl;	293	u32 ic_ctrl;
294	u32 wr_chan_alt;	294	u32 wr_chan_alt;
295	u32 wr_chan_def_alt;	295	u32 wr_chan_def_alt;
296	u32 general1_alt;	296	u32 general1_alt;
297	u32 stat;	297	u32 stat;
298	};	298	};
299		299
300	#define IPU_CM_REG ((struct ipu_cm *)(IPU_CTRL_BASE_ADDR + \	300	#define IPU_CM_REG ((struct ipu_cm *)(IPU_CTRL_BASE_ADDR + \
301	IPU_CM_REG_BASE))	301	IPU_CM_REG_BASE))
302	#define IPU_CONF (&IPU_CM_REG->conf)	302	#define IPU_CONF (&IPU_CM_REG->conf)
303	#define IPU_SRM_PRI1 (&IPU_CM_REG->srm_pri1)	303	#define IPU_SRM_PRI1 (&IPU_CM_REG->srm_pri1)
304	#define IPU_SRM_PRI2 (&IPU_CM_REG->srm_pri2)	304	#define IPU_SRM_PRI2 (&IPU_CM_REG->srm_pri2)
305	#define IPU_FS_PROC_FLOW1 (&IPU_CM_REG->fs_proc_flow[0])	305	#define IPU_FS_PROC_FLOW1 (&IPU_CM_REG->fs_proc_flow[0])
306	#define IPU_FS_PROC_FLOW2 (&IPU_CM_REG->fs_proc_flow[1])	306	#define IPU_FS_PROC_FLOW2 (&IPU_CM_REG->fs_proc_flow[1])
307	#define IPU_FS_PROC_FLOW3 (&IPU_CM_REG->fs_proc_flow[2])	307	#define IPU_FS_PROC_FLOW3 (&IPU_CM_REG->fs_proc_flow[2])
308	#define IPU_FS_DISP_FLOW1 (&IPU_CM_REG->fs_disp_flow[0])	308	#define IPU_FS_DISP_FLOW1 (&IPU_CM_REG->fs_disp_flow[0])
309	#define IPU_DISP_GEN (&IPU_CM_REG->disp_gen)	309	#define IPU_DISP_GEN (&IPU_CM_REG->disp_gen)
310	#define IPU_MEM_RST (&IPU_CM_REG->mem_rst)	310	#define IPU_MEM_RST (&IPU_CM_REG->mem_rst)
311	#define IPU_GPR (&IPU_CM_REG->gpr)	311	#define IPU_GPR (&IPU_CM_REG->gpr)
312	#define IPU_CHA_DB_MODE_SEL(ch) (&IPU_CM_REG->ch_db_mode_sel[ch / 32])	312	#define IPU_CHA_DB_MODE_SEL(ch) (&IPU_CM_REG->ch_db_mode_sel[ch / 32])
313		313
314	#define IPU_STAT ((struct ipu_stat *)(IPU_CTRL_BASE_ADDR + \	314	#define IPU_STAT ((struct ipu_stat *)(IPU_CTRL_BASE_ADDR + \
315	IPU_STAT_REG_BASE))	315	IPU_STAT_REG_BASE))
316	#define IPU_CHA_CUR_BUF(ch) (&IPU_STAT->cur_buf[ch / 32])	316	#define IPU_CHA_CUR_BUF(ch) (&IPU_STAT->cur_buf[ch / 32])
317	#define IPU_CHA_BUF0_RDY(ch) (&IPU_STAT->ch_buf0_rdy[ch / 32])	317	#define IPU_CHA_BUF0_RDY(ch) (&IPU_STAT->ch_buf0_rdy[ch / 32])
318	#define IPU_CHA_BUF1_RDY(ch) (&IPU_STAT->ch_buf1_rdy[ch / 32])	318	#define IPU_CHA_BUF1_RDY(ch) (&IPU_STAT->ch_buf1_rdy[ch / 32])
319		319
320	#define IPU_INT_CTRL(n) (&IPU_CM_REG->int_ctrl[(n) - 1])	320	#define IPU_INT_CTRL(n) (&IPU_CM_REG->int_ctrl[(n) - 1])
321		321
322	#define IDMAC_REG ((struct ipu_idmac *)(IPU_CTRL_BASE_ADDR + \	322	#define IDMAC_REG ((struct ipu_idmac *)(IPU_CTRL_BASE_ADDR + \
323	IPU_IDMAC_REG_BASE))	323	IPU_IDMAC_REG_BASE))
324	#define IDMAC_CONF (&IDMAC_REG->conf)	324	#define IDMAC_CONF (&IDMAC_REG->conf)
325	#define IDMAC_CHA_EN(ch) (&IDMAC_REG->ch_en[ch / 32])	325	#define IDMAC_CHA_EN(ch) (&IDMAC_REG->ch_en[ch / 32])
326	#define IDMAC_CHA_PRI(ch) (&IDMAC_REG->ch_pri[ch / 32])	326	#define IDMAC_CHA_PRI(ch) (&IDMAC_REG->ch_pri[ch / 32])
327		327
328	#define DI_REG(di) ((struct ipu_di *)(IPU_CTRL_BASE_ADDR + \	328	#define DI_REG(di) ((struct ipu_di *)(IPU_CTRL_BASE_ADDR + \
329	((di == 1) ? IPU_DI1_REG_BASE : \	329	((di == 1) ? IPU_DI1_REG_BASE : \
330	IPU_DI0_REG_BASE)))	330	IPU_DI0_REG_BASE)))
331	#define DI_GENERAL(di) (&DI_REG(di)->general)	331	#define DI_GENERAL(di) (&DI_REG(di)->general)
332	#define DI_BS_CLKGEN0(di) (&DI_REG(di)->bs_clkgen0)	332	#define DI_BS_CLKGEN0(di) (&DI_REG(di)->bs_clkgen0)
333	#define DI_BS_CLKGEN1(di) (&DI_REG(di)->bs_clkgen1)	333	#define DI_BS_CLKGEN1(di) (&DI_REG(di)->bs_clkgen1)
334		334
335	#define DI_SW_GEN0(di, gen) (&DI_REG(di)->sw_gen0[gen - 1])	335	#define DI_SW_GEN0(di, gen) (&DI_REG(di)->sw_gen0[gen - 1])
336	#define DI_SW_GEN1(di, gen) (&DI_REG(di)->sw_gen1[gen - 1])	336	#define DI_SW_GEN1(di, gen) (&DI_REG(di)->sw_gen1[gen - 1])
337	#define DI_STP_REP(di, gen) (&DI_REG(di)->stp_rep[(gen - 1) / 2])	337	#define DI_STP_REP(di, gen) (&DI_REG(di)->stp_rep[(gen - 1) / 2])
338	#define DI_SYNC_AS_GEN(di) (&DI_REG(di)->sync_as)	338	#define DI_SYNC_AS_GEN(di) (&DI_REG(di)->sync_as)
339	#define DI_DW_GEN(di, gen) (&DI_REG(di)->dw_gen[gen])	339	#define DI_DW_GEN(di, gen) (&DI_REG(di)->dw_gen[gen])
340	#define DI_DW_SET(di, gen, set) (&DI_REG(di)->dw_set[gen + 12 * set])	340	#define DI_DW_SET(di, gen, set) (&DI_REG(di)->dw_set[gen + 12 * set])
341	#define DI_POL(di) (&DI_REG(di)->pol)	341	#define DI_POL(di) (&DI_REG(di)->pol)
342	#define DI_SCR_CONF(di) (&DI_REG(di)->scr_conf)	342	#define DI_SCR_CONF(di) (&DI_REG(di)->scr_conf)
343		343
344	#define DMFC_REG ((struct ipu_dmfc *)(IPU_CTRL_BASE_ADDR + \	344	#define DMFC_REG ((struct ipu_dmfc *)(IPU_CTRL_BASE_ADDR + \
345	IPU_DMFC_REG_BASE))	345	IPU_DMFC_REG_BASE))
346	#define DMFC_WR_CHAN (&DMFC_REG->wr_chan)	346	#define DMFC_WR_CHAN (&DMFC_REG->wr_chan)
347	#define DMFC_WR_CHAN_DEF (&DMFC_REG->wr_chan_def)	347	#define DMFC_WR_CHAN_DEF (&DMFC_REG->wr_chan_def)
348	#define DMFC_DP_CHAN (&DMFC_REG->dp_chan)	348	#define DMFC_DP_CHAN (&DMFC_REG->dp_chan)
349	#define DMFC_DP_CHAN_DEF (&DMFC_REG->dp_chan_def)	349	#define DMFC_DP_CHAN_DEF (&DMFC_REG->dp_chan_def)
350	#define DMFC_GENERAL1 (&DMFC_REG->general[0])	350	#define DMFC_GENERAL1 (&DMFC_REG->general[0])
351	#define DMFC_IC_CTRL (&DMFC_REG->ic_ctrl)	351	#define DMFC_IC_CTRL (&DMFC_REG->ic_ctrl)
352		352
353		353
354	#define DC_REG ((struct ipu_dc *)(IPU_CTRL_BASE_ADDR + \	354	#define DC_REG ((struct ipu_dc *)(IPU_CTRL_BASE_ADDR + \
355	IPU_DC_REG_BASE))	355	IPU_DC_REG_BASE))
356	#define DC_MAP_CONF_PTR(n) (&DC_REG->dc_map_ptr[n / 2])	356	#define DC_MAP_CONF_PTR(n) (&DC_REG->dc_map_ptr[n / 2])
357	#define DC_MAP_CONF_VAL(n) (&DC_REG->dc_map_val[n / 2])	357	#define DC_MAP_CONF_VAL(n) (&DC_REG->dc_map_val[n / 2])
358		358
359		359
360	static inline struct ipu_dc_ch *dc_ch_offset(int ch)	360	static inline struct ipu_dc_ch *dc_ch_offset(int ch)
361	{	361	{
362	switch (ch) {	362	switch (ch) {
363	case 0:	363	case 0:
364	case 1:	364	case 1:
365	case 2:	365	case 2:
366	return &DC_REG->dc_ch0_1_2[ch];	366	return &DC_REG->dc_ch0_1_2[ch];
367	case 5:	367	case 5:
368	case 6:	368	case 6:
369	return &DC_REG->dc_ch5_6[ch - 5];	369	return &DC_REG->dc_ch5_6[ch - 5];
370	case 8:	370	case 8:
371	return &DC_REG->dc_ch8;	371	return &DC_REG->dc_ch8;
372	case 9:	372	case 9:
373	return &DC_REG->dc_ch9;	373	return &DC_REG->dc_ch9;
374	default:	374	default:
375	printf("%s: invalid channel %d\n", __func__, ch);	375	printf("%s: invalid channel %d\n", __func__, ch);
376	return NULL;	376	return NULL;
377	}	377	}
378		378
379	}	379	}
380		380
381	#define DC_RL_CH(ch, evt) (&dc_ch_offset(ch)->rl[evt / 2])	381	#define DC_RL_CH(ch, evt) (&dc_ch_offset(ch)->rl[evt / 2])
382		382
383	#define DC_WR_CH_CONF(ch) (&dc_ch_offset(ch)->wr_ch_conf)	383	#define DC_WR_CH_CONF(ch) (&dc_ch_offset(ch)->wr_ch_conf)
384	#define DC_WR_CH_ADDR(ch) (&dc_ch_offset(ch)->wr_ch_addr)	384	#define DC_WR_CH_ADDR(ch) (&dc_ch_offset(ch)->wr_ch_addr)
385		385
386	#define DC_WR_CH_CONF_1 DC_WR_CH_CONF(1)	386	#define DC_WR_CH_CONF_1 DC_WR_CH_CONF(1)
387	#define DC_WR_CH_CONF_5 DC_WR_CH_CONF(5)	387	#define DC_WR_CH_CONF_5 DC_WR_CH_CONF(5)
388		388
389	#define DC_GEN (&DC_REG->gen)	389	#define DC_GEN (&DC_REG->gen)
390	#define DC_DISP_CONF2(disp) (&DC_REG->disp_conf2[disp])	390	#define DC_DISP_CONF2(disp) (&DC_REG->disp_conf2[disp])
391	#define DC_STAT (&DC_REG->stat)	391	#define DC_STAT (&DC_REG->stat)
392		392
393	#define DP_SYNC 0	393	#define DP_SYNC 0
394	#define DP_ASYNC0 0x60	394	#define DP_ASYNC0 0x60
395	#define DP_ASYNC1 0xBC	395	#define DP_ASYNC1 0xBC
396		396
397	#define DP_REG ((struct ipu_dp *)(IPU_CTRL_BASE_ADDR + \	397	#define DP_REG ((struct ipu_dp *)(IPU_CTRL_BASE_ADDR + \
398	IPU_DP_REG_BASE))	398	IPU_DP_REG_BASE))
399	#define DP_COM_CONF() (&DP_REG->com_conf_sync)	399	#define DP_COM_CONF() (&DP_REG->com_conf_sync)
400	#define DP_GRAPH_WIND_CTRL() (&DP_REG->graph_wind_ctrl_sync)	400	#define DP_GRAPH_WIND_CTRL() (&DP_REG->graph_wind_ctrl_sync)
401	#define DP_CSC_A_0() (&DP_REG->csca_sync[0])	401	#define DP_CSC_A_0() (&DP_REG->csca_sync[0])
402	#define DP_CSC_A_1() (&DP_REG->csca_sync[1])	402	#define DP_CSC_A_1() (&DP_REG->csca_sync[1])
403	#define DP_CSC_A_2() (&DP_REG->csca_sync[2])	403	#define DP_CSC_A_2() (&DP_REG->csca_sync[2])
404	#define DP_CSC_A_3() (&DP_REG->csca_sync[3])	404	#define DP_CSC_A_3() (&DP_REG->csca_sync[3])
405		405
406	#define DP_CSC_0() (&DP_REG->csc_sync[0])	406	#define DP_CSC_0() (&DP_REG->csc_sync[0])
407	#define DP_CSC_1() (&DP_REG->csc_sync[1])	407	#define DP_CSC_1() (&DP_REG->csc_sync[1])
408		408
409	/* DC template opcodes */	409	/* DC template opcodes */
410	#define WROD(lf) (0x18 \| (lf << 1))	410	#define WROD(lf) (0x18 \| (lf << 1))
411		411
412	#endif	412	#endif
413		413