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Commit d481c80d78f954133c035dae6c7d22de3625795d

Authored by Jean-Christophe PLAGNIOL-VILLARD
1 parent 4e170b1662
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

at91rm9200: rename lowlevel init value to CONFIG_SYS_ 

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Showing 6 changed files with 203 additions and 203 deletions Inline Diff

board/m501sk/memsetup.S
Diff comments   View file @ d481c80
1 /* 1 /*
2 * Memory Setup stuff - taken from blob memsetup.S 2 * Memory Setup stuff - taken from blob memsetup.S
3 * 3 *
4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and 4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
5 * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) 5 * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
6 * 6 *
7 * Modified for the at91rm9200dk board by 7 * Modified for the at91rm9200dk board by
8 * (C) Copyright 2004 8 * (C) Copyright 2004
9 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> 9 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
10 * 10 *
11 * See file CREDITS for list of people who contributed to this 11 * See file CREDITS for list of people who contributed to this
12 * project. 12 * project.
13 * 13 *
14 * This program is free software; you can redistribute it and/or 14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as 15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of 16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version. 17 * the License, or (at your option) any later version.
18 * 18 *
19 * This program is distributed in the hope that it will be useful, 19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details. 22 * GNU General Public License for more details.
23 * 23 *
24 * You should have received a copy of the GNU General Public License 24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software 25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA 27 * MA 02111-1307 USA
28 */ 28 */
29 29
30 #include <config.h> 30 #include <config.h>
31 #include <version.h> 31 #include <version.h>
32 32
33 #ifdef CONFIG_BOOTBINFUNC 33 #ifdef CONFIG_BOOTBINFUNC
34 /* 34 /*
35 * some parameters for the board 35 * some parameters for the board
36 * 36 *
37 * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in 37 * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
38 * turn is based on the boot.bin code from ATMEL 38 * turn is based on the boot.bin code from ATMEL
39 * 39 *
40 */ 40 */
41 41
42 /* flash */ 42 /* flash */
43 #define MC_PUIA 0xFFFFFF10 43 #define MC_PUIA 0xFFFFFF10
44 #define MC_PUIA_VAL 0x00000000 44 #define CONFIG_SYS_MC_PUIA_VAL 0x00000000
45 #define MC_PUP 0xFFFFFF50 45 #define MC_PUP 0xFFFFFF50
46 #define MC_PUP_VAL 0x00000000 46 #define CONFIG_SYS_MC_PUP_VAL 0x00000000
47 #define MC_PUER 0xFFFFFF54 47 #define MC_PUER 0xFFFFFF54
48 #define MC_PUER_VAL 0x00000000 48 #define CONFIG_SYS_MC_PUER_VAL 0x00000000
49 #define MC_ASR 0xFFFFFF04 49 #define MC_ASR 0xFFFFFF04
50 #define MC_ASR_VAL 0x00000000 50 #define CONFIG_SYS_MC_ASR_VAL 0x00000000
51 #define MC_AASR 0xFFFFFF08 51 #define MC_AASR 0xFFFFFF08
52 #define MC_AASR_VAL 0x00000000 52 #define CONFIG_SYS_MC_AASR_VAL 0x00000000
53 #define EBI_CFGR 0xFFFFFF64 53 #define EBI_CFGR 0xFFFFFF64
54 #define EBI_CFGR_VAL 0x00000000 54 #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
55 #define SMC_CSR0 0xFFFFFF70 55 #define SMC_CSR0 0xFFFFFF70
56 #define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ 56 #define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
57 57
58 /* clocks */ 58 /* clocks */
59 #define PLLAR 0xFFFFFC28 59 #define PLLAR 0xFFFFFC28
60 #define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ 60 #define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
61 #define PLLBR 0xFFFFFC2C 61 #define PLLBR 0xFFFFFC2C
62 #define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ 62 #define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
63 #define MCKR 0xFFFFFC30 63 #define MCKR 0xFFFFFC30
64 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ 64 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
65 #define MCKR_VAL 0x00000202 65 #define CONFIG_SYS_MCKR_VAL 0x00000202
66 66
67 /* sdram */ 67 /* sdram */
68 #define PIOC_ASR 0xFFFFF870 68 #define PIOC_ASR 0xFFFFF870
69 #define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as Perip (D16/D31) */ 69 #define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as Perip (D16/D31) */
70 #define PIOC_BSR 0xFFFFF874 70 #define PIOC_BSR 0xFFFFF874
71 #define PIOC_BSR_VAL 0x00000000 71 #define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
72 #define PIOC_PDR 0xFFFFF804 72 #define PIOC_PDR 0xFFFFF804
73 #define PIOC_PDR_VAL 0xFFFF0000 73 #define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
74 #define EBI_CSA 0xFFFFFF60 74 #define EBI_CSA 0xFFFFFF60
75 #define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ 75 #define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
76 #define SDRC_CR 0xFFFFFF98 76 #define SDRC_CR 0xFFFFFF98
77 #define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */ 77 #define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
78 #define SDRAM 0x20000000 /* address of the SDRAM */ 78 #define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
79 #define SDRAM1 0x20000080 /* address of the SDRAM */ 79 #define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */
80 #define SDRAM_VAL 0x00000000 /* value written to SDRAM */ 80 #define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
81 #define SDRC_MR 0xFFFFFF90 81 #define SDRC_MR 0xFFFFFF90
82 #define SDRC_MR_VAL 0x00000002 /* Precharge All */ 82 #define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
83 #define SDRC_MR_VAL1 0x00000004 /* refresh */ 83 #define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
84 #define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ 84 #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
85 #define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ 85 #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
86 #define SDRC_TR 0xFFFFFF94 86 #define SDRC_TR 0xFFFFFF94
87 #define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ 87 #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
88 88
89 _TEXT_BASE: 89 _TEXT_BASE:
90 .word TEXT_BASE 90 .word TEXT_BASE
91 91
92 .globl lowlevelinit 92 .globl lowlevelinit
93 lowlevelinit: 93 lowlevelinit:
94 /* memory control configuration */ 94 /* memory control configuration */
95 /* this isn't very elegant, but what the heck */ 95 /* this isn't very elegant, but what the heck */
96 ldr r0, =SMRDATA 96 ldr r0, =SMRDATA
97 ldr r1, _TEXT_BASE 97 ldr r1, _TEXT_BASE
98 sub r0, r0, r1 98 sub r0, r0, r1
99 add r2, r0, #80 99 add r2, r0, #80
100 0: 100 0:
101 /* the address */ 101 /* the address */
102 ldr r1, [r0], #4 102 ldr r1, [r0], #4
103 /* the value */ 103 /* the value */
104 ldr r3, [r0], #4 104 ldr r3, [r0], #4
105 str r3, [r1] 105 str r3, [r1]
106 cmp r2, r0 106 cmp r2, r0
107 bne 0b 107 bne 0b
108 /* delay - this is all done by guess */ 108 /* delay - this is all done by guess */
109 ldr r0, =0x00010000 109 ldr r0, =0x00010000
110 1: 110 1:
111 subs r0, r0, #1 111 subs r0, r0, #1
112 bhi 1b 112 bhi 1b
113 ldr r0, =SMRDATA1 113 ldr r0, =SMRDATA1
114 ldr r1, _TEXT_BASE 114 ldr r1, _TEXT_BASE
115 sub r0, r0, r1 115 sub r0, r0, r1
116 add r2, r0, #176 116 add r2, r0, #176
117 2: 117 2:
118 /* the address */ 118 /* the address */
119 ldr r1, [r0], #4 119 ldr r1, [r0], #4
120 /* the value */ 120 /* the value */
121 ldr r3, [r0], #4 121 ldr r3, [r0], #4
122 str r3, [r1] 122 str r3, [r1]
123 cmp r2, r0 123 cmp r2, r0
124 bne 2b 124 bne 2b
125 125
126 /* everything is fine now */ 126 /* everything is fine now */
127 mov pc, lr 127 mov pc, lr
128 128
129 .ltorg 129 .ltorg
130 130
131 SMRDATA: 131 SMRDATA:
132 .word MC_PUIA 132 .word MC_PUIA
133 .word MC_PUIA_VAL 133 .word CONFIG_SYS_MC_PUIA_VAL
134 .word MC_PUP 134 .word MC_PUP
135 .word MC_PUP_VAL 135 .word CONFIG_SYS_MC_PUP_VAL
136 .word MC_PUER 136 .word MC_PUER
137 .word MC_PUER_VAL 137 .word CONFIG_SYS_MC_PUER_VAL
138 .word MC_ASR 138 .word MC_ASR
139 .word MC_ASR_VAL 139 .word CONFIG_SYS_MC_ASR_VAL
140 .word MC_AASR 140 .word MC_AASR
141 .word MC_AASR_VAL 141 .word CONFIG_SYS_MC_AASR_VAL
142 .word EBI_CFGR 142 .word EBI_CFGR
143 .word EBI_CFGR_VAL 143 .word CONFIG_SYS_EBI_CFGR_VAL
144 .word SMC_CSR0 144 .word SMC_CSR0
145 .word SMC_CSR0_VAL 145 .word CONFIG_SYS_SMC_CSR0_VAL
146 .word PLLAR 146 .word PLLAR
147 .word PLLAR_VAL 147 .word CONFIG_SYS_PLLAR_VAL
148 .word PLLBR 148 .word PLLBR
149 .word PLLBR_VAL 149 .word CONFIG_SYS_PLLBR_VAL
150 .word MCKR 150 .word MCKR
151 .word MCKR_VAL 151 .word CONFIG_SYS_MCKR_VAL
152 /* SMRDATA is 80 bytes long */ 152 /* SMRDATA is 80 bytes long */
153 /* here there's a delay of 100 */ 153 /* here there's a delay of 100 */
154 SMRDATA1: 154 SMRDATA1:
155 .word PIOC_ASR 155 .word PIOC_ASR
156 .word PIOC_ASR_VAL 156 .word CONFIG_SYS_PIOC_ASR_VAL
157 .word PIOC_BSR 157 .word PIOC_BSR
158 .word PIOC_BSR_VAL 158 .word CONFIG_SYS_PIOC_BSR_VAL
159 .word PIOC_PDR 159 .word PIOC_PDR
160 .word PIOC_PDR_VAL 160 .word CONFIG_SYS_PIOC_PDR_VAL
161 .word EBI_CSA 161 .word EBI_CSA
162 .word EBI_CSA_VAL 162 .word CONFIG_SYS_EBI_CSA_VAL
163 .word SDRC_CR 163 .word SDRC_CR
164 .word SDRC_CR_VAL 164 .word CONFIG_SYS_SDRC_CR_VAL
165 .word SDRC_MR 165 .word SDRC_MR
166 .word SDRC_MR_VAL 166 .word CONFIG_SYS_SDRC_MR_VAL
167 .word SDRAM 167 .word CONFIG_SYS_SDRAM
168 .word SDRAM_VAL 168 .word CONFIG_SYS_SDRAM_VAL
169 .word SDRC_MR 169 .word SDRC_MR
170 .word SDRC_MR_VAL1 170 .word CONFIG_SYS_SDRC_MR_VAL1
171 .word SDRAM 171 .word CONFIG_SYS_SDRAM
172 .word SDRAM_VAL 172 .word CONFIG_SYS_SDRAM_VAL
173 .word SDRAM 173 .word CONFIG_SYS_SDRAM
174 .word SDRAM_VAL 174 .word CONFIG_SYS_SDRAM_VAL
175 .word SDRAM 175 .word CONFIG_SYS_SDRAM
176 .word SDRAM_VAL 176 .word CONFIG_SYS_SDRAM_VAL
177 .word SDRAM 177 .word CONFIG_SYS_SDRAM
178 .word SDRAM_VAL 178 .word CONFIG_SYS_SDRAM_VAL
179 .word SDRAM 179 .word CONFIG_SYS_SDRAM
180 .word SDRAM_VAL 180 .word CONFIG_SYS_SDRAM_VAL
181 .word SDRAM 181 .word CONFIG_SYS_SDRAM
182 .word SDRAM_VAL 182 .word CONFIG_SYS_SDRAM_VAL
183 .word SDRAM 183 .word CONFIG_SYS_SDRAM
184 .word SDRAM_VAL 184 .word CONFIG_SYS_SDRAM_VAL
185 .word SDRAM 185 .word CONFIG_SYS_SDRAM
186 .word SDRAM_VAL 186 .word CONFIG_SYS_SDRAM_VAL
187 .word SDRC_MR 187 .word SDRC_MR
188 .word SDRC_MR_VAL2 188 .word CONFIG_SYS_SDRC_MR_VAL2
189 .word SDRAM1 189 .word CONFIG_SYS_SDRAM1
190 .word SDRAM_VAL 190 .word CONFIG_SYS_SDRAM_VAL
191 .word SDRC_TR 191 .word SDRC_TR
192 .word SDRC_TR_VAL 192 .word CONFIG_SYS_SDRC_TR_VAL
193 .word SDRAM 193 .word CONFIG_SYS_SDRAM
194 .word SDRAM_VAL 194 .word CONFIG_SYS_SDRAM_VAL
195 .word SDRC_MR 195 .word SDRC_MR
196 .word SDRC_MR_VAL3 196 .word CONFIG_SYS_SDRC_MR_VAL3
197 .word SDRAM 197 .word CONFIG_SYS_SDRAM
198 .word SDRAM_VAL 198 .word CONFIG_SYS_SDRAM_VAL
199 /* SMRDATA1 is 176 bytes long */ 199 /* SMRDATA1 is 176 bytes long */
200 #endif /* CONFIG_BOOTBINFUNC */ 200 #endif /* CONFIG_BOOTBINFUNC */
201 201
cpu/arm920t/at91rm9200/lowlevel_init.S
Diff comments   View file @ d481c80
1 /* 1 /*
2 * Memory Setup stuff - taken from blob memsetup.S 2 * Memory Setup stuff - taken from blob memsetup.S
3 * 3 *
4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and 4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
5 * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) 5 * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
6 * 6 *
7 * Modified for the at91rm9200dk board by 7 * Modified for the at91rm9200dk board by
8 * (C) Copyright 2004 8 * (C) Copyright 2004
9 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> 9 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
10 * 10 *
11 * See file CREDITS for list of people who contributed to this 11 * See file CREDITS for list of people who contributed to this
12 * project. 12 * project.
13 * 13 *
14 * This program is free software; you can redistribute it and/or 14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as 15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of 16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version. 17 * the License, or (at your option) any later version.
18 * 18 *
19 * This program is distributed in the hope that it will be useful, 19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details. 22 * GNU General Public License for more details.
23 * 23 *
24 * You should have received a copy of the GNU General Public License 24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software 25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA 27 * MA 02111-1307 USA
28 */ 28 */
29 29
30 #include <config.h> 30 #include <config.h>
31 #include <version.h> 31 #include <version.h>
32 32
33 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 33 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
34 /* 34 /*
35 * some parameters for the board 35 * some parameters for the board
36 * 36 *
37 * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in 37 * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
38 * turn is based on the boot.bin code from ATMEL 38 * turn is based on the boot.bin code from ATMEL
39 * 39 *
40 */ 40 */
41 41
42 /* flash */ 42 /* flash */
43 #define MC_PUIA 0xFFFFFF10 43 #define MC_PUIA 0xFFFFFF10
44 #define MC_PUP 0xFFFFFF50 44 #define MC_PUP 0xFFFFFF50
45 #define MC_PUER 0xFFFFFF54 45 #define MC_PUER 0xFFFFFF54
46 #define MC_ASR 0xFFFFFF04 46 #define MC_ASR 0xFFFFFF04
47 #define MC_AASR 0xFFFFFF08 47 #define MC_AASR 0xFFFFFF08
48 #define EBI_CFGR 0xFFFFFF64 48 #define EBI_CFGR 0xFFFFFF64
49 #define SMC_CSR0 0xFFFFFF70 49 #define SMC_CSR0 0xFFFFFF70
50 50
51 /* clocks */ 51 /* clocks */
52 #define PLLAR 0xFFFFFC28 52 #define PLLAR 0xFFFFFC28
53 #define PLLBR 0xFFFFFC2C 53 #define PLLBR 0xFFFFFC2C
54 #define MCKR 0xFFFFFC30 54 #define MCKR 0xFFFFFC30
55 55
56 #define AT91C_BASE_CKGR 0xFFFFFC20 56 #define AT91C_BASE_CKGR 0xFFFFFC20
57 #define CKGR_MOR 0 57 #define CKGR_MOR 0
58 58
59 /* sdram */ 59 /* sdram */
60 #define PIOC_ASR 0xFFFFF870 60 #define PIOC_ASR 0xFFFFF870
61 #define PIOC_BSR 0xFFFFF874 61 #define PIOC_BSR 0xFFFFF874
62 #define PIOC_PDR 0xFFFFF804 62 #define PIOC_PDR 0xFFFFF804
63 #define EBI_CSA 0xFFFFFF60 63 #define EBI_CSA 0xFFFFFF60
64 #define SDRC_CR 0xFFFFFF98 64 #define SDRC_CR 0xFFFFFF98
65 #define SDRC_MR 0xFFFFFF90 65 #define SDRC_MR 0xFFFFFF90
66 #define SDRC_TR 0xFFFFFF94 66 #define SDRC_TR 0xFFFFFF94
67 67
68 68
69 _MTEXT_BASE: 69 _MTEXT_BASE:
70 #undef START_FROM_MEM 70 #undef START_FROM_MEM
71 #ifdef START_FROM_MEM 71 #ifdef START_FROM_MEM
72 .word TEXT_BASE-PHYS_FLASH_1 72 .word TEXT_BASE-PHYS_FLASH_1
73 #else 73 #else
74 .word TEXT_BASE 74 .word TEXT_BASE
75 #endif 75 #endif
76 76
77 .globl lowlevel_init 77 .globl lowlevel_init
78 lowlevel_init: 78 lowlevel_init:
79 /* Get the CKGR Base Address */ 79 /* Get the CKGR Base Address */
80 ldr r1, =AT91C_BASE_CKGR 80 ldr r1, =AT91C_BASE_CKGR
81 /* Main oscillator Enable register */ 81 /* Main oscillator Enable register */
82 #ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR 82 #ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
83 ldr r0, =0x0000FF01 /* Enable main oscillator, OSCOUNT = 0xFF */ 83 ldr r0, =0x0000FF01 /* Enable main oscillator, OSCOUNT = 0xFF */
84 #else 84 #else
85 ldr r0, =0x0000FF00 /* Disable main oscillator, OSCOUNT = 0xFF */ 85 ldr r0, =0x0000FF00 /* Disable main oscillator, OSCOUNT = 0xFF */
86 #endif 86 #endif
87 str r0, [r1, #CKGR_MOR] 87 str r0, [r1, #CKGR_MOR]
88 /* Add loop to compensate Main Oscillator startup time */ 88 /* Add loop to compensate Main Oscillator startup time */
89 ldr r0, =0x00000010 89 ldr r0, =0x00000010
90 LoopOsc: 90 LoopOsc:
91 subs r0, r0, #1 91 subs r0, r0, #1
92 bhi LoopOsc 92 bhi LoopOsc
93 93
94 /* memory control configuration */ 94 /* memory control configuration */
95 /* this isn't very elegant, but what the heck */ 95 /* this isn't very elegant, but what the heck */
96 ldr r0, =SMRDATA 96 ldr r0, =SMRDATA
97 ldr r1, _MTEXT_BASE 97 ldr r1, _MTEXT_BASE
98 sub r0, r0, r1 98 sub r0, r0, r1
99 add r2, r0, #80 99 add r2, r0, #80
100 0: 100 0:
101 /* the address */ 101 /* the address */
102 ldr r1, [r0], #4 102 ldr r1, [r0], #4
103 /* the value */ 103 /* the value */
104 ldr r3, [r0], #4 104 ldr r3, [r0], #4
105 str r3, [r1] 105 str r3, [r1]
106 cmp r2, r0 106 cmp r2, r0
107 bne 0b 107 bne 0b
108 /* delay - this is all done by guess */ 108 /* delay - this is all done by guess */
109 ldr r0, =0x00010000 109 ldr r0, =0x00010000
110 1: 110 1:
111 subs r0, r0, #1 111 subs r0, r0, #1
112 bhi 1b 112 bhi 1b
113 ldr r0, =SMRDATA1 113 ldr r0, =SMRDATA1
114 ldr r1, _MTEXT_BASE 114 ldr r1, _MTEXT_BASE
115 sub r0, r0, r1 115 sub r0, r0, r1
116 add r2, r0, #176 116 add r2, r0, #176
117 2: 117 2:
118 /* the address */ 118 /* the address */
119 ldr r1, [r0], #4 119 ldr r1, [r0], #4
120 /* the value */ 120 /* the value */
121 ldr r3, [r0], #4 121 ldr r3, [r0], #4
122 str r3, [r1] 122 str r3, [r1]
123 cmp r2, r0 123 cmp r2, r0
124 bne 2b 124 bne 2b
125 125
126 /* switch from FastBus to Asynchronous clock mode */ 126 /* switch from FastBus to Asynchronous clock mode */
127 mrc p15, 0, r0, c1, c0, 0 127 mrc p15, 0, r0, c1, c0, 0
128 orr r0, r0, #0xC0000000 @ set bit 31 (iA) and 30 (nF) 128 orr r0, r0, #0xC0000000 @ set bit 31 (iA) and 30 (nF)
129 mcr p15, 0, r0, c1, c0, 0 129 mcr p15, 0, r0, c1, c0, 0
130 130
131 /* everything is fine now */ 131 /* everything is fine now */
132 mov pc, lr 132 mov pc, lr
133 133
134 .ltorg 134 .ltorg
135 135
136 SMRDATA: 136 SMRDATA:
137 .word MC_PUIA 137 .word MC_PUIA
138 .word MC_PUIA_VAL 138 .word CONFIG_SYS_MC_PUIA_VAL
139 .word MC_PUP 139 .word MC_PUP
140 .word MC_PUP_VAL 140 .word CONFIG_SYS_MC_PUP_VAL
141 .word MC_PUER 141 .word MC_PUER
142 .word MC_PUER_VAL 142 .word CONFIG_SYS_MC_PUER_VAL
143 .word MC_ASR 143 .word MC_ASR
144 .word MC_ASR_VAL 144 .word CONFIG_SYS_MC_ASR_VAL
145 .word MC_AASR 145 .word MC_AASR
146 .word MC_AASR_VAL 146 .word CONFIG_SYS_MC_AASR_VAL
147 .word EBI_CFGR 147 .word EBI_CFGR
148 .word EBI_CFGR_VAL 148 .word CONFIG_SYS_EBI_CFGR_VAL
149 .word SMC_CSR0 149 .word SMC_CSR0
150 .word SMC_CSR0_VAL 150 .word CONFIG_SYS_SMC_CSR0_VAL
151 .word PLLAR 151 .word PLLAR
152 .word PLLAR_VAL 152 .word CONFIG_SYS_PLLAR_VAL
153 .word PLLBR 153 .word PLLBR
154 .word PLLBR_VAL 154 .word CONFIG_SYS_PLLBR_VAL
155 .word MCKR 155 .word MCKR
156 .word MCKR_VAL 156 .word CONFIG_SYS_MCKR_VAL
157 /* SMRDATA is 80 bytes long */ 157 /* SMRDATA is 80 bytes long */
158 /* here there's a delay of 100 */ 158 /* here there's a delay of 100 */
159 SMRDATA1: 159 SMRDATA1:
160 .word PIOC_ASR 160 .word PIOC_ASR
161 .word PIOC_ASR_VAL 161 .word CONFIG_SYS_PIOC_ASR_VAL
162 .word PIOC_BSR 162 .word PIOC_BSR
163 .word PIOC_BSR_VAL 163 .word CONFIG_SYS_PIOC_BSR_VAL
164 .word PIOC_PDR 164 .word PIOC_PDR
165 .word PIOC_PDR_VAL 165 .word CONFIG_SYS_PIOC_PDR_VAL
166 .word EBI_CSA 166 .word EBI_CSA
167 .word EBI_CSA_VAL 167 .word CONFIG_SYS_EBI_CSA_VAL
168 .word SDRC_CR 168 .word SDRC_CR
169 .word SDRC_CR_VAL 169 .word CONFIG_SYS_SDRC_CR_VAL
170 .word SDRC_MR 170 .word SDRC_MR
171 .word SDRC_MR_VAL 171 .word CONFIG_SYS_SDRC_MR_VAL
172 .word SDRAM 172 .word CONFIG_SYS_SDRAM
173 .word SDRAM_VAL 173 .word CONFIG_SYS_SDRAM_VAL
174 .word SDRC_MR 174 .word SDRC_MR
175 .word SDRC_MR_VAL1 175 .word CONFIG_SYS_SDRC_MR_VAL1
176 .word SDRAM 176 .word CONFIG_SYS_SDRAM
177 .word SDRAM_VAL 177 .word CONFIG_SYS_SDRAM_VAL
178 .word SDRAM 178 .word CONFIG_SYS_SDRAM
179 .word SDRAM_VAL 179 .word CONFIG_SYS_SDRAM_VAL
180 .word SDRAM 180 .word CONFIG_SYS_SDRAM
181 .word SDRAM_VAL 181 .word CONFIG_SYS_SDRAM_VAL
182 .word SDRAM 182 .word CONFIG_SYS_SDRAM
183 .word SDRAM_VAL 183 .word CONFIG_SYS_SDRAM_VAL
184 .word SDRAM 184 .word CONFIG_SYS_SDRAM
185 .word SDRAM_VAL 185 .word CONFIG_SYS_SDRAM_VAL
186 .word SDRAM 186 .word CONFIG_SYS_SDRAM
187 .word SDRAM_VAL 187 .word CONFIG_SYS_SDRAM_VAL
188 .word SDRAM 188 .word CONFIG_SYS_SDRAM
189 .word SDRAM_VAL 189 .word CONFIG_SYS_SDRAM_VAL
190 .word SDRAM 190 .word CONFIG_SYS_SDRAM
191 .word SDRAM_VAL 191 .word CONFIG_SYS_SDRAM_VAL
192 .word SDRC_MR 192 .word SDRC_MR
193 .word SDRC_MR_VAL2 193 .word CONFIG_SYS_SDRC_MR_VAL2
194 .word SDRAM1 194 .word CONFIG_SYS_SDRAM1
195 .word SDRAM_VAL 195 .word CONFIG_SYS_SDRAM_VAL
196 .word SDRC_TR 196 .word SDRC_TR
197 .word SDRC_TR_VAL 197 .word CONFIG_SYS_SDRC_TR_VAL
198 .word SDRAM 198 .word CONFIG_SYS_SDRAM
199 .word SDRAM_VAL 199 .word CONFIG_SYS_SDRAM_VAL
200 .word SDRC_MR 200 .word SDRC_MR
201 .word SDRC_MR_VAL3 201 .word CONFIG_SYS_SDRC_MR_VAL3
202 .word SDRAM 202 .word CONFIG_SYS_SDRAM
203 .word SDRAM_VAL 203 .word CONFIG_SYS_SDRAM_VAL
204 /* SMRDATA1 is 176 bytes long */ 204 /* SMRDATA1 is 176 bytes long */
205 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 205 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
206 206
include/configs/at91rm9200dk.h
Diff comments   View file @ d481c80
1 /* 1 /*
2 * Rick Bronson <rick@efn.org> 2 * Rick Bronson <rick@efn.org>
3 * 3 *
4 * Configuration settings for the AT91RM9200DK board. 4 * Configuration settings for the AT91RM9200DK board.
5 * 5 *
6 * See file CREDITS for list of people who contributed to this 6 * See file CREDITS for list of people who contributed to this
7 * project. 7 * project.
8 * 8 *
9 * This program is free software; you can redistribute it and/or 9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as 10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of 11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version. 12 * the License, or (at your option) any later version.
13 * 13 *
14 * This program is distributed in the hope that it will be useful, 14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details. 17 * GNU General Public License for more details.
18 * 18 *
19 * You should have received a copy of the GNU General Public License 19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software 20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA 22 * MA 02111-1307 USA
23 */ 23 */
24 24
25 #ifndef __CONFIG_H 25 #ifndef __CONFIG_H
26 #define __CONFIG_H 26 #define __CONFIG_H
27 27
28 /* ARM asynchronous clock */ 28 /* ARM asynchronous clock */
29 #define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */ 29 #define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
30 #define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */ 30 #define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
31 /* #define AT91C_MASTER_CLOCK 44928000 */ /* peripheral clock (AT91C_MASTER_CLOCK / 4) */ 31 /* #define AT91C_MASTER_CLOCK 44928000 */ /* peripheral clock (AT91C_MASTER_CLOCK / 4) */
32 32
33 #define AT91_SLOW_CLOCK 32768 /* slow clock */ 33 #define AT91_SLOW_CLOCK 32768 /* slow clock */
34 34
35 #define CONFIG_ARM920T 1 /* This is an ARM920T Core */ 35 #define CONFIG_ARM920T 1 /* This is an ARM920T Core */
36 #define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ 36 #define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
37 #define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */ 37 #define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
38 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ 38 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
39 #define USE_920T_MMU 1 39 #define USE_920T_MMU 1
40 40
41 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 41 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
42 #define CONFIG_SETUP_MEMORY_TAGS 1 42 #define CONFIG_SETUP_MEMORY_TAGS 1
43 #define CONFIG_INITRD_TAG 1 43 #define CONFIG_INITRD_TAG 1
44 44
45 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 45 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
46 #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 46 #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
47 /* flash */ 47 /* flash */
48 #define MC_PUIA_VAL 0x00000000 48 #define CONFIG_SYS_MC_PUIA_VAL 0x00000000
49 #define MC_PUP_VAL 0x00000000 49 #define CONFIG_SYS_MC_PUP_VAL 0x00000000
50 #define MC_PUER_VAL 0x00000000 50 #define CONFIG_SYS_MC_PUER_VAL 0x00000000
51 #define MC_ASR_VAL 0x00000000 51 #define CONFIG_SYS_MC_ASR_VAL 0x00000000
52 #define MC_AASR_VAL 0x00000000 52 #define CONFIG_SYS_MC_AASR_VAL 0x00000000
53 #define EBI_CFGR_VAL 0x00000000 53 #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
54 #define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ 54 #define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
55 55
56 /* clocks */ 56 /* clocks */
57 #define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ 57 #define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
58 #define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ 58 #define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
59 #define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ 59 #define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
60 60
61 /* sdram */ 61 /* sdram */
62 #define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ 62 #define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
63 #define PIOC_BSR_VAL 0x00000000 63 #define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
64 #define PIOC_PDR_VAL 0xFFFF0000 64 #define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
65 #define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ 65 #define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
66 #define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */ 66 #define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
67 #define SDRAM 0x20000000 /* address of the SDRAM */ 67 #define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
68 #define SDRAM1 0x20000080 /* address of the SDRAM */ 68 #define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */
69 #define SDRAM_VAL 0x00000000 /* value written to SDRAM */ 69 #define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
70 #define SDRC_MR_VAL 0x00000002 /* Precharge All */ 70 #define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
71 #define SDRC_MR_VAL1 0x00000004 /* refresh */ 71 #define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
72 #define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ 72 #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
73 #define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ 73 #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
74 #define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ 74 #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
75 #else 75 #else
76 #define CONFIG_SKIP_RELOCATE_UBOOT 76 #define CONFIG_SKIP_RELOCATE_UBOOT
77 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 77 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
78 /* 78 /*
79 * Size of malloc() pool 79 * Size of malloc() pool
80 */ 80 */
81 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) 81 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
82 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 82 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
83 83
84 #define CONFIG_BAUDRATE 115200 84 #define CONFIG_BAUDRATE 115200
85 85
86 /* 86 /*
87 * Hardware drivers 87 * Hardware drivers
88 */ 88 */
89 89
90 /* define one of these to choose the DBGU, USART0 or USART1 as console */ 90 /* define one of these to choose the DBGU, USART0 or USART1 as console */
91 #define CONFIG_DBGU 91 #define CONFIG_DBGU
92 #undef CONFIG_USART0 92 #undef CONFIG_USART0
93 #undef CONFIG_USART1 93 #undef CONFIG_USART1
94 94
95 #undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ 95 #undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
96 96
97 #undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ 97 #undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
98 98
99 #define CONFIG_BOOTDELAY 3 99 #define CONFIG_BOOTDELAY 3
100 /* #define CONFIG_ENV_OVERWRITE 1 */ 100 /* #define CONFIG_ENV_OVERWRITE 1 */
101 101
102 102
103 /* 103 /*
104 * BOOTP options 104 * BOOTP options
105 */ 105 */
106 #define CONFIG_BOOTP_BOOTFILESIZE 106 #define CONFIG_BOOTP_BOOTFILESIZE
107 #define CONFIG_BOOTP_BOOTPATH 107 #define CONFIG_BOOTP_BOOTPATH
108 #define CONFIG_BOOTP_GATEWAY 108 #define CONFIG_BOOTP_GATEWAY
109 #define CONFIG_BOOTP_HOSTNAME 109 #define CONFIG_BOOTP_HOSTNAME
110 110
111 111
112 /* 112 /*
113 * Command line configuration. 113 * Command line configuration.
114 */ 114 */
115 #include <config_cmd_default.h> 115 #include <config_cmd_default.h>
116 116
117 #define CONFIG_CMD_DHCP 117 #define CONFIG_CMD_DHCP
118 #define CONFIG_CMD_MII 118 #define CONFIG_CMD_MII
119 #define CONFIG_CMD_NAND 119 #define CONFIG_CMD_NAND
120 120
121 #define CONFIG_NAND_LEGACY 121 #define CONFIG_NAND_LEGACY
122 122
123 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ 123 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
124 #define SECTORSIZE 512 124 #define SECTORSIZE 512
125 125
126 #define ADDR_COLUMN 1 126 #define ADDR_COLUMN 1
127 #define ADDR_PAGE 2 127 #define ADDR_PAGE 2
128 #define ADDR_COLUMN_PAGE 3 128 #define ADDR_COLUMN_PAGE 3
129 129
130 #define NAND_ChipID_UNKNOWN 0x00 130 #define NAND_ChipID_UNKNOWN 0x00
131 #define NAND_MAX_FLOORS 1 131 #define NAND_MAX_FLOORS 1
132 #define NAND_MAX_CHIPS 1 132 #define NAND_MAX_CHIPS 1
133 133
134 #define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ 134 #define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
135 #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ 135 #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
136 136
137 #include <asm/arch/AT91RM9200.h> /* needed for port definitions */ 137 #include <asm/arch/AT91RM9200.h> /* needed for port definitions */
138 #define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0) 138 #define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
139 #define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0) 139 #define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
140 140
141 #define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2)) 141 #define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
142 142
143 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0) 143 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
144 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0) 144 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
145 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) 145 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
146 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) 146 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
147 /* the following are NOP's in our implementation */ 147 /* the following are NOP's in our implementation */
148 #define NAND_CTL_CLRALE(nandptr) 148 #define NAND_CTL_CLRALE(nandptr)
149 #define NAND_CTL_SETALE(nandptr) 149 #define NAND_CTL_SETALE(nandptr)
150 #define NAND_CTL_CLRCLE(nandptr) 150 #define NAND_CTL_CLRCLE(nandptr)
151 #define NAND_CTL_SETCLE(nandptr) 151 #define NAND_CTL_SETCLE(nandptr)
152 152
153 #define CONFIG_NR_DRAM_BANKS 1 153 #define CONFIG_NR_DRAM_BANKS 1
154 #define PHYS_SDRAM 0x20000000 154 #define PHYS_SDRAM 0x20000000
155 #define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */ 155 #define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */
156 156
157 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 157 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
158 #define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 158 #define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
159 159
160 #define CONFIG_DRIVER_ETHER 160 #define CONFIG_DRIVER_ETHER
161 #define CONFIG_NET_RETRY_COUNT 20 161 #define CONFIG_NET_RETRY_COUNT 20
162 #define CONFIG_AT91C_USE_RMII 162 #define CONFIG_AT91C_USE_RMII
163 163
164 /* AC Characteristics */ 164 /* AC Characteristics */
165 /* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */ 165 /* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
166 #define DATAFLASH_TCSS (0xC << 16) 166 #define DATAFLASH_TCSS (0xC << 16)
167 #define DATAFLASH_TCHS (0x1 << 24) 167 #define DATAFLASH_TCHS (0x1 << 24)
168 168
169 #define CONFIG_HAS_DATAFLASH 1 169 #define CONFIG_HAS_DATAFLASH 1
170 #define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) 170 #define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
171 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 171 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 2
172 #define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384 172 #define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384
173 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */ 173 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
174 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */ 174 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
175 175
176 #define PHYS_FLASH_1 0x10000000 176 #define PHYS_FLASH_1 0x10000000
177 #define PHYS_FLASH_SIZE 0x200000 /* 2 megs main flash */ 177 #define PHYS_FLASH_SIZE 0x200000 /* 2 megs main flash */
178 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 178 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
179 #define CONFIG_SYS_MAX_FLASH_BANKS 1 179 #define CONFIG_SYS_MAX_FLASH_BANKS 1
180 #define CONFIG_SYS_MAX_FLASH_SECT 256 180 #define CONFIG_SYS_MAX_FLASH_SECT 256
181 #define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ 181 #define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
182 #define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ 182 #define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
183 183
184 #undef CONFIG_ENV_IS_IN_DATAFLASH 184 #undef CONFIG_ENV_IS_IN_DATAFLASH
185 185
186 #ifdef CONFIG_ENV_IS_IN_DATAFLASH 186 #ifdef CONFIG_ENV_IS_IN_DATAFLASH
187 #define CONFIG_ENV_OFFSET 0x20000 187 #define CONFIG_ENV_OFFSET 0x20000
188 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) 188 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
189 #define CONFIG_ENV_SIZE 0x2000 /* 0x8000 */ 189 #define CONFIG_ENV_SIZE 0x2000 /* 0x8000 */
190 #else 190 #else
191 #define CONFIG_ENV_IS_IN_FLASH 1 191 #define CONFIG_ENV_IS_IN_FLASH 1
192 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 192 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
193 #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */ 193 #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */
194 #define CONFIG_ENV_SIZE 0x2000 /* 0x8000 */ 194 #define CONFIG_ENV_SIZE 0x2000 /* 0x8000 */
195 #else 195 #else
196 #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */ 196 #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */
197 #define CONFIG_ENV_SIZE 0x10000 /* sectors are 64K here */ 197 #define CONFIG_ENV_SIZE 0x10000 /* sectors are 64K here */
198 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 198 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
199 #endif /* CONFIG_ENV_IS_IN_DATAFLASH */ 199 #endif /* CONFIG_ENV_IS_IN_DATAFLASH */
200 200
201 201
202 #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ 202 #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
203 203
204 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 204 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
205 #define CONFIG_SYS_BOOT_SIZE 0x6000 /* 24 KBytes */ 205 #define CONFIG_SYS_BOOT_SIZE 0x6000 /* 24 KBytes */
206 #define CONFIG_SYS_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000) 206 #define CONFIG_SYS_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000)
207 #define CONFIG_SYS_U_BOOT_SIZE 0x10000 /* 64 KBytes */ 207 #define CONFIG_SYS_U_BOOT_SIZE 0x10000 /* 64 KBytes */
208 #else 208 #else
209 #define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */ 209 #define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */
210 #define CONFIG_SYS_U_BOOT_BASE PHYS_FLASH_1 210 #define CONFIG_SYS_U_BOOT_BASE PHYS_FLASH_1
211 #define CONFIG_SYS_U_BOOT_SIZE 0x60000 /* 384 KBytes */ 211 #define CONFIG_SYS_U_BOOT_SIZE 0x60000 /* 384 KBytes */
212 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 212 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
213 213
214 #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 19200, 38400, 57600, 9600 } 214 #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 19200, 38400, 57600, 9600 }
215 215
216 #define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */ 216 #define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */
217 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 217 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
218 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 218 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
219 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 219 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
220 220
221 #define CONFIG_SYS_HZ 1000 221 #define CONFIG_SYS_HZ 1000
222 #define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */ 222 #define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
223 /* AT91C_TC_TIMER_DIV1_CLOCK */ 223 /* AT91C_TC_TIMER_DIV1_CLOCK */
224 224
225 #define CONFIG_STACKSIZE (32*1024) /* regular stack */ 225 #define CONFIG_STACKSIZE (32*1024) /* regular stack */
226 226
227 #ifdef CONFIG_USE_IRQ 227 #ifdef CONFIG_USE_IRQ
228 #error CONFIG_USE_IRQ not supported 228 #error CONFIG_USE_IRQ not supported
229 #endif 229 #endif
230 230
231 #endif 231 #endif
232 232
include/configs/cmc_pu2.h
Diff comments   View file @ d481c80
1 /* 1 /*
2 * 2004-2005 Gary Jennejohn <garyj@denx.de> 2 * 2004-2005 Gary Jennejohn <garyj@denx.de>
3 * 3 *
4 * Configuration settings for the CMC PU2 board. 4 * Configuration settings for the CMC PU2 board.
5 * 5 *
6 * See file CREDITS for list of people who contributed to this 6 * See file CREDITS for list of people who contributed to this
7 * project. 7 * project.
8 * 8 *
9 * This program is free software; you can redistribute it and/or 9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as 10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of 11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version. 12 * the License, or (at your option) any later version.
13 * 13 *
14 * This program is distributed in the hope that it will be useful, 14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details. 17 * GNU General Public License for more details.
18 * 18 *
19 * You should have received a copy of the GNU General Public License 19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software 20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA 22 * MA 02111-1307 USA
23 */ 23 */
24 24
25 #ifndef __CONFIG_H 25 #ifndef __CONFIG_H
26 #define __CONFIG_H 26 #define __CONFIG_H
27 27
28 /* ARM asynchronous clock */ 28 /* ARM asynchronous clock */
29 #define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */ 29 #define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
30 #define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */ 30 #define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */
31 31
32 #define AT91_SLOW_CLOCK 32768 /* slow clock */ 32 #define AT91_SLOW_CLOCK 32768 /* slow clock */
33 33
34 #define CONFIG_ARM920T 1 /* This is an ARM920T Core */ 34 #define CONFIG_ARM920T 1 /* This is an ARM920T Core */
35 #define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ 35 #define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
36 #define CONFIG_CMC_PU2 1 /* on an CMC_PU2 Board */ 36 #define CONFIG_CMC_PU2 1 /* on an CMC_PU2 Board */
37 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ 37 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
38 #define USE_920T_MMU 1 38 #define USE_920T_MMU 1
39 39
40 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 40 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
41 #define CONFIG_SETUP_MEMORY_TAGS 1 41 #define CONFIG_SETUP_MEMORY_TAGS 1
42 #define CONFIG_INITRD_TAG 1 42 #define CONFIG_INITRD_TAG 1
43 43
44 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 44 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
45 #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 45 #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
46 /* flash */ 46 /* flash */
47 #define MC_PUIA_VAL 0x00000000 47 #define CONFIG_SYS_MC_PUIA_VAL 0x00000000
48 #define MC_PUP_VAL 0x00000000 48 #define CONFIG_SYS_MC_PUP_VAL 0x00000000
49 #define MC_PUER_VAL 0x00000000 49 #define CONFIG_SYS_MC_PUER_VAL 0x00000000
50 #define MC_ASR_VAL 0x00000000 50 #define CONFIG_SYS_MC_ASR_VAL 0x00000000
51 #define MC_AASR_VAL 0x00000000 51 #define CONFIG_SYS_MC_AASR_VAL 0x00000000
52 #define EBI_CFGR_VAL 0x00000000 52 #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
53 #define SMC_CSR0_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */ 53 #define CONFIG_SYS_SMC_CSR0_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */
54 54
55 /* clocks */ 55 /* clocks */
56 #define PLLAR_VAL 0x2026BE04 /* 179,712 MHz for PCK */ 56 #define CONFIG_SYS_PLLAR_VAL 0x2026BE04 /* 179,712 MHz for PCK */
57 #define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ 57 #define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
58 #define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */ 58 #define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */
59 59
60 /* sdram */ 60 /* sdram */
61 #define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ 61 #define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
62 #define PIOC_BSR_VAL 0x00000000 62 #define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
63 #define PIOC_PDR_VAL 0xFFFF0000 63 #define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
64 #define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ 64 #define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
65 #define SDRC_CR_VAL 0x3399c1d4 /* set up the SDRAM */ 65 #define CONFIG_SYS_SDRC_CR_VAL 0x3399c1d4 /* set up the CONFIG_SYS_SDRAM */
66 #define SDRAM 0x20000000 /* address of the SDRAM */ 66 #define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
67 #define SDRAM1 0x20000080 /* address of the SDRAM */ 67 #define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */
68 #define SDRAM_VAL 0x00000000 /* value written to SDRAM */ 68 #define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
69 #define SDRC_MR_VAL 0x00000002 /* Precharge All */ 69 #define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
70 #define SDRC_MR_VAL1 0x00000004 /* refresh */ 70 #define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
71 #define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ 71 #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
72 #define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ 72 #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
73 #define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ 73 #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
74 #else 74 #else
75 #define CONFIG_SKIP_RELOCATE_UBOOT 75 #define CONFIG_SKIP_RELOCATE_UBOOT
76 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 76 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
77 77
78 /* 78 /*
79 * Size of malloc() pool 79 * Size of malloc() pool
80 */ 80 */
81 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) 81 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
82 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 82 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
83 83
84 #define CONFIG_BAUDRATE 9600 84 #define CONFIG_BAUDRATE 9600
85 85
86 /* 86 /*
87 * Hardware drivers 87 * Hardware drivers
88 */ 88 */
89 89
90 /* define one of these to choose the DBGU, USART0 or USART1 as console */ 90 /* define one of these to choose the DBGU, USART0 or USART1 as console */
91 #undef CONFIG_DBGU 91 #undef CONFIG_DBGU
92 #define CONFIG_USART0 92 #define CONFIG_USART0
93 #undef CONFIG_USART1 93 #undef CONFIG_USART1
94 94
95 #undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ 95 #undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
96 96
97 #undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ 97 #undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
98 98
99 #define CONFIG_HARD_I2C 99 #define CONFIG_HARD_I2C
100 100
101 #ifdef CONFIG_HARD_I2C 101 #ifdef CONFIG_HARD_I2C
102 #define CONFIG_SYS_I2C_SPEED 0 /* not used */ 102 #define CONFIG_SYS_I2C_SPEED 0 /* not used */
103 #define CONFIG_SYS_I2C_SLAVE 0 /* not used */ 103 #define CONFIG_SYS_I2C_SLAVE 0 /* not used */
104 #define CONFIG_RTC_RS5C372A /* RICOH I2C RTC */ 104 #define CONFIG_RTC_RS5C372A /* RICOH I2C RTC */
105 #define CONFIG_SYS_I2C_RTC_ADDR 0x32 105 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
106 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 106 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
107 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 107 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
108 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 108 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
109 #else 109 #else
110 #define CONFIG_TIMESTAMP 110 #define CONFIG_TIMESTAMP
111 #endif 111 #endif
112 /* still about 20 kB free with this defined */ 112 /* still about 20 kB free with this defined */
113 #define CONFIG_SYS_LONGHELP 113 #define CONFIG_SYS_LONGHELP
114 114
115 #define CONFIG_BOOTDELAY 1 115 #define CONFIG_BOOTDELAY 1
116 116
117 117
118 /* 118 /*
119 * BOOTP options 119 * BOOTP options
120 */ 120 */
121 #define CONFIG_BOOTP_BOOTFILESIZE 121 #define CONFIG_BOOTP_BOOTFILESIZE
122 #define CONFIG_BOOTP_BOOTPATH 122 #define CONFIG_BOOTP_BOOTPATH
123 #define CONFIG_BOOTP_GATEWAY 123 #define CONFIG_BOOTP_GATEWAY
124 #define CONFIG_BOOTP_HOSTNAME 124 #define CONFIG_BOOTP_HOSTNAME
125 125
126 126
127 /* 127 /*
128 * Command line configuration. 128 * Command line configuration.
129 */ 129 */
130 #include <config_cmd_default.h> 130 #include <config_cmd_default.h>
131 131
132 #define CONFIG_CMD_DHCP 132 #define CONFIG_CMD_DHCP
133 #define CONFIG_CMD_NFS 133 #define CONFIG_CMD_NFS
134 #define CONFIG_CMD_SNTP 134 #define CONFIG_CMD_SNTP
135 135
136 #undef CONFIG_CMD_FPGA 136 #undef CONFIG_CMD_FPGA
137 #undef CONFIG_CMD_MISC 137 #undef CONFIG_CMD_MISC
138 138
139 #if defined(CONFIG_HARD_I2C) 139 #if defined(CONFIG_HARD_I2C)
140 #define CONFIG_CMD_DATE 140 #define CONFIG_CMD_DATE
141 #define CONFIG_CMD_EEPROM 141 #define CONFIG_CMD_EEPROM
142 #define CONFIG_CMD_I2C 142 #define CONFIG_CMD_I2C
143 #endif 143 #endif
144 144
145 145
146 #define CONFIG_SYS_LONGHELP 146 #define CONFIG_SYS_LONGHELP
147 147
148 #define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ 148 #define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
149 #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ 149 #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
150 150
151 #define CONFIG_NR_DRAM_BANKS 1 151 #define CONFIG_NR_DRAM_BANKS 1
152 #define PHYS_SDRAM 0x20000000 152 #define PHYS_SDRAM 0x20000000
153 #define PHYS_SDRAM_SIZE 0x1000000 /* 16 megs */ 153 #define PHYS_SDRAM_SIZE 0x1000000 /* 16 megs */
154 154
155 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 155 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
156 #define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 156 #define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
157 157
158 #define CONFIG_DRIVER_ETHER 158 #define CONFIG_DRIVER_ETHER
159 #define CONFIG_NET_RETRY_COUNT 20 159 #define CONFIG_NET_RETRY_COUNT 20
160 #define CONFIG_AT91C_USE_RMII 160 #define CONFIG_AT91C_USE_RMII
161 161
162 #define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) 162 #define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
163 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 163 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 2
164 #define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384 164 #define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384
165 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */ 165 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
166 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */ 166 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
167 167
168 #define PHYS_FLASH_1 0x10000000 168 #define PHYS_FLASH_1 0x10000000
169 #define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */ 169 #define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */
170 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 170 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
171 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 171 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
172 #define CONFIG_SYS_MAX_FLASH_BANKS 1 172 #define CONFIG_SYS_MAX_FLASH_BANKS 1
173 #define CONFIG_SYS_MAX_FLASH_SECT 256 173 #define CONFIG_SYS_MAX_FLASH_SECT 256
174 #define CONFIG_SYS_FLASH_ERASE_TOUT (11 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ 174 #define CONFIG_SYS_FLASH_ERASE_TOUT (11 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
175 #define CONFIG_SYS_FLASH_WRITE_TOUT ( 2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ 175 #define CONFIG_SYS_FLASH_WRITE_TOUT ( 2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
176 176
177 #define CONFIG_ENV_IS_IN_FLASH 1 177 #define CONFIG_ENV_IS_IN_FLASH 1
178 #define CONFIG_ENV_OFFSET 0x20000 /* after u-boot.bin */ 178 #define CONFIG_ENV_OFFSET 0x20000 /* after u-boot.bin */
179 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* sectors are 64 kB */ 179 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* sectors are 64 kB */
180 #define CONFIG_ENV_SIZE (16 << 10) /* Use only 16 kB */ 180 #define CONFIG_ENV_SIZE (16 << 10) /* Use only 16 kB */
181 181
182 #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ 182 #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
183 183
184 #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } 184 #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
185 185
186 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 186 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
187 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 187 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
188 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 188 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
189 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 189 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
190 190
191 #define CONFIG_SYS_HZ 1000 191 #define CONFIG_SYS_HZ 1000
192 #define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK/2) /* AT91C_TC0_CMR is implicitly set to */ 192 #define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK/2) /* AT91C_TC0_CMR is implicitly set to */
193 /* AT91C_TC_TIMER_DIV1_CLOCK */ 193 /* AT91C_TC_TIMER_DIV1_CLOCK */
194 194
195 #define CONFIG_STACKSIZE (32*1024) /* regular stack */ 195 #define CONFIG_STACKSIZE (32*1024) /* regular stack */
196 196
197 #ifdef CONFIG_USE_IRQ 197 #ifdef CONFIG_USE_IRQ
198 #error CONFIG_USE_IRQ not supported 198 #error CONFIG_USE_IRQ not supported
199 #endif 199 #endif
200 200
201 #define CONFIG_EXTRA_ENV_SETTINGS \ 201 #define CONFIG_EXTRA_ENV_SETTINGS \
202 "net_nfs=tftp ${loadaddr} ${bootfile};run nfsargs addip addcons " \ 202 "net_nfs=tftp ${loadaddr} ${bootfile};run nfsargs addip addcons " \
203 "addmtd;bootm\0" \ 203 "addmtd;bootm\0" \
204 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 204 "nfsargs=setenv bootargs root=/dev/nfs rw " \
205 "nfsroot=${serverip}:${rootpath}\0" \ 205 "nfsroot=${serverip}:${rootpath}\0" \
206 "net_cramfs=tftp ${loadaddr} ${bootfile}; run flashargs addip " \ 206 "net_cramfs=tftp ${loadaddr} ${bootfile}; run flashargs addip " \
207 "addcons addmtd; bootm\0" \ 207 "addcons addmtd; bootm\0" \
208 "flash_cramfs=run flashargs addip addcons addmtd; bootm 10030000\0" \ 208 "flash_cramfs=run flashargs addip addcons addmtd; bootm 10030000\0" \
209 "flashargs=setenv bootargs root=/dev/mtdblock3 ro\0" \ 209 "flashargs=setenv bootargs root=/dev/mtdblock3 ro\0" \
210 "addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \ 210 "addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \
211 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ 211 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
212 "${hostname}::off\0" \ 212 "${hostname}::off\0" \
213 "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ 213 "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
214 "addmtd=setenv bootargs ${bootargs} mtdparts=cmc_pu2:128k(uboot)ro," \ 214 "addmtd=setenv bootargs ${bootargs} mtdparts=cmc_pu2:128k(uboot)ro," \
215 "64k(environment),768k(linux),4096k(root),-\0" \ 215 "64k(environment),768k(linux),4096k(root),-\0" \
216 "load=tftp ${loadaddr} ${loadfile}\0" \ 216 "load=tftp ${loadaddr} ${loadfile}\0" \
217 "update=protect off 10000000 1001ffff;erase 10000000 1001ffff; " \ 217 "update=protect off 10000000 1001ffff;erase 10000000 1001ffff; " \
218 "cp.b ${loadaddr} 10000000 ${filesize};" \ 218 "cp.b ${loadaddr} 10000000 ${filesize};" \
219 "protect on 10000000 1001ffff\0" \ 219 "protect on 10000000 1001ffff\0" \
220 "updatel=era 10030000 100effff;tftp ${loadaddr} ${bootfile}; " \ 220 "updatel=era 10030000 100effff;tftp ${loadaddr} ${bootfile}; " \
221 "cp.b ${loadaddr} 10030000 ${filesize}\0" \ 221 "cp.b ${loadaddr} 10030000 ${filesize}\0" \
222 "updatec=era 100f0000 104effff;tftp ${loadaddr} ${cramfsimage}; " \ 222 "updatec=era 100f0000 104effff;tftp ${loadaddr} ${cramfsimage}; " \
223 "cp.b ${loadaddr} 100f0000 ${filesize}\0" \ 223 "cp.b ${loadaddr} 100f0000 ${filesize}\0" \
224 "updatej=era 104f0000 107fffff;tftp ${loadaddr} ${jffsimage}; " \ 224 "updatej=era 104f0000 107fffff;tftp ${loadaddr} ${jffsimage}; " \
225 "cp.b ${loadaddr} 104f0000 ${filesize}\0" \ 225 "cp.b ${loadaddr} 104f0000 ${filesize}\0" \
226 "cramfsimage=cramfs_cmc-pu2.img\0" \ 226 "cramfsimage=cramfs_cmc-pu2.img\0" \
227 "jffsimage=jffs2_cmc-pu2.img\0" \ 227 "jffsimage=jffs2_cmc-pu2.img\0" \
228 "loadfile=u-boot_cmc-pu2.bin\0" \ 228 "loadfile=u-boot_cmc-pu2.bin\0" \
229 "bootfile=uImage_cmc-pu2\0" \ 229 "bootfile=uImage_cmc-pu2\0" \
230 "loadaddr=0x20800000\0" \ 230 "loadaddr=0x20800000\0" \
231 "hostname=CMC-TC-PU2\0" \ 231 "hostname=CMC-TC-PU2\0" \
232 "bootcmd=run dhcp_start;run flash_cramfs\0" \ 232 "bootcmd=run dhcp_start;run flash_cramfs\0" \
233 "autoload=n\0" \ 233 "autoload=n\0" \
234 "dhcp_start=echo no DHCP\0" \ 234 "dhcp_start=echo no DHCP\0" \
235 "ipaddr=192.168.0.190\0" 235 "ipaddr=192.168.0.190\0"
236 #endif /* __CONFIG_H */ 236 #endif /* __CONFIG_H */
237 237
include/configs/csb637.h
Diff comments   View file @ d481c80
1 /* 1 /*
2 * (C) Copyright 2005 REA Elektronik GmbH <www.rea.de> 2 * (C) Copyright 2005 REA Elektronik GmbH <www.rea.de>
3 * Anders Larsen <alarsen@rea.de> 3 * Anders Larsen <alarsen@rea.de>
4 * 4 *
5 * Configuation settings for the Cogent CSB637 board. 5 * Configuation settings for the Cogent CSB637 board.
6 * 6 *
7 * See file CREDITS for list of people who contributed to this 7 * See file CREDITS for list of people who contributed to this
8 * project. 8 * project.
9 * 9 *
10 * This program is free software; you can redistribute it and/or 10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as 11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of 12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version. 13 * the License, or (at your option) any later version.
14 * 14 *
15 * This program is distributed in the hope that it will be useful, 15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details. 18 * GNU General Public License for more details.
19 * 19 *
20 * You should have received a copy of the GNU General Public License 20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software 21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA 23 * MA 02111-1307 USA
24 */ 24 */
25 25
26 #ifndef __CONFIG_H 26 #ifndef __CONFIG_H
27 #define __CONFIG_H 27 #define __CONFIG_H
28 28
29 /* ARM asynchronous clock */ 29 /* ARM asynchronous clock */
30 #define AT91C_MAIN_CLOCK 184320000 /* from 3.6864 MHz crystal (3686400 * 50) */ 30 #define AT91C_MAIN_CLOCK 184320000 /* from 3.6864 MHz crystal (3686400 * 50) */
31 #define AT91C_MASTER_CLOCK 46080000 /* (AT91C_MAIN_CLOCK/4) peripheral clock */ 31 #define AT91C_MASTER_CLOCK 46080000 /* (AT91C_MAIN_CLOCK/4) peripheral clock */
32 32
33 #define AT91_SLOW_CLOCK 32768 /* slow clock */ 33 #define AT91_SLOW_CLOCK 32768 /* slow clock */
34 34
35 #define CONFIG_ARM920T 1 /* This is an ARM920T Core */ 35 #define CONFIG_ARM920T 1 /* This is an ARM920T Core */
36 #define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ 36 #define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
37 #define CONFIG_CSB637 1 /* on a CSB637 board */ 37 #define CONFIG_CSB637 1 /* on a CSB637 board */
38 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ 38 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
39 #define USE_920T_MMU 1 39 #define USE_920T_MMU 1
40 40
41 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 41 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
42 #define CONFIG_SETUP_MEMORY_TAGS 1 42 #define CONFIG_SETUP_MEMORY_TAGS 1
43 #define CONFIG_INITRD_TAG 1 43 #define CONFIG_INITRD_TAG 1
44 44
45 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 45 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
46 #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 46 #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
47 /* flash */ 47 /* flash */
48 #define MC_PUIA_VAL 0x00000000 48 #define CONFIG_SYS_MC_PUIA_VAL 0x00000000
49 #define MC_PUP_VAL 0x00000000 49 #define CONFIG_SYS_MC_PUP_VAL 0x00000000
50 #define MC_PUER_VAL 0x00000000 50 #define CONFIG_SYS_MC_PUER_VAL 0x00000000
51 #define MC_ASR_VAL 0x00000000 51 #define CONFIG_SYS_MC_ASR_VAL 0x00000000
52 #define MC_AASR_VAL 0x00000000 52 #define CONFIG_SYS_MC_AASR_VAL 0x00000000
53 #define EBI_CFGR_VAL 0x00000000 53 #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
54 #define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ 54 #define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
55 55
56 /* clocks */ 56 /* clocks */
57 #define PLLAR_VAL 0x2031BE01 /* 184.320000 MHz for PCK */ 57 #define CONFIG_SYS_PLLAR_VAL 0x2031BE01 /* 184.320000 MHz for PCK */
58 #define PLLBR_VAL 0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */ 58 #define CONFIG_SYS_PLLBR_VAL 0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */
59 #define MCKR_VAL 0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */ 59 #define CONFIG_SYS_MCKR_VAL 0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */
60 60
61 /* sdram */ 61 /* sdram */
62 #define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ 62 #define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
63 #define PIOC_BSR_VAL 0x00000000 63 #define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
64 #define PIOC_PDR_VAL 0xFFFF0000 64 #define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
65 #define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ 65 #define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
66 #define SDRC_CR_VAL 0x21914159 /* set up the SDRAM */ 66 #define CONFIG_SYS_SDRC_CR_VAL 0x21914159 /* set up the CONFIG_SYS_SDRAM */
67 #define SDRAM 0x20000000 /* address of the SDRAM */ 67 #define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
68 #define SDRAM1 0x20000080 /* address of the SDRAM */ 68 #define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */
69 #define SDRAM_VAL 0x00000000 /* value written to SDRAM */ 69 #define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
70 #define SDRC_MR_VAL 0x00000002 /* Precharge All */ 70 #define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
71 #define SDRC_MR_VAL1 0x00000004 /* refresh */ 71 #define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
72 #define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ 72 #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
73 #define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ 73 #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
74 #define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ 74 #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
75 #else 75 #else
76 #define CONFIG_SKIP_RELOCATE_UBOOT 76 #define CONFIG_SKIP_RELOCATE_UBOOT
77 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 77 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
78 /* 78 /*
79 * Size of malloc() pool 79 * Size of malloc() pool
80 */ 80 */
81 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) 81 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
82 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 82 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
83 83
84 #define CONFIG_BAUDRATE 115200 84 #define CONFIG_BAUDRATE 115200
85 85
86 #define CONFIG_SYS_AT91C_BRGR_DIVISOR 75 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */ 86 #define CONFIG_SYS_AT91C_BRGR_DIVISOR 75 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
87 87
88 /* 88 /*
89 * Hardware drivers 89 * Hardware drivers
90 */ 90 */
91 91
92 /* define one of these to choose the DBGU, USART0 or USART1 as console */ 92 /* define one of these to choose the DBGU, USART0 or USART1 as console */
93 #define CONFIG_DBGU 93 #define CONFIG_DBGU
94 #undef CONFIG_USART0 94 #undef CONFIG_USART0
95 #undef CONFIG_USART1 95 #undef CONFIG_USART1
96 96
97 #undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ 97 #undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
98 98
99 #undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ 99 #undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
100 100
101 #define CONFIG_BOOTDELAY 3 101 #define CONFIG_BOOTDELAY 3
102 /* #define CONFIG_ENV_OVERWRITE 1 */ 102 /* #define CONFIG_ENV_OVERWRITE 1 */
103 103
104 104
105 /* 105 /*
106 * BOOTP options 106 * BOOTP options
107 */ 107 */
108 #define CONFIG_BOOTP_BOOTFILESIZE 108 #define CONFIG_BOOTP_BOOTFILESIZE
109 #define CONFIG_BOOTP_BOOTPATH 109 #define CONFIG_BOOTP_BOOTPATH
110 #define CONFIG_BOOTP_GATEWAY 110 #define CONFIG_BOOTP_GATEWAY
111 #define CONFIG_BOOTP_HOSTNAME 111 #define CONFIG_BOOTP_HOSTNAME
112 112
113 113
114 /* 114 /*
115 * Command line configuration. 115 * Command line configuration.
116 */ 116 */
117 #include <config_cmd_default.h> 117 #include <config_cmd_default.h>
118 118
119 #define CONFIG_CMD_DHCP 119 #define CONFIG_CMD_DHCP
120 #define CONFIG_CMD_JFFS2 120 #define CONFIG_CMD_JFFS2
121 #define CONFIG_CMD_PING 121 #define CONFIG_CMD_PING
122 122
123 #ifdef NAND_SUPPORT_HAS_BEEN_FIXED /* NAND support is broken / unimplemented */ 123 #ifdef NAND_SUPPORT_HAS_BEEN_FIXED /* NAND support is broken / unimplemented */
124 124
125 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ 125 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
126 #define SECTORSIZE 512 126 #define SECTORSIZE 512
127 127
128 #define ADDR_COLUMN 1 128 #define ADDR_COLUMN 1
129 #define ADDR_PAGE 2 129 #define ADDR_PAGE 2
130 #define ADDR_COLUMN_PAGE 3 130 #define ADDR_COLUMN_PAGE 3
131 131
132 #define NAND_ChipID_UNKNOWN 0x00 132 #define NAND_ChipID_UNKNOWN 0x00
133 #define NAND_MAX_FLOORS 1 133 #define NAND_MAX_FLOORS 1
134 #define NAND_MAX_CHIPS 1 134 #define NAND_MAX_CHIPS 1
135 135
136 #define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ 136 #define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
137 #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ 137 #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
138 138
139 #include <asm/arch/AT91RM9200.h> /* needed for port definitions */ 139 #include <asm/arch/AT91RM9200.h> /* needed for port definitions */
140 #define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0) 140 #define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
141 #define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0) 141 #define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
142 142
143 #define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2)) 143 #define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
144 144
145 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0) 145 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
146 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0) 146 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
147 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) 147 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
148 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) 148 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
149 /* the following are NOP's in our implementation */ 149 /* the following are NOP's in our implementation */
150 #define NAND_CTL_CLRALE(nandptr) 150 #define NAND_CTL_CLRALE(nandptr)
151 #define NAND_CTL_SETALE(nandptr) 151 #define NAND_CTL_SETALE(nandptr)
152 #define NAND_CTL_CLRCLE(nandptr) 152 #define NAND_CTL_CLRCLE(nandptr)
153 #define NAND_CTL_SETCLE(nandptr) 153 #define NAND_CTL_SETCLE(nandptr)
154 154
155 #endif /* NAND_SUPPORT_HAS_BEEN_FIXED */ 155 #endif /* NAND_SUPPORT_HAS_BEEN_FIXED */
156 156
157 #define CONFIG_NR_DRAM_BANKS 1 157 #define CONFIG_NR_DRAM_BANKS 1
158 #define PHYS_SDRAM 0x20000000 158 #define PHYS_SDRAM 0x20000000
159 #define PHYS_SDRAM_SIZE 0x4000000 /* 64 megs */ 159 #define PHYS_SDRAM_SIZE 0x4000000 /* 64 megs */
160 160
161 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 161 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
162 #define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 512*1024 - 4 162 #define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 512*1024 - 4
163 #define CONFIG_SYS_ALT_MEMTEST 1 163 #define CONFIG_SYS_ALT_MEMTEST 1
164 #define CONFIG_SYS_MEMTEST_SCRATCH CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 4 164 #define CONFIG_SYS_MEMTEST_SCRATCH CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 4
165 165
166 #define CONFIG_DRIVER_ETHER 166 #define CONFIG_DRIVER_ETHER
167 #define CONFIG_NET_RETRY_COUNT 20 167 #define CONFIG_NET_RETRY_COUNT 20
168 #undef CONFIG_AT91C_USE_RMII 168 #undef CONFIG_AT91C_USE_RMII
169 169
170 #undef CONFIG_HAS_DATAFLASH 170 #undef CONFIG_HAS_DATAFLASH
171 #define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) 171 #define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
172 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 0 172 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 0
173 #define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384 173 #define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384
174 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */ 174 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
175 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */ 175 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
176 176
177 /* 177 /*
178 * FLASH Device configuration 178 * FLASH Device configuration
179 */ 179 */
180 #define PHYS_FLASH_1 0x10000000 180 #define PHYS_FLASH_1 0x10000000
181 #define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */ 181 #define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */
182 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 182 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
183 #define CONFIG_SYS_FLASH_CFI 1 /* flash is CFI conformant */ 183 #define CONFIG_SYS_FLASH_CFI 1 /* flash is CFI conformant */
184 #define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ 184 #define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
185 #define CONFIG_SYS_FLASH_EMPTY_INFO 185 #define CONFIG_SYS_FLASH_EMPTY_INFO
186 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ 186 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
187 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */ 187 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */
188 #define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */ 188 #define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */
189 #define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */ 189 #define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */
190 #define CONFIG_SYS_MAX_FLASH_SECT 64 190 #define CONFIG_SYS_MAX_FLASH_SECT 64
191 191
192 #define CONFIG_SYS_JFFS2_FIRST_BANK 0 192 #define CONFIG_SYS_JFFS2_FIRST_BANK 0
193 #define CONFIG_SYS_JFFS2_FIRST_SECTOR 3 193 #define CONFIG_SYS_JFFS2_FIRST_SECTOR 3
194 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 194 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
195 195
196 #undef CONFIG_ENV_IS_IN_DATAFLASH 196 #undef CONFIG_ENV_IS_IN_DATAFLASH
197 197
198 #ifdef CONFIG_ENV_IS_IN_DATAFLASH 198 #ifdef CONFIG_ENV_IS_IN_DATAFLASH
199 #define CONFIG_ENV_OFFSET 0x20000 199 #define CONFIG_ENV_OFFSET 0x20000
200 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) 200 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
201 #define CONFIG_ENV_SIZE 0x2000 /* 0x8000 */ 201 #define CONFIG_ENV_SIZE 0x2000 /* 0x8000 */
202 #else 202 #else
203 #define CONFIG_ENV_IS_IN_FLASH 1 203 #define CONFIG_ENV_IS_IN_FLASH 1
204 #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* after u-boot.bin */ 204 #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* after u-boot.bin */
205 #define CONFIG_ENV_SIZE 0x20000 /* sectors are 128K here */ 205 #define CONFIG_ENV_SIZE 0x20000 /* sectors are 128K here */
206 #endif /* CONFIG_ENV_IS_IN_DATAFLASH */ 206 #endif /* CONFIG_ENV_IS_IN_DATAFLASH */
207 207
208 208
209 #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ 209 #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
210 210
211 #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } 211 #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
212 212
213 #define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */ 213 #define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */
214 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 214 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
215 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 215 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
216 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 216 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
217 217
218 #define CONFIG_SYS_HZ 1000 218 #define CONFIG_SYS_HZ 1000
219 #define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */ 219 #define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
220 /* AT91C_TC_TIMER_DIV1_CLOCK */ 220 /* AT91C_TC_TIMER_DIV1_CLOCK */
221 221
222 #define CONFIG_STACKSIZE (32*1024) /* regular stack */ 222 #define CONFIG_STACKSIZE (32*1024) /* regular stack */
223 223
224 #ifdef CONFIG_USE_IRQ 224 #ifdef CONFIG_USE_IRQ
225 #error CONFIG_USE_IRQ not supported 225 #error CONFIG_USE_IRQ not supported
226 #endif 226 #endif
227 227
228 #endif 228 #endif
229 229
include/configs/mp2usb.h
Diff comments   View file @ d481c80
1 /* 1 /*
2 * 2004-2005 Gary Jennejohn <garyj@denx.de> 2 * 2004-2005 Gary Jennejohn <garyj@denx.de>
3 * 3 *
4 * Modified for the MP2USB by (C) Copyright 2005 Eric Benard 4 * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
5 * ebenard@eukrea.com 5 * ebenard@eukrea.com
6 * 6 *
7 * Configuration settings for the MP2USB board. 7 * Configuration settings for the MP2USB board.
8 * 8 *
9 * See file CREDITS for list of people who contributed to this 9 * See file CREDITS for list of people who contributed to this
10 * project. 10 * project.
11 * 11 *
12 * This program is free software; you can redistribute it and/or 12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as 13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of 14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version. 15 * the License, or (at your option) any later version.
16 * 16 *
17 * This program is distributed in the hope that it will be useful, 17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details. 20 * GNU General Public License for more details.
21 * 21 *
22 * You should have received a copy of the GNU General Public License 22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software 23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA 25 * MA 02111-1307 USA
26 */ 26 */
27 27
28 #ifndef __CONFIG_H 28 #ifndef __CONFIG_H
29 #define __CONFIG_H 29 #define __CONFIG_H
30 30
31 /* ARM asynchronous clock */ 31 /* ARM asynchronous clock */
32 #define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 45) */ 32 #define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 45) */
33 #define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */ 33 #define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */
34 34
35 #define AT91_SLOW_CLOCK 32768 /* slow clock */ 35 #define AT91_SLOW_CLOCK 32768 /* slow clock */
36 36
37 #define CONFIG_ARM920T 1 /* This is an ARM920T Core */ 37 #define CONFIG_ARM920T 1 /* This is an ARM920T Core */
38 #define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ 38 #define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
39 #define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */ 39 #define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
40 #define CONFIG_MP2USB 1 /* on an MP2USB Board */ 40 #define CONFIG_MP2USB 1 /* on an MP2USB Board */
41 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ 41 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
42 #define USE_920T_MMU 1 42 #define USE_920T_MMU 1
43 43
44 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 44 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
45 #define CONFIG_SETUP_MEMORY_TAGS 1 45 #define CONFIG_SETUP_MEMORY_TAGS 1
46 #define CONFIG_INITRD_TAG 1 46 #define CONFIG_INITRD_TAG 1
47 47
48 #define CONFIG_SYS_ATMEL_PLL_INIT_BUG 1 48 #define CONFIG_SYS_ATMEL_PLL_INIT_BUG 1
49 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 49 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
50 #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 50 #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
51 /* flash */ 51 /* flash */
52 #define MC_PUIA_VAL 0x00000000 52 #define CONFIG_SYS_MC_PUIA_VAL 0x00000000
53 #define MC_PUP_VAL 0x00000000 53 #define CONFIG_SYS_MC_PUP_VAL 0x00000000
54 #define MC_PUER_VAL 0x00000000 54 #define CONFIG_SYS_MC_PUER_VAL 0x00000000
55 #define MC_ASR_VAL 0x00000000 55 #define CONFIG_SYS_MC_ASR_VAL 0x00000000
56 #define MC_AASR_VAL 0x00000000 56 #define CONFIG_SYS_MC_AASR_VAL 0x00000000
57 #define EBI_CFGR_VAL 0x00000000 57 #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
58 #define SMC_CSR0_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */ 58 #define CONFIG_SYS_SMC_CSR0_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */
59 59
60 /* clocks */ 60 /* clocks */
61 #define PLLAR_VAL 0x20263E04 /* 180 MHz for PCK */ 61 #define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 180 MHz for PCK */
62 #define PLLBR_VAL 0x1048bE0E /* 48 MHz (divider by 2 for USB) */ 62 #define CONFIG_SYS_PLLBR_VAL 0x1048bE0E /* 48 MHz (divider by 2 for USB) */
63 #define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 60MHz from PLLA */ 63 #define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 60MHz from PLLA */
64 64
65 /* sdram */ 65 /* sdram */
66 #define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ 66 #define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
67 #define PIOC_BSR_VAL 0x00000000 67 #define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
68 #define PIOC_PDR_VAL 0xFFFF0000 68 #define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
69 #define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ 69 #define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
70 #define SDRC_CR_VAL 0x3211295A /* set up the SDRAM */ 70 #define CONFIG_SYS_SDRC_CR_VAL 0x3211295A /* set up the CONFIG_SYS_SDRAM */
71 #define SDRAM 0x20000000 /* address of the SDRAM */ 71 #define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
72 #define SDRAM1 0x20000020 /* address of the SDRAM */ 72 #define CONFIG_SYS_SDRAM1 0x20000020 /* address of the CONFIG_SYS_SDRAM */
73 #define SDRAM_VAL 0x00000000 /* value written to SDRAM */ 73 #define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
74 #define SDRC_MR_VAL 0x00000002 /* Precharge All */ 74 #define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
75 #define SDRC_MR_VAL1 0x00000004 /* refresh */ 75 #define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
76 #define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ 76 #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
77 #define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ 77 #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
78 #define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ 78 #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
79 #else 79 #else
80 #define CONFIG_SKIP_RELOCATE_UBOOT 80 #define CONFIG_SKIP_RELOCATE_UBOOT
81 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 81 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
82 82
83 /* 83 /*
84 * Size of malloc() pool 84 * Size of malloc() pool
85 */ 85 */
86 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) 86 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
87 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 87 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
88 88
89 #define CONFIG_BAUDRATE 115200 89 #define CONFIG_BAUDRATE 115200
90 90
91 #define CONFIG_SYS_AT91C_BRGR_DIVISOR 33 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK /(baudrate * 16) */ 91 #define CONFIG_SYS_AT91C_BRGR_DIVISOR 33 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK /(baudrate * 16) */
92 92
93 /* 93 /*
94 * Hardware drivers 94 * Hardware drivers
95 */ 95 */
96 96
97 /* define one of these to choose the DBGU, USART0 or USART1 as console */ 97 /* define one of these to choose the DBGU, USART0 or USART1 as console */
98 #define CONFIG_DBGU 98 #define CONFIG_DBGU
99 #undef CONFIG_USART0 99 #undef CONFIG_USART0
100 #undef CONFIG_USART1 100 #undef CONFIG_USART1
101 101
102 #undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ 102 #undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
103 103
104 #undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ 104 #undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
105 105
106 #define CONFIG_USB_OHCI_NEW 1 106 #define CONFIG_USB_OHCI_NEW 1
107 #define CONFIG_USB_KEYBOARD 1 107 #define CONFIG_USB_KEYBOARD 1
108 #define CONFIG_USB_STORAGE 1 108 #define CONFIG_USB_STORAGE 1
109 #define CONFIG_DOS_PARTITION 1 109 #define CONFIG_DOS_PARTITION 1
110 #define CONFIG_AT91C_PQFP_UHPBUG 1 110 #define CONFIG_AT91C_PQFP_UHPBUG 1
111 111
112 #undef CONFIG_SYS_USB_OHCI_BOARD_INIT 112 #undef CONFIG_SYS_USB_OHCI_BOARD_INIT
113 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 113 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
114 #define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE 114 #define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE
115 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200" 115 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200"
116 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 116 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
117 117
118 #undef CONFIG_HARD_I2C 118 #undef CONFIG_HARD_I2C
119 119
120 #ifdef CONFIG_HARD_I2C 120 #ifdef CONFIG_HARD_I2C
121 #define CONFIG_SYS_I2C_SPEED 0 /* not used */ 121 #define CONFIG_SYS_I2C_SPEED 0 /* not used */
122 #define CONFIG_SYS_I2C_SLAVE 0 /* not used */ 122 #define CONFIG_SYS_I2C_SLAVE 0 /* not used */
123 #define CONFIG_RTC_RS5C372A /* RICOH I2C RTC */ 123 #define CONFIG_RTC_RS5C372A /* RICOH I2C RTC */
124 #define CONFIG_SYS_I2C_RTC_ADDR 0x32 124 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
125 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 125 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
126 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 126 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
127 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 127 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
128 #endif 128 #endif
129 /* still about 20 kB free with this defined */ 129 /* still about 20 kB free with this defined */
130 #define CONFIG_SYS_LONGHELP 130 #define CONFIG_SYS_LONGHELP
131 131
132 #define CONFIG_BOOTDELAY 3 132 #define CONFIG_BOOTDELAY 3
133 133
134 #if !defined(CONFIG_HARD_I2C) 134 #if !defined(CONFIG_HARD_I2C)
135 #define CONFIG_TIMESTAMP 135 #define CONFIG_TIMESTAMP
136 #endif 136 #endif
137 137
138 138
139 /* 139 /*
140 * BOOTP options 140 * BOOTP options
141 */ 141 */
142 #define CONFIG_BOOTP_BOOTFILESIZE 142 #define CONFIG_BOOTP_BOOTFILESIZE
143 #define CONFIG_BOOTP_BOOTPATH 143 #define CONFIG_BOOTP_BOOTPATH
144 #define CONFIG_BOOTP_GATEWAY 144 #define CONFIG_BOOTP_GATEWAY
145 #define CONFIG_BOOTP_HOSTNAME 145 #define CONFIG_BOOTP_HOSTNAME
146 146
147 147
148 /* 148 /*
149 * Command line configuration. 149 * Command line configuration.
150 */ 150 */
151 #include <config_cmd_default.h> 151 #include <config_cmd_default.h>
152 152
153 #define CONFIG_CMD_DHCP 153 #define CONFIG_CMD_DHCP
154 #define CONFIG_CMD_NFS 154 #define CONFIG_CMD_NFS
155 #define CONFIG_CMD_SNTP 155 #define CONFIG_CMD_SNTP
156 156
157 #if defined(CONFIG_HARD_I2C) 157 #if defined(CONFIG_HARD_I2C)
158 158
159 #define CONFIG_CMD_DATE 159 #define CONFIG_CMD_DATE
160 #define CONFIG_CMD_EEPROM 160 #define CONFIG_CMD_EEPROM
161 #define CONFIG_CMD_I2C 161 #define CONFIG_CMD_I2C
162 #define CONFIG_CMD_MISC 162 #define CONFIG_CMD_MISC
163 163
164 #else 164 #else
165 165
166 #define CONFIG_CMD_USB 166 #define CONFIG_CMD_USB
167 #define CONFIG_CMD_CACHE 167 #define CONFIG_CMD_CACHE
168 168
169 #undef CONFIG_CMD_AUTOSCRIPT 169 #undef CONFIG_CMD_AUTOSCRIPT
170 #undef CONFIG_CMD_BDI 170 #undef CONFIG_CMD_BDI
171 #undef CONFIG_CMD_FPGA 171 #undef CONFIG_CMD_FPGA
172 #undef CONFIG_CMD_IMI 172 #undef CONFIG_CMD_IMI
173 #undef CONFIG_CMD_LOADS 173 #undef CONFIG_CMD_LOADS
174 #undef CONFIG_CMD_MISC 174 #undef CONFIG_CMD_MISC
175 175
176 #endif 176 #endif
177 177
178 178
179 #define CONFIG_SYS_LONGHELP 179 #define CONFIG_SYS_LONGHELP
180 180
181 #define CONFIG_NR_DRAM_BANKS 1 181 #define CONFIG_NR_DRAM_BANKS 1
182 #define PHYS_SDRAM 0x20000000 182 #define PHYS_SDRAM 0x20000000
183 #define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ 183 #define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
184 184
185 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 185 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
186 #define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 186 #define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
187 187
188 #define CONFIG_DRIVER_ETHER 188 #define CONFIG_DRIVER_ETHER
189 #define CONFIG_NET_RETRY_COUNT 20 189 #define CONFIG_NET_RETRY_COUNT 20
190 #undef CONFIG_AT91C_USE_RMII 190 #undef CONFIG_AT91C_USE_RMII
191 191
192 #define PHYS_FLASH_1 0x10000000 192 #define PHYS_FLASH_1 0x10000000
193 #define PHYS_FLASH_SIZE 0x1000000 /* 16 megs main flash */ 193 #define PHYS_FLASH_SIZE 0x1000000 /* 16 megs main flash */
194 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 194 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
195 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 195 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
196 #define CONFIG_SYS_MAX_FLASH_BANKS 1 196 #define CONFIG_SYS_MAX_FLASH_BANKS 1
197 #define CONFIG_SYS_MAX_FLASH_SECT 256 197 #define CONFIG_SYS_MAX_FLASH_SECT 256
198 #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ 198 #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
199 #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ 199 #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
200 #define CONFIG_SYS_FLASH_LOCK_TOUT (10*CONFIG_SYS_HZ) /* Timeout for Flash Set Lock Bit */ 200 #define CONFIG_SYS_FLASH_LOCK_TOUT (10*CONFIG_SYS_HZ) /* Timeout for Flash Set Lock Bit */
201 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (10*CONFIG_SYS_HZ) /* Timeout for Flash Clear Lock Bits */ 201 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (10*CONFIG_SYS_HZ) /* Timeout for Flash Clear Lock Bits */
202 #define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 202 #define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
203 203
204 #define CONFIG_ENV_IS_IN_FLASH 1 204 #define CONFIG_ENV_IS_IN_FLASH 1
205 #define CONFIG_ENV_OFFSET 0x20000 /* after u-boot.bin */ 205 #define CONFIG_ENV_OFFSET 0x20000 /* after u-boot.bin */
206 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_ENV_OFFSET) 206 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_ENV_OFFSET)
207 #define CONFIG_ENV_SIZE 0x20000 207 #define CONFIG_ENV_SIZE 0x20000
208 208
209 #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ 209 #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
210 210
211 #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } 211 #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
212 212
213 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 213 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
214 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 214 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
215 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 215 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
216 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 216 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
217 217
218 #define CONFIG_SYS_DEVICE_DEREGISTER /* needs device_deregister */ 218 #define CONFIG_SYS_DEVICE_DEREGISTER /* needs device_deregister */
219 #define LITTLEENDIAN 1 /* used by usb_ohci.c */ 219 #define LITTLEENDIAN 1 /* used by usb_ohci.c */
220 220
221 #define CONFIG_SYS_HZ 1000 221 #define CONFIG_SYS_HZ 1000
222 #define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK/2) /* AT91C_TC0_CMR is implicitly set to */ 222 #define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK/2) /* AT91C_TC0_CMR is implicitly set to */
223 /* AT91C_TC_TIMER_DIV1_CLOCK */ 223 /* AT91C_TC_TIMER_DIV1_CLOCK */
224 224
225 #define CONFIG_STACKSIZE (32*1024) /* regular stack */ 225 #define CONFIG_STACKSIZE (32*1024) /* regular stack */
226 226
227 #ifdef CONFIG_USE_IRQ 227 #ifdef CONFIG_USE_IRQ
228 #error CONFIG_USE_IRQ not supported 228 #error CONFIG_USE_IRQ not supported
229 #endif 229 #endif
230 230
231 #define CONFIG_SYS_DEVICE_NULLDEV 1 /* enble null device */ 231 #define CONFIG_SYS_DEVICE_NULLDEV 1 /* enble null device */
232 #undef CONFIG_SILENT_CONSOLE /* enable silent startup */ 232 #undef CONFIG_SILENT_CONSOLE /* enable silent startup */
233 233
234 #define CONFIG_AUTOBOOT_KEYED 234 #define CONFIG_AUTOBOOT_KEYED
235 #define CONFIG_AUTOBOOT_PROMPT \ 235 #define CONFIG_AUTOBOOT_PROMPT \
236 "Press SPACE to abort autoboot in %d seconds\n", bootdelay 236 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
237 #define CONFIG_AUTOBOOT_STOP_STR " " 237 #define CONFIG_AUTOBOOT_STOP_STR " "
238 #define CONFIG_AUTOBOOT_DELAY_STR "d" 238 #define CONFIG_AUTOBOOT_DELAY_STR "d"
239 239
240 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ 240 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
241 241
242 #endif /* __CONFIG_H */ 242 #endif /* __CONFIG_H */
243 243