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Commit d481c80d78f954133c035dae6c7d22de3625795d

Authored by Jean-Christophe PLAGNIOL-VILLARD
1 parent 4e170b1662
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

at91rm9200: rename lowlevel init value to CONFIG_SYS_ 

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Showing 6 changed files with 203 additions and 203 deletions Side-by-side Diff

board/m501sk/memsetup.S
Diff comments   View file @ d481c80
... ... @@ -41,50 +41,50 @@
41 41  
42 42 /* flash */
43 43 #define MC_PUIA 0xFFFFFF10
44   -#define MC_PUIA_VAL 0x00000000
  44 +#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
45 45 #define MC_PUP 0xFFFFFF50
46   -#define MC_PUP_VAL 0x00000000
  46 +#define CONFIG_SYS_MC_PUP_VAL 0x00000000
47 47 #define MC_PUER 0xFFFFFF54
48   -#define MC_PUER_VAL 0x00000000
  48 +#define CONFIG_SYS_MC_PUER_VAL 0x00000000
49 49 #define MC_ASR 0xFFFFFF04
50   -#define MC_ASR_VAL 0x00000000
  50 +#define CONFIG_SYS_MC_ASR_VAL 0x00000000
51 51 #define MC_AASR 0xFFFFFF08
52   -#define MC_AASR_VAL 0x00000000
  52 +#define CONFIG_SYS_MC_AASR_VAL 0x00000000
53 53 #define EBI_CFGR 0xFFFFFF64
54   -#define EBI_CFGR_VAL 0x00000000
  54 +#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
55 55 #define SMC_CSR0 0xFFFFFF70
56   -#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
  56 +#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
57 57  
58 58 /* clocks */
59 59 #define PLLAR 0xFFFFFC28
60   -#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
  60 +#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
61 61 #define PLLBR 0xFFFFFC2C
62   -#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
  62 +#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
63 63 #define MCKR 0xFFFFFC30
64 64 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
65   -#define MCKR_VAL 0x00000202
  65 +#define CONFIG_SYS_MCKR_VAL 0x00000202
66 66  
67 67 /* sdram */
68 68 #define PIOC_ASR 0xFFFFF870
69   -#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as Perip (D16/D31) */
  69 +#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as Perip (D16/D31) */
70 70 #define PIOC_BSR 0xFFFFF874
71   -#define PIOC_BSR_VAL 0x00000000
  71 +#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
72 72 #define PIOC_PDR 0xFFFFF804
73   -#define PIOC_PDR_VAL 0xFFFF0000
  73 +#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
74 74 #define EBI_CSA 0xFFFFFF60
75   -#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
  75 +#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
76 76 #define SDRC_CR 0xFFFFFF98
77   -#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */
78   -#define SDRAM 0x20000000 /* address of the SDRAM */
79   -#define SDRAM1 0x20000080 /* address of the SDRAM */
80   -#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
  77 +#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
  78 +#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
  79 +#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */
  80 +#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
81 81 #define SDRC_MR 0xFFFFFF90
82   -#define SDRC_MR_VAL 0x00000002 /* Precharge All */
83   -#define SDRC_MR_VAL1 0x00000004 /* refresh */
84   -#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
85   -#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
  82 +#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
  83 +#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
  84 +#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
  85 +#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
86 86 #define SDRC_TR 0xFFFFFF94
87   -#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
  87 +#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
88 88  
89 89 _TEXT_BASE:
90 90 .word TEXT_BASE
91 91  
92 92  
93 93  
94 94  
95 95  
96 96  
97 97  
98 98  
99 99  
100 100  
101 101  
102 102  
103 103  
104 104  
105 105  
106 106  
107 107  
108 108  
109 109  
... ... @@ -130,72 +130,72 @@
130 130  
131 131 SMRDATA:
132 132 .word MC_PUIA
133   - .word MC_PUIA_VAL
  133 + .word CONFIG_SYS_MC_PUIA_VAL
134 134 .word MC_PUP
135   - .word MC_PUP_VAL
  135 + .word CONFIG_SYS_MC_PUP_VAL
136 136 .word MC_PUER
137   - .word MC_PUER_VAL
  137 + .word CONFIG_SYS_MC_PUER_VAL
138 138 .word MC_ASR
139   - .word MC_ASR_VAL
  139 + .word CONFIG_SYS_MC_ASR_VAL
140 140 .word MC_AASR
141   - .word MC_AASR_VAL
  141 + .word CONFIG_SYS_MC_AASR_VAL
142 142 .word EBI_CFGR
143   - .word EBI_CFGR_VAL
  143 + .word CONFIG_SYS_EBI_CFGR_VAL
144 144 .word SMC_CSR0
145   - .word SMC_CSR0_VAL
  145 + .word CONFIG_SYS_SMC_CSR0_VAL
146 146 .word PLLAR
147   - .word PLLAR_VAL
  147 + .word CONFIG_SYS_PLLAR_VAL
148 148 .word PLLBR
149   - .word PLLBR_VAL
  149 + .word CONFIG_SYS_PLLBR_VAL
150 150 .word MCKR
151   - .word MCKR_VAL
  151 + .word CONFIG_SYS_MCKR_VAL
152 152 /* SMRDATA is 80 bytes long */
153 153 /* here there's a delay of 100 */
154 154 SMRDATA1:
155 155 .word PIOC_ASR
156   - .word PIOC_ASR_VAL
  156 + .word CONFIG_SYS_PIOC_ASR_VAL
157 157 .word PIOC_BSR
158   - .word PIOC_BSR_VAL
  158 + .word CONFIG_SYS_PIOC_BSR_VAL
159 159 .word PIOC_PDR
160   - .word PIOC_PDR_VAL
  160 + .word CONFIG_SYS_PIOC_PDR_VAL
161 161 .word EBI_CSA
162   - .word EBI_CSA_VAL
  162 + .word CONFIG_SYS_EBI_CSA_VAL
163 163 .word SDRC_CR
164   - .word SDRC_CR_VAL
  164 + .word CONFIG_SYS_SDRC_CR_VAL
165 165 .word SDRC_MR
166   - .word SDRC_MR_VAL
167   - .word SDRAM
168   - .word SDRAM_VAL
  166 + .word CONFIG_SYS_SDRC_MR_VAL
  167 + .word CONFIG_SYS_SDRAM
  168 + .word CONFIG_SYS_SDRAM_VAL
169 169 .word SDRC_MR
170   - .word SDRC_MR_VAL1
171   - .word SDRAM
172   - .word SDRAM_VAL
173   - .word SDRAM
174   - .word SDRAM_VAL
175   - .word SDRAM
176   - .word SDRAM_VAL
177   - .word SDRAM
178   - .word SDRAM_VAL
179   - .word SDRAM
180   - .word SDRAM_VAL
181   - .word SDRAM
182   - .word SDRAM_VAL
183   - .word SDRAM
184   - .word SDRAM_VAL
185   - .word SDRAM
186   - .word SDRAM_VAL
  170 + .word CONFIG_SYS_SDRC_MR_VAL1
  171 + .word CONFIG_SYS_SDRAM
  172 + .word CONFIG_SYS_SDRAM_VAL
  173 + .word CONFIG_SYS_SDRAM
  174 + .word CONFIG_SYS_SDRAM_VAL
  175 + .word CONFIG_SYS_SDRAM
  176 + .word CONFIG_SYS_SDRAM_VAL
  177 + .word CONFIG_SYS_SDRAM
  178 + .word CONFIG_SYS_SDRAM_VAL
  179 + .word CONFIG_SYS_SDRAM
  180 + .word CONFIG_SYS_SDRAM_VAL
  181 + .word CONFIG_SYS_SDRAM
  182 + .word CONFIG_SYS_SDRAM_VAL
  183 + .word CONFIG_SYS_SDRAM
  184 + .word CONFIG_SYS_SDRAM_VAL
  185 + .word CONFIG_SYS_SDRAM
  186 + .word CONFIG_SYS_SDRAM_VAL
187 187 .word SDRC_MR
188   - .word SDRC_MR_VAL2
189   - .word SDRAM1
190   - .word SDRAM_VAL
  188 + .word CONFIG_SYS_SDRC_MR_VAL2
  189 + .word CONFIG_SYS_SDRAM1
  190 + .word CONFIG_SYS_SDRAM_VAL
191 191 .word SDRC_TR
192   - .word SDRC_TR_VAL
193   - .word SDRAM
194   - .word SDRAM_VAL
  192 + .word CONFIG_SYS_SDRC_TR_VAL
  193 + .word CONFIG_SYS_SDRAM
  194 + .word CONFIG_SYS_SDRAM_VAL
195 195 .word SDRC_MR
196   - .word SDRC_MR_VAL3
197   - .word SDRAM
198   - .word SDRAM_VAL
  196 + .word CONFIG_SYS_SDRC_MR_VAL3
  197 + .word CONFIG_SYS_SDRAM
  198 + .word CONFIG_SYS_SDRAM_VAL
199 199 /* SMRDATA1 is 176 bytes long */
200 200 #endif /* CONFIG_BOOTBINFUNC */
cpu/arm920t/at91rm9200/lowlevel_init.S
Diff comments   View file @ d481c80
... ... @@ -135,72 +135,72 @@
135 135  
136 136 SMRDATA:
137 137 .word MC_PUIA
138   - .word MC_PUIA_VAL
  138 + .word CONFIG_SYS_MC_PUIA_VAL
139 139 .word MC_PUP
140   - .word MC_PUP_VAL
  140 + .word CONFIG_SYS_MC_PUP_VAL
141 141 .word MC_PUER
142   - .word MC_PUER_VAL
  142 + .word CONFIG_SYS_MC_PUER_VAL
143 143 .word MC_ASR
144   - .word MC_ASR_VAL
  144 + .word CONFIG_SYS_MC_ASR_VAL
145 145 .word MC_AASR
146   - .word MC_AASR_VAL
  146 + .word CONFIG_SYS_MC_AASR_VAL
147 147 .word EBI_CFGR
148   - .word EBI_CFGR_VAL
  148 + .word CONFIG_SYS_EBI_CFGR_VAL
149 149 .word SMC_CSR0
150   - .word SMC_CSR0_VAL
  150 + .word CONFIG_SYS_SMC_CSR0_VAL
151 151 .word PLLAR
152   - .word PLLAR_VAL
  152 + .word CONFIG_SYS_PLLAR_VAL
153 153 .word PLLBR
154   - .word PLLBR_VAL
  154 + .word CONFIG_SYS_PLLBR_VAL
155 155 .word MCKR
156   - .word MCKR_VAL
  156 + .word CONFIG_SYS_MCKR_VAL
157 157 /* SMRDATA is 80 bytes long */
158 158 /* here there's a delay of 100 */
159 159 SMRDATA1:
160 160 .word PIOC_ASR
161   - .word PIOC_ASR_VAL
  161 + .word CONFIG_SYS_PIOC_ASR_VAL
162 162 .word PIOC_BSR
163   - .word PIOC_BSR_VAL
  163 + .word CONFIG_SYS_PIOC_BSR_VAL
164 164 .word PIOC_PDR
165   - .word PIOC_PDR_VAL
  165 + .word CONFIG_SYS_PIOC_PDR_VAL
166 166 .word EBI_CSA
167   - .word EBI_CSA_VAL
  167 + .word CONFIG_SYS_EBI_CSA_VAL
168 168 .word SDRC_CR
169   - .word SDRC_CR_VAL
  169 + .word CONFIG_SYS_SDRC_CR_VAL
170 170 .word SDRC_MR
171   - .word SDRC_MR_VAL
172   - .word SDRAM
173   - .word SDRAM_VAL
  171 + .word CONFIG_SYS_SDRC_MR_VAL
  172 + .word CONFIG_SYS_SDRAM
  173 + .word CONFIG_SYS_SDRAM_VAL
174 174 .word SDRC_MR
175   - .word SDRC_MR_VAL1
176   - .word SDRAM
177   - .word SDRAM_VAL
178   - .word SDRAM
179   - .word SDRAM_VAL
180   - .word SDRAM
181   - .word SDRAM_VAL
182   - .word SDRAM
183   - .word SDRAM_VAL
184   - .word SDRAM
185   - .word SDRAM_VAL
186   - .word SDRAM
187   - .word SDRAM_VAL
188   - .word SDRAM
189   - .word SDRAM_VAL
190   - .word SDRAM
191   - .word SDRAM_VAL
  175 + .word CONFIG_SYS_SDRC_MR_VAL1
  176 + .word CONFIG_SYS_SDRAM
  177 + .word CONFIG_SYS_SDRAM_VAL
  178 + .word CONFIG_SYS_SDRAM
  179 + .word CONFIG_SYS_SDRAM_VAL
  180 + .word CONFIG_SYS_SDRAM
  181 + .word CONFIG_SYS_SDRAM_VAL
  182 + .word CONFIG_SYS_SDRAM
  183 + .word CONFIG_SYS_SDRAM_VAL
  184 + .word CONFIG_SYS_SDRAM
  185 + .word CONFIG_SYS_SDRAM_VAL
  186 + .word CONFIG_SYS_SDRAM
  187 + .word CONFIG_SYS_SDRAM_VAL
  188 + .word CONFIG_SYS_SDRAM
  189 + .word CONFIG_SYS_SDRAM_VAL
  190 + .word CONFIG_SYS_SDRAM
  191 + .word CONFIG_SYS_SDRAM_VAL
192 192 .word SDRC_MR
193   - .word SDRC_MR_VAL2
194   - .word SDRAM1
195   - .word SDRAM_VAL
  193 + .word CONFIG_SYS_SDRC_MR_VAL2
  194 + .word CONFIG_SYS_SDRAM1
  195 + .word CONFIG_SYS_SDRAM_VAL
196 196 .word SDRC_TR
197   - .word SDRC_TR_VAL
198   - .word SDRAM
199   - .word SDRAM_VAL
  197 + .word CONFIG_SYS_SDRC_TR_VAL
  198 + .word CONFIG_SYS_SDRAM
  199 + .word CONFIG_SYS_SDRAM_VAL
200 200 .word SDRC_MR
201   - .word SDRC_MR_VAL3
202   - .word SDRAM
203   - .word SDRAM_VAL
  201 + .word CONFIG_SYS_SDRC_MR_VAL3
  202 + .word CONFIG_SYS_SDRAM
  203 + .word CONFIG_SYS_SDRAM_VAL
204 204 /* SMRDATA1 is 176 bytes long */
205 205 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
include/configs/at91rm9200dk.h
Diff comments   View file @ d481c80
... ... @@ -45,33 +45,33 @@
45 45 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
46 46 #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
47 47 /* flash */
48   -#define MC_PUIA_VAL 0x00000000
49   -#define MC_PUP_VAL 0x00000000
50   -#define MC_PUER_VAL 0x00000000
51   -#define MC_ASR_VAL 0x00000000
52   -#define MC_AASR_VAL 0x00000000
53   -#define EBI_CFGR_VAL 0x00000000
54   -#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
  48 +#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
  49 +#define CONFIG_SYS_MC_PUP_VAL 0x00000000
  50 +#define CONFIG_SYS_MC_PUER_VAL 0x00000000
  51 +#define CONFIG_SYS_MC_ASR_VAL 0x00000000
  52 +#define CONFIG_SYS_MC_AASR_VAL 0x00000000
  53 +#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
  54 +#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
55 55  
56 56 /* clocks */
57   -#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
58   -#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
59   -#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
  57 +#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
  58 +#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
  59 +#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
60 60  
61 61 /* sdram */
62   -#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
63   -#define PIOC_BSR_VAL 0x00000000
64   -#define PIOC_PDR_VAL 0xFFFF0000
65   -#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
66   -#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */
67   -#define SDRAM 0x20000000 /* address of the SDRAM */
68   -#define SDRAM1 0x20000080 /* address of the SDRAM */
69   -#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
70   -#define SDRC_MR_VAL 0x00000002 /* Precharge All */
71   -#define SDRC_MR_VAL1 0x00000004 /* refresh */
72   -#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
73   -#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
74   -#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
  62 +#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
  63 +#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
  64 +#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
  65 +#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
  66 +#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
  67 +#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
  68 +#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */
  69 +#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
  70 +#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
  71 +#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
  72 +#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
  73 +#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
  74 +#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
75 75 #else
76 76 #define CONFIG_SKIP_RELOCATE_UBOOT
77 77 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
include/configs/cmc_pu2.h
Diff comments   View file @ d481c80
... ... @@ -44,33 +44,33 @@
44 44 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
45 45 #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
46 46 /* flash */
47   -#define MC_PUIA_VAL 0x00000000
48   -#define MC_PUP_VAL 0x00000000
49   -#define MC_PUER_VAL 0x00000000
50   -#define MC_ASR_VAL 0x00000000
51   -#define MC_AASR_VAL 0x00000000
52   -#define EBI_CFGR_VAL 0x00000000
53   -#define SMC_CSR0_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */
  47 +#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
  48 +#define CONFIG_SYS_MC_PUP_VAL 0x00000000
  49 +#define CONFIG_SYS_MC_PUER_VAL 0x00000000
  50 +#define CONFIG_SYS_MC_ASR_VAL 0x00000000
  51 +#define CONFIG_SYS_MC_AASR_VAL 0x00000000
  52 +#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
  53 +#define CONFIG_SYS_SMC_CSR0_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */
54 54  
55 55 /* clocks */
56   -#define PLLAR_VAL 0x2026BE04 /* 179,712 MHz for PCK */
57   -#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
58   -#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */
  56 +#define CONFIG_SYS_PLLAR_VAL 0x2026BE04 /* 179,712 MHz for PCK */
  57 +#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
  58 +#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */
59 59  
60 60 /* sdram */
61   -#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
62   -#define PIOC_BSR_VAL 0x00000000
63   -#define PIOC_PDR_VAL 0xFFFF0000
64   -#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
65   -#define SDRC_CR_VAL 0x3399c1d4 /* set up the SDRAM */
66   -#define SDRAM 0x20000000 /* address of the SDRAM */
67   -#define SDRAM1 0x20000080 /* address of the SDRAM */
68   -#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
69   -#define SDRC_MR_VAL 0x00000002 /* Precharge All */
70   -#define SDRC_MR_VAL1 0x00000004 /* refresh */
71   -#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
72   -#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
73   -#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
  61 +#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
  62 +#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
  63 +#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
  64 +#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
  65 +#define CONFIG_SYS_SDRC_CR_VAL 0x3399c1d4 /* set up the CONFIG_SYS_SDRAM */
  66 +#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
  67 +#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */
  68 +#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
  69 +#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
  70 +#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
  71 +#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
  72 +#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
  73 +#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
74 74 #else
75 75 #define CONFIG_SKIP_RELOCATE_UBOOT
76 76 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
include/configs/csb637.h
Diff comments   View file @ d481c80
... ... @@ -45,33 +45,33 @@
45 45 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
46 46 #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
47 47 /* flash */
48   -#define MC_PUIA_VAL 0x00000000
49   -#define MC_PUP_VAL 0x00000000
50   -#define MC_PUER_VAL 0x00000000
51   -#define MC_ASR_VAL 0x00000000
52   -#define MC_AASR_VAL 0x00000000
53   -#define EBI_CFGR_VAL 0x00000000
54   -#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
  48 +#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
  49 +#define CONFIG_SYS_MC_PUP_VAL 0x00000000
  50 +#define CONFIG_SYS_MC_PUER_VAL 0x00000000
  51 +#define CONFIG_SYS_MC_ASR_VAL 0x00000000
  52 +#define CONFIG_SYS_MC_AASR_VAL 0x00000000
  53 +#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
  54 +#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
55 55  
56 56 /* clocks */
57   -#define PLLAR_VAL 0x2031BE01 /* 184.320000 MHz for PCK */
58   -#define PLLBR_VAL 0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */
59   -#define MCKR_VAL 0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */
  57 +#define CONFIG_SYS_PLLAR_VAL 0x2031BE01 /* 184.320000 MHz for PCK */
  58 +#define CONFIG_SYS_PLLBR_VAL 0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */
  59 +#define CONFIG_SYS_MCKR_VAL 0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */
60 60  
61 61 /* sdram */
62   -#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
63   -#define PIOC_BSR_VAL 0x00000000
64   -#define PIOC_PDR_VAL 0xFFFF0000
65   -#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
66   -#define SDRC_CR_VAL 0x21914159 /* set up the SDRAM */
67   -#define SDRAM 0x20000000 /* address of the SDRAM */
68   -#define SDRAM1 0x20000080 /* address of the SDRAM */
69   -#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
70   -#define SDRC_MR_VAL 0x00000002 /* Precharge All */
71   -#define SDRC_MR_VAL1 0x00000004 /* refresh */
72   -#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
73   -#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
74   -#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
  62 +#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
  63 +#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
  64 +#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
  65 +#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
  66 +#define CONFIG_SYS_SDRC_CR_VAL 0x21914159 /* set up the CONFIG_SYS_SDRAM */
  67 +#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
  68 +#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */
  69 +#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
  70 +#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
  71 +#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
  72 +#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
  73 +#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
  74 +#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
75 75 #else
76 76 #define CONFIG_SKIP_RELOCATE_UBOOT
77 77 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
include/configs/mp2usb.h
Diff comments   View file @ d481c80
... ... @@ -49,33 +49,33 @@
49 49 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
50 50 #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
51 51 /* flash */
52   -#define MC_PUIA_VAL 0x00000000
53   -#define MC_PUP_VAL 0x00000000
54   -#define MC_PUER_VAL 0x00000000
55   -#define MC_ASR_VAL 0x00000000
56   -#define MC_AASR_VAL 0x00000000
57   -#define EBI_CFGR_VAL 0x00000000
58   -#define SMC_CSR0_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */
  52 +#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
  53 +#define CONFIG_SYS_MC_PUP_VAL 0x00000000
  54 +#define CONFIG_SYS_MC_PUER_VAL 0x00000000
  55 +#define CONFIG_SYS_MC_ASR_VAL 0x00000000
  56 +#define CONFIG_SYS_MC_AASR_VAL 0x00000000
  57 +#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
  58 +#define CONFIG_SYS_SMC_CSR0_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */
59 59  
60 60 /* clocks */
61   -#define PLLAR_VAL 0x20263E04 /* 180 MHz for PCK */
62   -#define PLLBR_VAL 0x1048bE0E /* 48 MHz (divider by 2 for USB) */
63   -#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 60MHz from PLLA */
  61 +#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 180 MHz for PCK */
  62 +#define CONFIG_SYS_PLLBR_VAL 0x1048bE0E /* 48 MHz (divider by 2 for USB) */
  63 +#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 60MHz from PLLA */
64 64  
65 65 /* sdram */
66   -#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
67   -#define PIOC_BSR_VAL 0x00000000
68   -#define PIOC_PDR_VAL 0xFFFF0000
69   -#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
70   -#define SDRC_CR_VAL 0x3211295A /* set up the SDRAM */
71   -#define SDRAM 0x20000000 /* address of the SDRAM */
72   -#define SDRAM1 0x20000020 /* address of the SDRAM */
73   -#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
74   -#define SDRC_MR_VAL 0x00000002 /* Precharge All */
75   -#define SDRC_MR_VAL1 0x00000004 /* refresh */
76   -#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
77   -#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
78   -#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
  66 +#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
  67 +#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
  68 +#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
  69 +#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
  70 +#define CONFIG_SYS_SDRC_CR_VAL 0x3211295A /* set up the CONFIG_SYS_SDRAM */
  71 +#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
  72 +#define CONFIG_SYS_SDRAM1 0x20000020 /* address of the CONFIG_SYS_SDRAM */
  73 +#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
  74 +#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
  75 +#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
  76 +#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
  77 +#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
  78 +#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
79 79 #else
80 80 #define CONFIG_SKIP_RELOCATE_UBOOT
81 81 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */