Eric Lee / smarc-uboot

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Commit d5f8a6ddd41dee0de17888f8b5334fe1b636c4ca

Authored by Tom Rini
2 parents ee860c60d2 fb5368789a
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

Showing 70 changed files Side-by-side Diff

arch/arm/include/asm/arch-fsl-lsch3/config.h
Diff comments   View file @ d5f8a6d
... ... @@ -43,7 +43,11 @@
43 43 /* DDR */
44 44 #define CONFIG_SYS_FSL_DDR_LE
45 45 #define CONFIG_VERY_BIG_RAM
  46 +#ifdef CONFIG_SYS_FSL_DDR4
  47 +#define CONFIG_SYS_FSL_DDRC_GEN4
  48 +#else
46 49 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
  50 +#endif
47 51 #define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
48 52 #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
49 53 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
arch/arm/include/asm/io.h
Diff comments   View file @ d5f8a6d
... ... @@ -136,6 +136,7 @@
136 136 * TODO: The kernel offers some more advanced versions of barriers, it might
137 137 * have some advantages to use them instead of the simple one here.
138 138 */
  139 +#define mb() asm volatile("dsb sy" : : : "memory")
139 140 #define dmb() __asm__ __volatile__ ("" : : : "memory")
140 141 #define __iormb() dmb()
141 142 #define __iowmb() dmb()
arch/powerpc/cpu/mpc83xx/cpu.c
Diff comments   View file @ d5f8a6d
... ... @@ -20,7 +20,7 @@
20 20 #include <netdev.h>
21 21 #include <fsl_esdhc.h>
22 22 #if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_MPC831x)
23   -#include <asm/immap_qe.h>
  23 +#include <linux/immap_qe.h>
24 24 #include <asm/io.h>
25 25 #endif
26 26  
arch/powerpc/cpu/mpc83xx/fdt.c
Diff comments   View file @ d5f8a6d
... ... @@ -18,7 +18,7 @@
18 18  
19 19 #if defined(CONFIG_BOOTCOUNT_LIMIT) && \
20 20 (defined(CONFIG_QE) && !defined(CONFIG_MPC831x))
21   -#include <asm/immap_qe.h>
  21 +#include <linux/immap_qe.h>
22 22  
23 23 void fdt_fixup_muram (void *blob)
24 24 {
arch/powerpc/cpu/mpc85xx/cpu_init.c
Diff comments   View file @ d5f8a6d
... ... @@ -200,7 +200,7 @@
200 200  
201 201 #ifdef CONFIG_SYS_FSL_CPC
202 202 #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
203   -static void disable_cpc_sram(void)
  203 +void disable_cpc_sram(void)
204 204 {
205 205 int i;
206 206  
... ... @@ -251,7 +251,7 @@
251 251 }
252 252 #endif
253 253  
254   -static void enable_cpc(void)
  254 +void enable_cpc(void)
255 255 {
256 256 int i;
257 257 u32 size = 0;
... ... @@ -306,6 +306,7 @@
306 306 #else
307 307 #define enable_cpc()
308 308 #define invalidate_cpc()
  309 +#define disable_cpc_sram()
309 310 #endif /* CONFIG_SYS_FSL_CPC */
310 311  
311 312 /*
... ... @@ -520,7 +521,8 @@
520 521 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
521 522 u32 type = in_be32(&gur->tp_ityp[idx]);
522 523  
523   - if (type & TP_ITYP_AV)
  524 + if ((type & TP_ITYP_AV) &&
  525 + TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
524 526 cluster_valid = 1;
525 527 }
526 528  
527 529  
528 530  
529 531  
530 532  
... ... @@ -545,89 +547,16 @@
545 547  
546 548 /*
547 549 * Initialize L2 as cache.
548   - *
549   - * The newer 8548, etc, parts have twice as much cache, but
550   - * use the same bit-encoding as the older 8555, etc, parts.
551   - *
552 550 */
553   -int cpu_init_r(void)
  551 +int l2cache_init(void)
554 552 {
555 553 __maybe_unused u32 svr = get_svr();
556   -#ifdef CONFIG_SYS_LBC_LCRR
557   - fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
558   -#endif
559 554 #ifdef CONFIG_L2_CACHE
560 555 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
561 556 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
562 557 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
563 558 #endif
564   -#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
565   - extern int spin_table_compat;
566   - const char *spin;
567   -#endif
568   -#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
569   - ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
570   -#endif
571   -#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
572   - defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
573   - /*
574   - * CPU22 and NMG_CPU_A011 share the same workaround.
575   - * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
576   - * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
577   - * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
578   - * fixed in 2.0. NMG_CPU_A011 is activated by default and can
579   - * be disabled by hwconfig with syntax:
580   - *
581   - * fsl_cpu_a011:disable
582   - */
583   - extern int enable_cpu_a011_workaround;
584   -#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
585   - enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
586   -#else
587   - char buffer[HWCONFIG_BUFFER_SIZE];
588   - char *buf = NULL;
589   - int n, res;
590 559  
591   - n = getenv_f("hwconfig", buffer, sizeof(buffer));
592   - if (n > 0)
593   - buf = buffer;
594   -
595   - res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
596   - if (res > 0)
597   - enable_cpu_a011_workaround = 0;
598   - else {
599   - if (n >= HWCONFIG_BUFFER_SIZE) {
600   - printf("fsl_cpu_a011 was not found. hwconfig variable "
601   - "may be too long\n");
602   - }
603   - enable_cpu_a011_workaround =
604   - (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
605   - (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
606   - }
607   -#endif
608   - if (enable_cpu_a011_workaround) {
609   - flush_dcache();
610   - mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
611   - sync();
612   - }
613   -#endif
614   -#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
615   - /*
616   - * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
617   - * in write shadow mode. Checking DCWS before setting SPR 976.
618   - */
619   - if (mfspr(L1CSR2) & L1CSR2_DCWS)
620   - mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
621   -#endif
622   -
623   -#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
624   - spin = getenv("spin_table_compat");
625   - if (spin && (*spin == 'n'))
626   - spin_table_compat = 0;
627   - else
628   - spin_table_compat = 1;
629   -#endif
630   -
631 560 puts ("L2: ");
632 561  
633 562 #if defined(CONFIG_L2_CACHE)
... ... @@ -751,6 +680,89 @@
751 680 puts("disabled\n");
752 681 #endif
753 682  
  683 + return 0;
  684 +}
  685 +
  686 +/*
  687 + *
  688 + * The newer 8548, etc, parts have twice as much cache, but
  689 + * use the same bit-encoding as the older 8555, etc, parts.
  690 + *
  691 + */
  692 +int cpu_init_r(void)
  693 +{
  694 + __maybe_unused u32 svr = get_svr();
  695 +#ifdef CONFIG_SYS_LBC_LCRR
  696 + fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
  697 +#endif
  698 +#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
  699 + extern int spin_table_compat;
  700 + const char *spin;
  701 +#endif
  702 +#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
  703 + ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
  704 +#endif
  705 +#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
  706 + defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
  707 + /*
  708 + * CPU22 and NMG_CPU_A011 share the same workaround.
  709 + * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
  710 + * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
  711 + * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
  712 + * fixed in 2.0. NMG_CPU_A011 is activated by default and can
  713 + * be disabled by hwconfig with syntax:
  714 + *
  715 + * fsl_cpu_a011:disable
  716 + */
  717 + extern int enable_cpu_a011_workaround;
  718 +#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
  719 + enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
  720 +#else
  721 + char buffer[HWCONFIG_BUFFER_SIZE];
  722 + char *buf = NULL;
  723 + int n, res;
  724 +
  725 + n = getenv_f("hwconfig", buffer, sizeof(buffer));
  726 + if (n > 0)
  727 + buf = buffer;
  728 +
  729 + res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
  730 + if (res > 0) {
  731 + enable_cpu_a011_workaround = 0;
  732 + } else {
  733 + if (n >= HWCONFIG_BUFFER_SIZE) {
  734 + printf("fsl_cpu_a011 was not found. hwconfig variable "
  735 + "may be too long\n");
  736 + }
  737 + enable_cpu_a011_workaround =
  738 + (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
  739 + (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
  740 + }
  741 +#endif
  742 + if (enable_cpu_a011_workaround) {
  743 + flush_dcache();
  744 + mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
  745 + sync();
  746 + }
  747 +#endif
  748 +#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
  749 + /*
  750 + * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
  751 + * in write shadow mode. Checking DCWS before setting SPR 976.
  752 + */
  753 + if (mfspr(L1CSR2) & L1CSR2_DCWS)
  754 + mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
  755 +#endif
  756 +
  757 +#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
  758 + spin = getenv("spin_table_compat");
  759 + if (spin && (*spin == 'n'))
  760 + spin_table_compat = 0;
  761 + else
  762 + spin_table_compat = 1;
  763 +#endif
  764 +
  765 + l2cache_init();
754 766 #if defined(CONFIG_RAMBOOT_PBL)
755 767 disable_cpc_sram();
756 768 #endif
arch/powerpc/cpu/mpc85xx/fdt.c
Diff comments   View file @ d5f8a6d
... ... @@ -612,6 +612,51 @@
612 612 #define fdt_fixup_usb(x)
613 613 #endif
614 614  
  615 +#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T4240) || \
  616 + defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
  617 +void fdt_fixup_dma3(void *blob)
  618 +{
  619 + /* the 3rd DMA is not functional if SRIO2 is chosen */
  620 + int nodeoff;
  621 + ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  622 +
  623 +#define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
  624 +#if defined(CONFIG_PPC_T2080)
  625 + u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
  626 + FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  627 + srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  628 +
  629 + switch (srds_prtcl_s2) {
  630 + case 0x29:
  631 + case 0x2d:
  632 + case 0x2e:
  633 +#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
  634 + defined(CONFIG_PPC_T4080)
  635 + u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
  636 + FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
  637 + srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
  638 +
  639 + switch (srds_prtcl_s4) {
  640 + case 6:
  641 + case 8:
  642 + case 14:
  643 + case 16:
  644 +#endif
  645 + nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,elo3-dma",
  646 + CONFIG_SYS_ELO3_DMA3);
  647 + if (nodeoff > 0)
  648 + fdt_status_disabled(blob, nodeoff);
  649 + else
  650 + printf("WARNING: unable to disable dma3\n");
  651 + break;
  652 + default:
  653 + break;
  654 + }
  655 +}
  656 +#else
  657 +#define fdt_fixup_dma3(x)
  658 +#endif
  659 +
615 660 #if defined(CONFIG_PPC_T1040)
616 661 static void fdt_fixup_l2_switch(void *blob)
617 662 {
... ... @@ -778,6 +823,8 @@
778 823 fdt_fixup_usb(blob);
779 824  
780 825 fdt_fixup_l2_switch(blob);
  826 +
  827 + fdt_fixup_dma3(blob);
781 828 }
782 829  
783 830 /*
arch/powerpc/cpu/mpc8xxx/cpu.c
Diff comments   View file @ d5f8a6d
... ... @@ -65,7 +65,6 @@
65 65 CPU_TYPE_ENTRY(T4080, T4080, 4),
66 66 CPU_TYPE_ENTRY(B4860, B4860, 0),
67 67 CPU_TYPE_ENTRY(G4860, G4860, 0),
68   - CPU_TYPE_ENTRY(G4060, G4060, 0),
69 68 CPU_TYPE_ENTRY(B4440, B4440, 0),
70 69 CPU_TYPE_ENTRY(B4460, B4460, 0),
71 70 CPU_TYPE_ENTRY(G4440, G4440, 0),
arch/powerpc/include/asm/cache.h
Diff comments   View file @ d5f8a6d
... ... @@ -57,6 +57,12 @@
57 57 #endif /* CONFIG_SYS_INIT_RAM_LOCK */
58 58 #endif /* __ASSEMBLY__ */
59 59  
  60 +#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
  61 +int l2cache_init(void);
  62 +void enable_cpc(void);
  63 +void disable_cpc_sram(void);
  64 +#endif
  65 +
60 66 /* prep registers for L2 */
61 67 #define CACHECRBA 0x80000823 /* Cache configuration register address */
62 68 #define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */
arch/powerpc/include/asm/immap_85xx.h
Diff comments   View file @ d5f8a6d
... ... @@ -2905,6 +2905,8 @@
2905 2905 #endif
2906 2906 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
2907 2907 #define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
  2908 +#define CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000
  2909 +#define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000
2908 2910 #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
2909 2911 #define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000
2910 2912 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
... ... @@ -3090,6 +3092,10 @@
3090 3092 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
3091 3093 #define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
3092 3094 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
  3095 +#define CONFIG_SYS_FSL_CORENET_SERDES3_ADDR \
  3096 + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET)
  3097 +#define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \
  3098 + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET)
3093 3099 #define CONFIG_SYS_MPC85xx_USB1_ADDR \
3094 3100 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET)
3095 3101 #define CONFIG_SYS_MPC85xx_USB2_ADDR \
arch/powerpc/include/asm/immap_qe.h
View file @ d5f8a6d
1   -/*
2   - * QUICC Engine (QE) Internal Memory Map.
3   - * The Internal Memory Map for devices with QE on them. This
4   - * is the superset of all QE devices (8360, etc.).
5   - *
6   - * Copyright (c) 2006-2009, 2011 Freescale Semiconductor, Inc.
7   - * Author: Shlomi Gridih <gridish@freescale.com>
8   - *
9   - * SPDX-License-Identifier: GPL-2.0+
10   - */
11   -
12   -#ifndef __IMMAP_QE_H__
13   -#define __IMMAP_QE_H__
14   -
15   -#ifdef CONFIG_MPC83xx
16   -#if defined(CONFIG_MPC8360)
17   -#define QE_MURAM_SIZE 0xc000UL
18   -#define MAX_QE_RISC 2
19   -#define QE_NUM_OF_SNUM 28
20   -#elif defined(CONFIG_MPC832x) || defined(CONFIG_MPC8309)
21   -#define QE_MURAM_SIZE 0x4000UL
22   -#define MAX_QE_RISC 1
23   -#define QE_NUM_OF_SNUM 28
24   -#endif
25   -#endif
26   -
27   -/* QE I-RAM */
28   -typedef struct qe_iram {
29   - u32 iadd; /* I-RAM Address Register */
30   - u32 idata; /* I-RAM Data Register */
31   - u8 res0[0x4];
32   - u32 iready;
33   - u8 res1[0x70];
34   -} __attribute__ ((packed)) qe_iram_t;
35   -
36   -/* QE Interrupt Controller */
37   -typedef struct qe_ic {
38   - u32 qicr;
39   - u32 qivec;
40   - u32 qripnr;
41   - u32 qipnr;
42   - u32 qipxcc;
43   - u32 qipycc;
44   - u32 qipwcc;
45   - u32 qipzcc;
46   - u32 qimr;
47   - u32 qrimr;
48   - u32 qicnr;
49   - u8 res0[0x4];
50   - u32 qiprta;
51   - u32 qiprtb;
52   - u8 res1[0x4];
53   - u32 qricr;
54   - u8 res2[0x20];
55   - u32 qhivec;
56   - u8 res3[0x1C];
57   -} __attribute__ ((packed)) qe_ic_t;
58   -
59   -/* Communications Processor */
60   -typedef struct cp_qe {
61   - u32 cecr; /* QE command register */
62   - u32 ceccr; /* QE controller configuration register */
63   - u32 cecdr; /* QE command data register */
64   - u8 res0[0xA];
65   - u16 ceter; /* QE timer event register */
66   - u8 res1[0x2];
67   - u16 cetmr; /* QE timers mask register */
68   - u32 cetscr; /* QE time-stamp timer control register */
69   - u32 cetsr1; /* QE time-stamp register 1 */
70   - u32 cetsr2; /* QE time-stamp register 2 */
71   - u8 res2[0x8];
72   - u32 cevter; /* QE virtual tasks event register */
73   - u32 cevtmr; /* QE virtual tasks mask register */
74   - u16 cercr; /* QE RAM control register */
75   - u8 res3[0x2];
76   - u8 res4[0x24];
77   - u16 ceexe1; /* QE external request 1 event register */
78   - u8 res5[0x2];
79   - u16 ceexm1; /* QE external request 1 mask register */
80   - u8 res6[0x2];
81   - u16 ceexe2; /* QE external request 2 event register */
82   - u8 res7[0x2];
83   - u16 ceexm2; /* QE external request 2 mask register */
84   - u8 res8[0x2];
85   - u16 ceexe3; /* QE external request 3 event register */
86   - u8 res9[0x2];
87   - u16 ceexm3; /* QE external request 3 mask register */
88   - u8 res10[0x2];
89   - u16 ceexe4; /* QE external request 4 event register */
90   - u8 res11[0x2];
91   - u16 ceexm4; /* QE external request 4 mask register */
92   - u8 res12[0x2];
93   - u8 res13[0x280];
94   -} __attribute__ ((packed)) cp_qe_t;
95   -
96   -/* QE Multiplexer */
97   -typedef struct qe_mux {
98   - u32 cmxgcr; /* CMX general clock route register */
99   - u32 cmxsi1cr_l; /* CMX SI1 clock route low register */
100   - u32 cmxsi1cr_h; /* CMX SI1 clock route high register */
101   - u32 cmxsi1syr; /* CMX SI1 SYNC route register */
102   - u32 cmxucr1; /* CMX UCC1, UCC3 clock route register */
103   - u32 cmxucr2; /* CMX UCC5, UCC7 clock route register */
104   - u32 cmxucr3; /* CMX UCC2, UCC4 clock route register */
105   - u32 cmxucr4; /* CMX UCC6, UCC8 clock route register */
106   - u32 cmxupcr; /* CMX UPC clock route register */
107   - u8 res0[0x1C];
108   -} __attribute__ ((packed)) qe_mux_t;
109   -
110   -/* QE Timers */
111   -typedef struct qe_timers {
112   - u8 gtcfr1; /* Timer 1 2 global configuration register */
113   - u8 res0[0x3];
114   - u8 gtcfr2; /* Timer 3 4 global configuration register */
115   - u8 res1[0xB];
116   - u16 gtmdr1; /* Timer 1 mode register */
117   - u16 gtmdr2; /* Timer 2 mode register */
118   - u16 gtrfr1; /* Timer 1 reference register */
119   - u16 gtrfr2; /* Timer 2 reference register */
120   - u16 gtcpr1; /* Timer 1 capture register */
121   - u16 gtcpr2; /* Timer 2 capture register */
122   - u16 gtcnr1; /* Timer 1 counter */
123   - u16 gtcnr2; /* Timer 2 counter */
124   - u16 gtmdr3; /* Timer 3 mode register */
125   - u16 gtmdr4; /* Timer 4 mode register */
126   - u16 gtrfr3; /* Timer 3 reference register */
127   - u16 gtrfr4; /* Timer 4 reference register */
128   - u16 gtcpr3; /* Timer 3 capture register */
129   - u16 gtcpr4; /* Timer 4 capture register */
130   - u16 gtcnr3; /* Timer 3 counter */
131   - u16 gtcnr4; /* Timer 4 counter */
132   - u16 gtevr1; /* Timer 1 event register */
133   - u16 gtevr2; /* Timer 2 event register */
134   - u16 gtevr3; /* Timer 3 event register */
135   - u16 gtevr4; /* Timer 4 event register */
136   - u16 gtps; /* Timer 1 prescale register */
137   - u8 res2[0x46];
138   -} __attribute__ ((packed)) qe_timers_t;
139   -
140   -/* BRG */
141   -typedef struct qe_brg {
142   - u32 brgc1; /* BRG1 configuration register */
143   - u32 brgc2; /* BRG2 configuration register */
144   - u32 brgc3; /* BRG3 configuration register */
145   - u32 brgc4; /* BRG4 configuration register */
146   - u32 brgc5; /* BRG5 configuration register */
147   - u32 brgc6; /* BRG6 configuration register */
148   - u32 brgc7; /* BRG7 configuration register */
149   - u32 brgc8; /* BRG8 configuration register */
150   - u32 brgc9; /* BRG9 configuration register */
151   - u32 brgc10; /* BRG10 configuration register */
152   - u32 brgc11; /* BRG11 configuration register */
153   - u32 brgc12; /* BRG12 configuration register */
154   - u32 brgc13; /* BRG13 configuration register */
155   - u32 brgc14; /* BRG14 configuration register */
156   - u32 brgc15; /* BRG15 configuration register */
157   - u32 brgc16; /* BRG16 configuration register */
158   - u8 res0[0x40];
159   -} __attribute__ ((packed)) qe_brg_t;
160   -
161   -/* SPI */
162   -typedef struct spi {
163   - u8 res0[0x20];
164   - u32 spmode; /* SPI mode register */
165   - u8 res1[0x2];
166   - u8 spie; /* SPI event register */
167   - u8 res2[0x1];
168   - u8 res3[0x2];
169   - u8 spim; /* SPI mask register */
170   - u8 res4[0x1];
171   - u8 res5[0x1];
172   - u8 spcom; /* SPI command register */
173   - u8 res6[0x2];
174   - u32 spitd; /* SPI transmit data register (cpu mode) */
175   - u32 spird; /* SPI receive data register (cpu mode) */
176   - u8 res7[0x8];
177   -} __attribute__ ((packed)) spi_t;
178   -
179   -/* SI */
180   -typedef struct si1 {
181   - u16 siamr1; /* SI1 TDMA mode register */
182   - u16 sibmr1; /* SI1 TDMB mode register */
183   - u16 sicmr1; /* SI1 TDMC mode register */
184   - u16 sidmr1; /* SI1 TDMD mode register */
185   - u8 siglmr1_h; /* SI1 global mode register high */
186   - u8 res0[0x1];
187   - u8 sicmdr1_h; /* SI1 command register high */
188   - u8 res2[0x1];
189   - u8 sistr1_h; /* SI1 status register high */
190   - u8 res3[0x1];
191   - u16 sirsr1_h; /* SI1 RAM shadow address register high */
192   - u8 sitarc1; /* SI1 RAM counter Tx TDMA */
193   - u8 sitbrc1; /* SI1 RAM counter Tx TDMB */
194   - u8 sitcrc1; /* SI1 RAM counter Tx TDMC */
195   - u8 sitdrc1; /* SI1 RAM counter Tx TDMD */
196   - u8 sirarc1; /* SI1 RAM counter Rx TDMA */
197   - u8 sirbrc1; /* SI1 RAM counter Rx TDMB */
198   - u8 sircrc1; /* SI1 RAM counter Rx TDMC */
199   - u8 sirdrc1; /* SI1 RAM counter Rx TDMD */
200   - u8 res4[0x8];
201   - u16 siemr1; /* SI1 TDME mode register 16 bits */
202   - u16 sifmr1; /* SI1 TDMF mode register 16 bits */
203   - u16 sigmr1; /* SI1 TDMG mode register 16 bits */
204   - u16 sihmr1; /* SI1 TDMH mode register 16 bits */
205   - u8 siglmg1_l; /* SI1 global mode register low 8 bits */
206   - u8 res5[0x1];
207   - u8 sicmdr1_l; /* SI1 command register low 8 bits */
208   - u8 res6[0x1];
209   - u8 sistr1_l; /* SI1 status register low 8 bits */
210   - u8 res7[0x1];
211   - u16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits */
212   - u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */
213   - u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */
214   - u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */
215   - u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */
216   - u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */
217   - u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */
218   - u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */
219   - u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */
220   - u8 res8[0x8];
221   - u32 siml1; /* SI1 multiframe limit register */
222   - u8 siedm1; /* SI1 extended diagnostic mode register */
223   - u8 res9[0xBB];
224   -} __attribute__ ((packed)) si1_t;
225   -
226   -/* SI Routing Tables */
227   -typedef struct sir {
228   - u8 tx[0x400];
229   - u8 rx[0x400];
230   - u8 res0[0x800];
231   -} __attribute__ ((packed)) sir_t;
232   -
233   -/* USB Controller. */
234   -typedef struct usb_ctlr {
235   - u8 usb_usmod;
236   - u8 usb_usadr;
237   - u8 usb_uscom;
238   - u8 res1[1];
239   - u16 usb_usep1;
240   - u16 usb_usep2;
241   - u16 usb_usep3;
242   - u16 usb_usep4;
243   - u8 res2[4];
244   - u16 usb_usber;
245   - u8 res3[2];
246   - u16 usb_usbmr;
247   - u8 res4[1];
248   - u8 usb_usbs;
249   - u16 usb_ussft;
250   - u8 res5[2];
251   - u16 usb_usfrn;
252   - u8 res6[0x22];
253   -} __attribute__ ((packed)) usb_t;
254   -
255   -/* MCC */
256   -typedef struct mcc {
257   - u32 mcce; /* MCC event register */
258   - u32 mccm; /* MCC mask register */
259   - u32 mccf; /* MCC configuration register */
260   - u32 merl; /* MCC emergency request level register */
261   - u8 res0[0xF0];
262   -} __attribute__ ((packed)) mcc_t;
263   -
264   -/* QE UCC Slow */
265   -typedef struct ucc_slow {
266   - u32 gumr_l; /* UCCx general mode register (low) */
267   - u32 gumr_h; /* UCCx general mode register (high) */
268   - u16 upsmr; /* UCCx protocol-specific mode register */
269   - u8 res0[0x2];
270   - u16 utodr; /* UCCx transmit on demand register */
271   - u16 udsr; /* UCCx data synchronization register */
272   - u16 ucce; /* UCCx event register */
273   - u8 res1[0x2];
274   - u16 uccm; /* UCCx mask register */
275   - u8 res2[0x1];
276   - u8 uccs; /* UCCx status register */
277   - u8 res3[0x24];
278   - u16 utpt;
279   - u8 guemr; /* UCC general extended mode register */
280   - u8 res4[0x200 - 0x091];
281   -} __attribute__ ((packed)) ucc_slow_t;
282   -
283   -typedef struct ucc_mii_mng {
284   - u32 miimcfg; /* MII management configuration reg */
285   - u32 miimcom; /* MII management command reg */
286   - u32 miimadd; /* MII management address reg */
287   - u32 miimcon; /* MII management control reg */
288   - u32 miimstat; /* MII management status reg */
289   - u32 miimind; /* MII management indication reg */
290   - u32 ifctl; /* interface control reg */
291   - u32 ifstat; /* interface statux reg */
292   -} __attribute__ ((packed))uec_mii_t;
293   -
294   -typedef struct ucc_ethernet {
295   - u32 maccfg1; /* mac configuration reg. 1 */
296   - u32 maccfg2; /* mac configuration reg. 2 */
297   - u32 ipgifg; /* interframe gap reg. */
298   - u32 hafdup; /* half-duplex reg. */
299   - u8 res1[0x10];
300   - u32 miimcfg; /* MII management configuration reg */
301   - u32 miimcom; /* MII management command reg */
302   - u32 miimadd; /* MII management address reg */
303   - u32 miimcon; /* MII management control reg */
304   - u32 miimstat; /* MII management status reg */
305   - u32 miimind; /* MII management indication reg */
306   - u32 ifctl; /* interface control reg */
307   - u32 ifstat; /* interface statux reg */
308   - u32 macstnaddr1; /* mac station address part 1 reg */
309   - u32 macstnaddr2; /* mac station address part 2 reg */
310   - u8 res2[0x8];
311   - u32 uempr; /* UCC Ethernet Mac parameter reg */
312   - u32 utbipar; /* UCC tbi address reg */
313   - u16 uescr; /* UCC Ethernet statistics control reg */
314   - u8 res3[0x180 - 0x15A];
315   - u32 tx64; /* Total number of frames (including bad
316   - * frames) transmitted that were exactly
317   - * of the minimal length (64 for un tagged,
318   - * 68 for tagged, or with length exactly
319   - * equal to the parameter MINLength */
320   - u32 tx127; /* Total number of frames (including bad
321   - * frames) transmitted that were between
322   - * MINLength (Including FCS length==4)
323   - * and 127 octets */
324   - u32 tx255; /* Total number of frames (including bad
325   - * frames) transmitted that were between
326   - * 128 (Including FCS length==4) and 255
327   - * octets */
328   - u32 rx64; /* Total number of frames received including
329   - * bad frames that were exactly of the
330   - * mninimal length (64 bytes) */
331   - u32 rx127; /* Total number of frames (including bad
332   - * frames) received that were between
333   - * MINLength (Including FCS length==4)
334   - * and 127 octets */
335   - u32 rx255; /* Total number of frames (including
336   - * bad frames) received that were between
337   - * 128 (Including FCS length==4) and 255
338   - * octets */
339   - u32 txok; /* Total number of octets residing in frames
340   - * that where involved in succesfull
341   - * transmission */
342   - u16 txcf; /* Total number of PAUSE control frames
343   - * transmitted by this MAC */
344   - u8 res4[0x2];
345   - u32 tmca; /* Total number of frames that were transmitted
346   - * succesfully with the group address bit set
347   - * that are not broadcast frames */
348   - u32 tbca; /* Total number of frames transmitted
349   - * succesfully that had destination address
350   - * field equal to the broadcast address */
351   - u32 rxfok; /* Total number of frames received OK */
352   - u32 rxbok; /* Total number of octets received OK */
353   - u32 rbyt; /* Total number of octets received including
354   - * octets in bad frames. Must be implemented
355   - * in HW because it includes octets in frames
356   - * that never even reach the UCC */
357   - u32 rmca; /* Total number of frames that were received
358   - * succesfully with the group address bit set
359   - * that are not broadcast frames */
360   - u32 rbca; /* Total number of frames received succesfully
361   - * that had destination address equal to the
362   - * broadcast address */
363   - u32 scar; /* Statistics carry register */
364   - u32 scam; /* Statistics caryy mask register */
365   - u8 res5[0x200 - 0x1c4];
366   -} __attribute__ ((packed)) uec_t;
367   -
368   -/* QE UCC Fast */
369   -typedef struct ucc_fast {
370   - u32 gumr; /* UCCx general mode register */
371   - u32 upsmr; /* UCCx protocol-specific mode register */
372   - u16 utodr; /* UCCx transmit on demand register */
373   - u8 res0[0x2];
374   - u16 udsr; /* UCCx data synchronization register */
375   - u8 res1[0x2];
376   - u32 ucce; /* UCCx event register */
377   - u32 uccm; /* UCCx mask register. */
378   - u8 uccs; /* UCCx status register */
379   - u8 res2[0x7];
380   - u32 urfb; /* UCC receive FIFO base */
381   - u16 urfs; /* UCC receive FIFO size */
382   - u8 res3[0x2];
383   - u16 urfet; /* UCC receive FIFO emergency threshold */
384   - u16 urfset; /* UCC receive FIFO special emergency
385   - * threshold */
386   - u32 utfb; /* UCC transmit FIFO base */
387   - u16 utfs; /* UCC transmit FIFO size */
388   - u8 res4[0x2];
389   - u16 utfet; /* UCC transmit FIFO emergency threshold */
390   - u8 res5[0x2];
391   - u16 utftt; /* UCC transmit FIFO transmit threshold */
392   - u8 res6[0x2];
393   - u16 utpt; /* UCC transmit polling timer */
394   - u8 res7[0x2];
395   - u32 urtry; /* UCC retry counter register */
396   - u8 res8[0x4C];
397   - u8 guemr; /* UCC general extended mode register */
398   - u8 res9[0x100 - 0x091];
399   - uec_t ucc_eth;
400   -} __attribute__ ((packed)) ucc_fast_t;
401   -
402   -/* QE UCC */
403   -typedef struct ucc_common {
404   - u8 res1[0x90];
405   - u8 guemr;
406   - u8 res2[0x200 - 0x091];
407   -} __attribute__ ((packed)) ucc_common_t;
408   -
409   -typedef struct ucc {
410   - union {
411   - ucc_slow_t slow;
412   - ucc_fast_t fast;
413   - ucc_common_t common;
414   - };
415   -} __attribute__ ((packed)) ucc_t;
416   -
417   -/* MultiPHY UTOPIA POS Controllers (UPC) */
418   -typedef struct upc {
419   - u32 upgcr; /* UTOPIA/POS general configuration register */
420   - u32 uplpa; /* UTOPIA/POS last PHY address */
421   - u32 uphec; /* ATM HEC register */
422   - u32 upuc; /* UTOPIA/POS UCC configuration */
423   - u32 updc1; /* UTOPIA/POS device 1 configuration */
424   - u32 updc2; /* UTOPIA/POS device 2 configuration */
425   - u32 updc3; /* UTOPIA/POS device 3 configuration */
426   - u32 updc4; /* UTOPIA/POS device 4 configuration */
427   - u32 upstpa; /* UTOPIA/POS STPA threshold */
428   - u8 res0[0xC];
429   - u32 updrs1_h; /* UTOPIA/POS device 1 rate select */
430   - u32 updrs1_l; /* UTOPIA/POS device 1 rate select */
431   - u32 updrs2_h; /* UTOPIA/POS device 2 rate select */
432   - u32 updrs2_l; /* UTOPIA/POS device 2 rate select */
433   - u32 updrs3_h; /* UTOPIA/POS device 3 rate select */
434   - u32 updrs3_l; /* UTOPIA/POS device 3 rate select */
435   - u32 updrs4_h; /* UTOPIA/POS device 4 rate select */
436   - u32 updrs4_l; /* UTOPIA/POS device 4 rate select */
437   - u32 updrp1; /* UTOPIA/POS device 1 receive priority low */
438   - u32 updrp2; /* UTOPIA/POS device 2 receive priority low */
439   - u32 updrp3; /* UTOPIA/POS device 3 receive priority low */
440   - u32 updrp4; /* UTOPIA/POS device 4 receive priority low */
441   - u32 upde1; /* UTOPIA/POS device 1 event */
442   - u32 upde2; /* UTOPIA/POS device 2 event */
443   - u32 upde3; /* UTOPIA/POS device 3 event */
444   - u32 upde4; /* UTOPIA/POS device 4 event */
445   - u16 uprp1;
446   - u16 uprp2;
447   - u16 uprp3;
448   - u16 uprp4;
449   - u8 res1[0x8];
450   - u16 uptirr1_0; /* Device 1 transmit internal rate 0 */
451   - u16 uptirr1_1; /* Device 1 transmit internal rate 1 */
452   - u16 uptirr1_2; /* Device 1 transmit internal rate 2 */
453   - u16 uptirr1_3; /* Device 1 transmit internal rate 3 */
454   - u16 uptirr2_0; /* Device 2 transmit internal rate 0 */
455   - u16 uptirr2_1; /* Device 2 transmit internal rate 1 */
456   - u16 uptirr2_2; /* Device 2 transmit internal rate 2 */
457   - u16 uptirr2_3; /* Device 2 transmit internal rate 3 */
458   - u16 uptirr3_0; /* Device 3 transmit internal rate 0 */
459   - u16 uptirr3_1; /* Device 3 transmit internal rate 1 */
460   - u16 uptirr3_2; /* Device 3 transmit internal rate 2 */
461   - u16 uptirr3_3; /* Device 3 transmit internal rate 3 */
462   - u16 uptirr4_0; /* Device 4 transmit internal rate 0 */
463   - u16 uptirr4_1; /* Device 4 transmit internal rate 1 */
464   - u16 uptirr4_2; /* Device 4 transmit internal rate 2 */
465   - u16 uptirr4_3; /* Device 4 transmit internal rate 3 */
466   - u32 uper1; /* Device 1 port enable register */
467   - u32 uper2; /* Device 2 port enable register */
468   - u32 uper3; /* Device 3 port enable register */
469   - u32 uper4; /* Device 4 port enable register */
470   - u8 res2[0x150];
471   -} __attribute__ ((packed)) upc_t;
472   -
473   -/* SDMA */
474   -typedef struct sdma {
475   - u32 sdsr; /* Serial DMA status register */
476   - u32 sdmr; /* Serial DMA mode register */
477   - u32 sdtr1; /* SDMA system bus threshold register */
478   - u32 sdtr2; /* SDMA secondary bus threshold register */
479   - u32 sdhy1; /* SDMA system bus hysteresis register */
480   - u32 sdhy2; /* SDMA secondary bus hysteresis register */
481   - u32 sdta1; /* SDMA system bus address register */
482   - u32 sdta2; /* SDMA secondary bus address register */
483   - u32 sdtm1; /* SDMA system bus MSNUM register */
484   - u32 sdtm2; /* SDMA secondary bus MSNUM register */
485   - u8 res0[0x10];
486   - u32 sdaqr; /* SDMA address bus qualify register */
487   - u32 sdaqmr; /* SDMA address bus qualify mask register */
488   - u8 res1[0x4];
489   - u32 sdwbcr; /* SDMA CAM entries base register */
490   - u8 res2[0x38];
491   -} __attribute__ ((packed)) sdma_t;
492   -
493   -/* Debug Space */
494   -typedef struct dbg {
495   - u32 bpdcr; /* Breakpoint debug command register */
496   - u32 bpdsr; /* Breakpoint debug status register */
497   - u32 bpdmr; /* Breakpoint debug mask register */
498   - u32 bprmrr0; /* Breakpoint request mode risc register 0 */
499   - u32 bprmrr1; /* Breakpoint request mode risc register 1 */
500   - u8 res0[0x8];
501   - u32 bprmtr0; /* Breakpoint request mode trb register 0 */
502   - u32 bprmtr1; /* Breakpoint request mode trb register 1 */
503   - u8 res1[0x8];
504   - u32 bprmir; /* Breakpoint request mode immediate register */
505   - u32 bprmsr; /* Breakpoint request mode serial register */
506   - u32 bpemr; /* Breakpoint exit mode register */
507   - u8 res2[0x48];
508   -} __attribute__ ((packed)) dbg_t;
509   -
510   -/*
511   - * RISC Special Registers (Trap and Breakpoint). These are described in
512   - * the QE Developer's Handbook.
513   -*/
514   -typedef struct rsp {
515   - u32 tibcr[16]; /* Trap/instruction breakpoint control regs */
516   - u8 res0[64];
517   - u32 ibcr0;
518   - u32 ibs0;
519   - u32 ibcnr0;
520   - u8 res1[4];
521   - u32 ibcr1;
522   - u32 ibs1;
523   - u32 ibcnr1;
524   - u32 npcr;
525   - u32 dbcr;
526   - u32 dbar;
527   - u32 dbamr;
528   - u32 dbsr;
529   - u32 dbcnr;
530   - u8 res2[12];
531   - u32 dbdr_h;
532   - u32 dbdr_l;
533   - u32 dbdmr_h;
534   - u32 dbdmr_l;
535   - u32 bsr;
536   - u32 bor;
537   - u32 bior;
538   - u8 res3[4];
539   - u32 iatr[4];
540   - u32 eccr; /* Exception control configuration register */
541   - u32 eicr;
542   - u8 res4[0x100-0xf8];
543   -} __attribute__ ((packed)) rsp_t;
544   -
545   -typedef struct qe_immap {
546   - qe_iram_t iram; /* I-RAM */
547   - qe_ic_t ic; /* Interrupt Controller */
548   - cp_qe_t cp; /* Communications Processor */
549   - qe_mux_t qmx; /* QE Multiplexer */
550   - qe_timers_t qet; /* QE Timers */
551   - spi_t spi[0x2]; /* spi */
552   - mcc_t mcc; /* mcc */
553   - qe_brg_t brg; /* brg */
554   - usb_t usb; /* USB */
555   - si1_t si1; /* SI */
556   - u8 res11[0x800];
557   - sir_t sir; /* SI Routing Tables */
558   - ucc_t ucc1; /* ucc1 */
559   - ucc_t ucc3; /* ucc3 */
560   - ucc_t ucc5; /* ucc5 */
561   - ucc_t ucc7; /* ucc7 */
562   - u8 res12[0x600];
563   - upc_t upc1; /* MultiPHY UTOPIA POS Controller 1 */
564   - ucc_t ucc2; /* ucc2 */
565   - ucc_t ucc4; /* ucc4 */
566   - ucc_t ucc6; /* ucc6 */
567   - ucc_t ucc8; /* ucc8 */
568   - u8 res13[0x600];
569   - upc_t upc2; /* MultiPHY UTOPIA POS Controller 2 */
570   - sdma_t sdma; /* SDMA */
571   - dbg_t dbg; /* Debug Space */
572   - rsp_t rsp[0x2]; /* RISC Special Registers
573   - * (Trap and Breakpoint) */
574   - u8 res14[0x300];
575   - u8 res15[0x3A00];
576   - u8 res16[0x8000]; /* 0x108000 - 0x110000 */
577   - u8 muram[QE_MURAM_SIZE];
578   -} __attribute__ ((packed)) qe_map_t;
579   -
580   -extern qe_map_t *qe_immr;
581   -
582   -#endif /* __IMMAP_QE_H__ */
arch/powerpc/include/asm/io.h
Diff comments   View file @ d5f8a6d
... ... @@ -123,6 +123,9 @@
123 123 #define iobarrier_r() eieio()
124 124 #define iobarrier_w() eieio()
125 125  
  126 +#define mb() sync()
  127 +#define isb() isync()
  128 +
126 129 /*
127 130 * Non ordered and non-swapping "raw" accessors
128 131 */
arch/powerpc/include/asm/processor.h
Diff comments   View file @ d5f8a6d
... ... @@ -1118,7 +1118,6 @@
1118 1118 #define SVR_B4860 0X868000
1119 1119 #define SVR_G4860 0x868001
1120 1120 #define SVR_B4460 0x868003
1121   -#define SVR_G4060 0x868003
1122 1121 #define SVR_B4440 0x868100
1123 1122 #define SVR_G4440 0x868101
1124 1123 #define SVR_B4420 0x868102
arch/powerpc/lib/board.c
Diff comments   View file @ d5f8a6d
... ... @@ -370,6 +370,11 @@
370 370 #ifdef CONFIG_DEEP_SLEEP
371 371 /* Jump to kernel in deep sleep case */
372 372 if (in_be32(&gur->scrtsr[0]) & (1 << 3)) {
  373 + l2cache_init();
  374 +#if defined(CONFIG_RAMBOOT_PBL)
  375 + disable_cpc_sram();
  376 +#endif
  377 + enable_cpc();
373 378 start_addr = in_be32(&scfg->sparecr[1]);
374 379 kernel_resume = (func_t)start_addr;
375 380 kernel_resume();
board/exmeritus/hww1u1a/hww1u1a.c
Diff comments   View file @ d5f8a6d
... ... @@ -203,7 +203,7 @@
203 203 int board_early_init_r(void)
204 204 {
205 205 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
206   - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  206 + int flash_esel = find_tlb_idx((void *)flashbase, 1);
207 207  
208 208 /*
209 209 * Remap bootflash region to caching-inhibited
... ... @@ -214,8 +214,14 @@
214 214 flush_dcache();
215 215 invalidate_icache();
216 216  
217   - /* invalidate existing TLB entry for FLASH */
218   - disable_tlb(flash_esel);
  217 + if (flash_esel == -1) {
  218 + /* very unlikely unless something is messed up */
  219 + puts("Error: Could not find TLB for FLASH BASE\n");
  220 + flash_esel = 2; /* give our best effort to continue */
  221 + } else {
  222 + /* invalidate existing TLB entry for FLASH */
  223 + disable_tlb(flash_esel);
  224 + }
219 225  
220 226 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
221 227 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
board/freescale/b4860qds/b4860qds.c
Diff comments   View file @ d5f8a6d
... ... @@ -913,7 +913,7 @@
913 913 int board_early_init_r(void)
914 914 {
915 915 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
916   - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  916 + int flash_esel = find_tlb_idx((void *)flashbase, 1);
917 917 int ret;
918 918  
919 919 /*
... ... @@ -925,8 +925,14 @@
925 925 flush_dcache();
926 926 invalidate_icache();
927 927  
928   - /* invalidate existing TLB entry for flash + promjet */
929   - disable_tlb(flash_esel);
  928 + if (flash_esel == -1) {
  929 + /* very unlikely unless something is messed up */
  930 + puts("Error: Could not find TLB for FLASH BASE\n");
  931 + flash_esel = 2; /* give our best effort to continue */
  932 + } else {
  933 + /* invalidate existing TLB entry for flash + promjet */
  934 + disable_tlb(flash_esel);
  935 + }
930 936  
931 937 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
932 938 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
board/freescale/bsc9132qds/bsc9132qds.c
Diff comments   View file @ d5f8a6d
... ... @@ -150,7 +150,7 @@
150 150 {
151 151 #ifndef CONFIG_SYS_NO_FLASH
152 152 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
153   - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  153 + int flash_esel = find_tlb_idx((void *)flashbase, 1);
154 154  
155 155 /*
156 156 * Remap Boot flash region to caching-inhibited
... ... @@ -161,8 +161,14 @@
161 161 flush_dcache();
162 162 invalidate_icache();
163 163  
164   - /* invalidate existing TLB entry for flash */
165   - disable_tlb(flash_esel);
  164 + if (flash_esel == -1) {
  165 + /* very unlikely unless something is messed up */
  166 + puts("Error: Could not find TLB for FLASH BASE\n");
  167 + flash_esel = 2; /* give our best effort to continue */
  168 + } else {
  169 + /* invalidate existing TLB entry for flash */
  170 + disable_tlb(flash_esel);
  171 + }
166 172  
167 173 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
168 174 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
board/freescale/c29xpcie/c29xpcie.c
Diff comments   View file @ d5f8a6d
... ... @@ -49,7 +49,7 @@
49 49 int board_early_init_r(void)
50 50 {
51 51 const unsigned long flashbase = CONFIG_SYS_FLASH_BASE;
52   - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  52 + int flash_esel = find_tlb_idx((void *)flashbase, 1);
53 53  
54 54 /*
55 55 * Remap Boot flash region to caching-inhibited
... ... @@ -60,8 +60,14 @@
60 60 flush_dcache();
61 61 invalidate_icache();
62 62  
63   - /* invalidate existing TLB entry for flash */
64   - disable_tlb(flash_esel);
  63 + if (flash_esel == -1) {
  64 + /* very unlikely unless something is messed up */
  65 + puts("Error: Could not find TLB for FLASH BASE\n");
  66 + flash_esel = 1; /* give our best effort to continue */
  67 + } else {
  68 + /* invalidate existing TLB entry for flash */
  69 + disable_tlb(flash_esel);
  70 + }
65 71  
66 72 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
67 73 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
board/freescale/corenet_ds/corenet_ds.c
Diff comments   View file @ d5f8a6d
... ... @@ -101,7 +101,7 @@
101 101 int board_early_init_r(void)
102 102 {
103 103 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
104   - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  104 + int flash_esel = find_tlb_idx((void *)flashbase, 1);
105 105  
106 106 /*
107 107 * Remap Boot flash + PROMJET region to caching-inhibited
... ... @@ -112,8 +112,14 @@
112 112 flush_dcache();
113 113 invalidate_icache();
114 114  
115   - /* invalidate existing TLB entry for flash + promjet */
116   - disable_tlb(flash_esel);
  115 + if (flash_esel == -1) {
  116 + /* very unlikely unless something is messed up */
  117 + puts("Error: Could not find TLB for FLASH BASE\n");
  118 + flash_esel = 2; /* give our best effort to continue */
  119 + } else {
  120 + /* invalidate existing TLB entry for flash + promjet */
  121 + disable_tlb(flash_esel);
  122 + }
117 123  
118 124 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
119 125 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
board/freescale/mpc8536ds/mpc8536ds.c
Diff comments   View file @ d5f8a6d
... ... @@ -196,7 +196,7 @@
196 196 int board_early_init_r(void)
197 197 {
198 198 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
199   - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  199 + int flash_esel = find_tlb_idx((void *)flashbase, 1);
200 200  
201 201 /*
202 202 * Remap Boot flash + PROMJET region to caching-inhibited
... ... @@ -207,8 +207,14 @@
207 207 flush_dcache();
208 208 invalidate_icache();
209 209  
210   - /* invalidate existing TLB entry for flash + promjet */
211   - disable_tlb(flash_esel);
  210 + if (flash_esel == -1) {
  211 + /* very unlikely unless something is messed up */
  212 + puts("Error: Could not find TLB for FLASH BASE\n");
  213 + flash_esel = 1; /* give our best effort to continue */
  214 + } else {
  215 + /* invalidate existing TLB entry for flash + promjet */
  216 + disable_tlb(flash_esel);
  217 + }
212 218  
213 219 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
214 220 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
board/freescale/mpc8572ds/mpc8572ds.c
Diff comments   View file @ d5f8a6d
... ... @@ -144,7 +144,7 @@
144 144 int board_early_init_r(void)
145 145 {
146 146 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
147   - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  147 + int flash_esel = find_tlb_idx((void *)flashbase, 1);
148 148  
149 149 /*
150 150 * Remap Boot flash + PROMJET region to caching-inhibited
... ... @@ -155,8 +155,14 @@
155 155 flush_dcache();
156 156 invalidate_icache();
157 157  
158   - /* invalidate existing TLB entry for flash + promjet */
159   - disable_tlb(flash_esel);
  158 + if (flash_esel == -1) {
  159 + /* very unlikely unless something is messed up */
  160 + puts("Error: Could not find TLB for FLASH BASE\n");
  161 + flash_esel = 2; /* give our best effort to continue */
  162 + } else {
  163 + /* invalidate existing TLB entry for flash + promjet */
  164 + disable_tlb(flash_esel);
  165 + }
160 166  
161 167 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
162 168 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
board/freescale/p1010rdb/p1010rdb.c
Diff comments   View file @ d5f8a6d
... ... @@ -93,7 +93,7 @@
93 93 int board_early_init_r(void)
94 94 {
95 95 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
96   - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  96 + int flash_esel = find_tlb_idx((void *)flashbase, 1);
97 97  
98 98 /*
99 99 * Remap Boot flash region to caching-inhibited
... ... @@ -104,8 +104,14 @@
104 104 flush_dcache();
105 105 invalidate_icache();
106 106  
107   - /* invalidate existing TLB entry for flash */
108   - disable_tlb(flash_esel);
  107 + if (flash_esel == -1) {
  108 + /* very unlikely unless something is messed up */
  109 + puts("Error: Could not find TLB for FLASH BASE\n");
  110 + flash_esel = 2; /* give our best effort to continue */
  111 + } else {
  112 + /* invalidate existing TLB entry for flash */
  113 + disable_tlb(flash_esel);
  114 + }
109 115  
110 116 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
111 117 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
board/freescale/p1022ds/p1022ds.c
Diff comments   View file @ d5f8a6d
... ... @@ -249,7 +249,7 @@
249 249 int board_early_init_r(void)
250 250 {
251 251 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
252   - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  252 + int flash_esel = find_tlb_idx((void *)flashbase, 1);
253 253  
254 254 /*
255 255 * Remap Boot flash + PROMJET region to caching-inhibited
... ... @@ -260,8 +260,14 @@
260 260 flush_dcache();
261 261 invalidate_icache();
262 262  
263   - /* invalidate existing TLB entry for flash + promjet */
264   - disable_tlb(flash_esel);
  263 + if (flash_esel == -1) {
  264 + /* very unlikely unless something is messed up */
  265 + puts("Error: Could not find TLB for FLASH BASE\n");
  266 + flash_esel = 2; /* give our best effort to continue */
  267 + } else {
  268 + /* invalidate existing TLB entry for flash + promjet */
  269 + disable_tlb(flash_esel);
  270 + }
265 271  
266 272 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
267 273 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
board/freescale/p1023rdb/p1023rdb.c
Diff comments   View file @ d5f8a6d
... ... @@ -57,7 +57,7 @@
57 57 int board_early_init_r(void)
58 58 {
59 59 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
60   - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  60 + int flash_esel = find_tlb_idx((void *)flashbase, 1);
61 61  
62 62 /*
63 63 * Remap Boot flash + PROMJET region to caching-inhibited
... ... @@ -68,8 +68,14 @@
68 68 flush_dcache();
69 69 invalidate_icache();
70 70  
71   - /* invalidate existing TLB entry for flash + promjet */
72   - disable_tlb(flash_esel);
  71 + if (flash_esel == -1) {
  72 + /* very unlikely unless something is messed up */
  73 + puts("Error: Could not find TLB for FLASH BASE\n");
  74 + flash_esel = 2; /* give our best effort to continue */
  75 + } else {
  76 + /* invalidate existing TLB entry for flash + promjet */
  77 + disable_tlb(flash_esel);
  78 + }
73 79  
74 80 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
75 81 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
board/freescale/p1023rds/Makefile
View file @ d5f8a6d
1   -#
2   -# Copyright 2010-2011 Freescale Semiconductor, Inc.
3   -#
4   -# SPDX-License-Identifier: GPL-2.0+
5   -#
6   -
7   -obj-y += p1023rds.o
8   -obj-y += law.o
9   -obj-y += tlb.o
board/freescale/p1023rds/README
View file @ d5f8a6d
1   -Overview
2   ---------
3   -The P1023 process includes a performance optimized implementation of the
4   -QorIQ data Path Acceleration Architecture (DPAA). This architecture
5   -provides the infrastructure to support simplified sharing of networking
6   -interfaces and accelerators by multiple CPU cores. P1023 is an e500 based
7   -dual core SOC.
8   -
9   -P1023RDS board is a Low End Dual core platform supporting the P1023
10   -processor of QorIQ series.
11   -
12   -Building U-boot
13   ----------------
14   -To build the u-boot for P1023RDS:
15   -Configure to NOR boot:
16   - make P1023RDS_config
17   -Configure to NAND boot:
18   - make P1023RDS_NAND_config
19   -Build:
20   - make
21   -
22   -Board Switches
23   ---------------
24   -Most switches on the board should not be changed. The most frequent
25   -user-settable switches on the board are used to configure
26   -the flash banks.
27   -
28   -J4: all open
29   -
30   -Default NOR flash boot switch setting:
31   - Sw3[1:8]: off on on off on on off off
32   - Sw4[1:8]: off off off on off off off off
33   - Sw6[1:8]: off on off on off on on off
34   - Sw7[1:8]: off on off off on off off off
35   - Sw8[1:8]: on off off off off off off off
36   -
37   -For NAND flash boot,set
38   -Sw4[1:4]: off on on on
39   -
40   -The default native ethernet setting is for RGMII mode.
41   -To use SGMII mode, set
42   -SW8[1:2]: OFF OFF
43   -SW7[6:7]: ON ON
44   -
45   -Memory Map
46   -----------
47   -0x0000_0000 0x7fff_ffff DDR 2G Cacheable
48   -0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
49   -0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
50   -0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
51   -
52   -0xe000_0000 0xe003_ffff BCSR 256K BCSR
53   -0xee00_0000 0xefff_ffff NOR flash 32M NOR flash
54   -0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M
55   -0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable
56   -0xffa0_0000 0xffaf_ffff NAND FLASH 1M non-cacheable
57   -0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
58   -
59   -Flashing u-boot Images
60   ----------------
61   -To program the image in the boot flash bank:
62   -NOR flash boot:
63   - => tftp 1000000 u-boot.bin
64   - => protect off all
65   - => erase eff40000 efffffff
66   - => cp.b 1000000 eff40000 c0000
67   -
68   -NAND flash boot:
69   - => tftp 1000000 u-boot-nand.bin
70   - => nand erase 0 80000
71   - => nand write 1000000 0 80000
72   -
73   -Firmware ucode location
74   ----------------------------------
75   -Microcode(ucode) to FMAN's IRAM is needed to make FMAN Ethernet work.
76   -u-boot loads ucode FLASH. The location for ucode:
77   -NOR Flash: 0xfe000000
78   -NAND Flash: 0x1f00000
79   -
80   -Using the Device Tree Source File
81   ----------------------------------
82   -To create the DTB (Device Tree Binary) image file,
83   -use a command similar to this:
84   -
85   - dtc -b 0 -f -I dts -O dtb p1023rds.dts > p1023rds.dtb
86   -
87   -Likely, that .dts file will come from here;
88   -
89   - linux-2.6/arch/powerpc/boot/dts/p1023rds.dts
90   -or
91   - make p1023rds.dtb ARCH=powerpc
92   -in linux-2.6 directory.
93   -
94   -Booting Linux
95   --------------
96   -Place a linux uImage in the TFTP disk area.
97   -
98   - tftp 1000000 uImage
99   - tftp 2000000 rootfs.ext2.gz.uboot
100   - tftp c00000 p1023rds.dtb
101   - bootm 1000000 2000000 c00000
board/freescale/p1023rds/bcsr.h
View file @ d5f8a6d
1   -/*
2   - * Copyright (C) 2011 Freescale Semiconductor, Inc.
3   - *
4   - * Authors: Chunhe Lan <b25806@freescale.com>
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -#ifndef __BCSR_H_
10   -#define __BCSR_H_
11   -
12   -#include <common.h>
13   -
14   -/*
15   - * BCSR Bit definitions
16   - * BCSR 15 *
17   - 0 device insertion oriention
18   - 1 stack processor present
19   - 2 power supply shut down/normal operation
20   - 3 I2C bus0 drive enable
21   - 4 reserved
22   - 5:7 I2C bus0 select
23   - 5 - I2C_BUS_0_SS0
24   - 6 - I2C_BUS_0_SS1
25   - 7 - I2C_BUS_0_SS2
26   -*/
27   -
28   -/* BCSR register base address is 0xFX000020 */
29   -#define BCSR_BASE_REG_OFFSET 0x20
30   -#define BCSR_ACCESS_REG_ADDR (CONFIG_SYS_BCSR_BASE + BCSR_BASE_REG_OFFSET)
31   -
32   -#define BCSR15_DEV_INS_ORI 0x80
33   -#define BCSR15_STACK_PRO_PRE 0x40
34   -#define BCSR15_POWER_SUPPLY 0x20
35   -#define BCSR15_I2C_BUS0_EN 0x10
36   -#define BCSR15_I2C_BUS0_SEG0 0x00
37   -#define BCSR15_I2C_BUS0_SEG1 0x04
38   -#define BCSR15_I2C_BUS0_SEG2 0x02
39   -#define BCSR15_I2C_BUS0_SEG3 0x06
40   -#define BCSR15_I2C_BUS0_SEG4 0x01
41   -#define BCSR15_I2C_BUS0_SEG5 0x05
42   -#define BCSR15_I2C_BUS0_SEG6 0x03
43   -#define BCSR15_I2C_BUS0_SEG7 0x07
44   -#define BCSR15_I2C_BUS0_SEG_CLR 0x07
45   -#define BCSR19_SGMII_SEL_L 0x01
46   -
47   -/*BCSR Utils functions*/
48   -void fixup_i2c_bus0_sel_seg0(void);
49   -#endif /* __BCSR_H_ */
board/freescale/p1023rds/law.c
View file @ d5f8a6d
1   -/*
2   - * Copyright 2010-2011 Freescale Semiconductor, Inc.
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -#include <common.h>
8   -#include <asm/fsl_law.h>
9   -#include <asm/mmu.h>
10   -
11   -struct law_entry law_table[] = {
12   - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
13   - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_4M,
14   - LAW_TRGT_IF_DPAA_SWP_SRAM),
15   - /* The LAW 0xe0000000 ~ 0xefffffff for BCSR and NOR flash */
16   - SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
17   -};
18   -
19   -int num_law_entries = ARRAY_SIZE(law_table);
board/freescale/p1023rds/p1023rds.c
View file @ d5f8a6d
1   -/*
2   - * Copyright 2010-2012 Freescale Semiconductor, Inc.
3   - *
4   - * Authors: Roy Zang <tie-fei.zang@freescale.com>
5   - * Chunhe Lan <b25806@freescale.com>
6   - *
7   - * SPDX-License-Identifier: GPL-2.0+
8   - */
9   -
10   -#include <common.h>
11   -#include <command.h>
12   -#include <pci.h>
13   -#include <asm/io.h>
14   -#include <asm/cache.h>
15   -#include <asm/processor.h>
16   -#include <asm/mmu.h>
17   -#include <asm/immap_85xx.h>
18   -#include <asm/fsl_pci.h>
19   -#include <fsl_ddr_sdram.h>
20   -#include <asm/fsl_portals.h>
21   -#include <libfdt.h>
22   -#include <fdt_support.h>
23   -#include <netdev.h>
24   -#include <malloc.h>
25   -#include <fm_eth.h>
26   -#include <fsl_mdio.h>
27   -#include <miiphy.h>
28   -#include <phy.h>
29   -#include <asm/fsl_dtsec.h>
30   -
31   -#include "bcsr.h"
32   -
33   -DECLARE_GLOBAL_DATA_PTR;
34   -
35   -int board_early_init_f(void)
36   -{
37   - fsl_lbc_t *lbc = LBC_BASE_ADDR;
38   -
39   - /* Set ABSWP to implement conversion of addresses in the LBC */
40   - setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
41   -
42   - return 0;
43   -}
44   -
45   -int checkboard(void)
46   -{
47   - u8 *bcsr = (u8 *)BCSR_ACCESS_REG_ADDR;
48   -
49   - printf("Board: P1023 RDS\n");
50   -
51   - clrbits_8(&bcsr[15], BCSR15_I2C_BUS0_SEG_CLR);
52   - setbits_8(&bcsr[15], BCSR15_I2C_BUS0_SEG0);
53   -
54   - return 0;
55   -}
56   -
57   -/* Fixed sdram init -- doesn't use serial presence detect. */
58   -phys_size_t fixed_sdram(void)
59   -{
60   -#ifndef CONFIG_SYS_RAMBOOT
61   - struct ccsr_ddr __iomem *ddr =
62   - (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
63   -
64   - set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);
65   -
66   - out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
67   - out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
68   - out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS);
69   - out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG);
70   - out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
71   - out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
72   - out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
73   - out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
74   - out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2);
75   - out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1);
76   - out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2);
77   - out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL);
78   - out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
79   - out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL);
80   - out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
81   - out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
82   - out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
83   - out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
84   - out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1);
85   - out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2);
86   - out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
87   -#endif
88   - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024ul;
89   -}
90   -
91   -#ifdef CONFIG_PCI
92   -void pci_init_board(void)
93   -{
94   - fsl_pcie_init_board(0);
95   -}
96   -#endif
97   -
98   -int board_early_init_r(void)
99   -{
100   - const unsigned int flashbase = CONFIG_SYS_BCSR_BASE;
101   - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
102   -
103   - /*
104   - * Remap Boot flash + BCSR region to caching-inhibited
105   - * so that flash can be erased properly.
106   - */
107   -
108   - /* Flush d-cache and invalidate i-cache of any FLASH data */
109   - flush_dcache();
110   - invalidate_icache();
111   -
112   - /* invalidate existing TLB entry for flash + bcsr */
113   - disable_tlb(flash_esel);
114   -
115   - set_tlb(1, flashbase, CONFIG_SYS_BCSR_BASE_PHYS,
116   - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
117   - 0, flash_esel, BOOKE_PAGESZ_256M, 1);
118   -
119   - setup_portals();
120   -
121   - return 0;
122   -}
123   -
124   -unsigned long get_board_sys_clk(ulong dummy)
125   -{
126   - return gd->bus_clk;
127   -}
128   -
129   -unsigned long get_board_ddr_clk(ulong dummy)
130   -{
131   - return gd->mem_clk;
132   -}
133   -
134   -int board_eth_init(bd_t *bis)
135   -{
136   - u8 *bcsr = (u8 *)BCSR_ACCESS_REG_ADDR;
137   - ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
138   - struct fsl_pq_mdio_info dtsec_mdio_info;
139   -
140   - /*
141   - * Need to set dTSEC 1 pin multiplexing to TSEC. The default setting
142   - * is not correct.
143   - */
144   - setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1);
145   -
146   - dtsec_mdio_info.regs =
147   - (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
148   - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
149   -
150   - /* Register the 1G MDIO bus */
151   - fsl_pq_mdio_init(bis, &dtsec_mdio_info);
152   -
153   - fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
154   - fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
155   -
156   - fm_info_set_mdio(FM1_DTSEC1,
157   - miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
158   - fm_info_set_mdio(FM1_DTSEC2,
159   - miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
160   -
161   - /* Make SERDES connected to SGMII by cleaing bcsr19[7] */
162   - if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_SGMII)
163   - clrbits_8(&bcsr[19], BCSR19_SGMII_SEL_L);
164   -
165   -#ifdef CONFIG_FMAN_ENET
166   - cpu_eth_init(bis);
167   -#endif
168   -
169   - return pci_eth_init(bis);
170   -}
171   -
172   -#if defined(CONFIG_OF_BOARD_SETUP)
173   -void ft_board_setup(void *blob, bd_t *bd)
174   -{
175   - phys_addr_t base;
176   - phys_size_t size;
177   -
178   - ft_cpu_setup(blob, bd);
179   -
180   - base = getenv_bootm_low();
181   - size = getenv_bootm_size();
182   -
183   - fdt_fixup_memory(blob, (u64)base, (u64)size);
184   -
185   -#ifdef CONFIG_HAS_FSL_DR_USB
186   - fdt_fixup_dr_usb(blob, bd);
187   -#endif
188   -
189   - fdt_fixup_fman_ethernet(blob);
190   -}
191   -#endif
board/freescale/p1023rds/tlb.c
View file @ d5f8a6d
1   -/*
2   - * Copyright 2010-2011 Freescale Semiconductor, Inc.
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -#include <common.h>
8   -#include <asm/mmu.h>
9   -
10   -struct fsl_e_tlb_entry tlb_table[] = {
11   - /* TLB 0 - for temp stack in cache */
12   - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
13   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
14   - 0, 0, BOOKE_PAGESZ_4K, 0),
15   - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
16   - CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
17   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
18   - 0, 0, BOOKE_PAGESZ_4K, 0),
19   - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
20   - CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
21   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
22   - 0, 0, BOOKE_PAGESZ_4K, 0),
23   - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
24   - CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
25   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
26   - 0, 0, BOOKE_PAGESZ_4K, 0),
27   -
28   - /* TLB 1 */
29   - /* *I*** - Covers boot page */
30   - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
31   - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
32   - 0, 0, BOOKE_PAGESZ_4K, 1),
33   -
34   - /* *I*G* - CCSRBAR */
35   - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
36   - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
37   - 0, 1, BOOKE_PAGESZ_4M, 1),
38   -
39   - /* *W*G* - BCSR and NOR flash on local bus*/
40   - /* This will be changed to *I*G* after relocation to RAM. */
41   - SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
42   - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
43   - 0, 2, BOOKE_PAGESZ_256M, 1),
44   -
45   - /* *I*G* - PCI */
46   - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
47   - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
48   - 0, 3, BOOKE_PAGESZ_1G, 1),
49   -
50   - /* *I*G* - PCI */
51   - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
52   - CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
53   - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
54   - 0, 4, BOOKE_PAGESZ_256M, 1),
55   -
56   - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
57   - CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
58   - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
59   - 0, 5, BOOKE_PAGESZ_256M, 1),
60   -
61   - /* *I*G* - PCI I/O */
62   - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
63   - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
64   - 0, 6, BOOKE_PAGESZ_256K, 1),
65   -
66   - /* Bman/Qman */
67   - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
68   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
69   - 0, 7, BOOKE_PAGESZ_1M, 1),
70   - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
71   - CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
72   - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
73   - 0, 8, BOOKE_PAGESZ_1M, 1),
74   - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
75   - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
76   - 0, 9, BOOKE_PAGESZ_1M, 1),
77   - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
78   - CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
79   - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
80   - 0, 10, BOOKE_PAGESZ_1M, 1),
81   -
82   - /* *I*G - NAND */
83   - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
84   - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
85   - 0, 11, BOOKE_PAGESZ_1M, 1),
86   -
87   -#ifdef CONFIG_SYS_RAMBOOT
88   - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
89   - CONFIG_SYS_DDR_SDRAM_BASE,
90   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
91   - 0, 12, BOOKE_PAGESZ_1G, 1),
92   -
93   - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
94   - CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
95   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
96   - 0, 13, BOOKE_PAGESZ_1G, 1),
97   -#endif
98   -};
99   -
100   -int num_tlb_entries = ARRAY_SIZE(tlb_table);
board/freescale/p1_p2_rdb/p1_p2_rdb.c
Diff comments   View file @ d5f8a6d
... ... @@ -128,7 +128,7 @@
128 128 int board_early_init_r(void)
129 129 {
130 130 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
131   - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  131 + int flash_esel = find_tlb_idx((void *)flashbase, 1);
132 132 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
133 133 unsigned int orig_bus = i2c_get_bus_num();
134 134 u8 i2c_data;
... ... @@ -163,8 +163,14 @@
163 163 flush_dcache();
164 164 invalidate_icache();
165 165  
166   - /* invalidate existing TLB entry for flash */
167   - disable_tlb(flash_esel);
  166 + if (flash_esel == -1) {
  167 + /* very unlikely unless something is messed up */
  168 + puts("Error: Could not find TLB for FLASH BASE\n");
  169 + flash_esel = 2; /* give our best effort to continue */
  170 + } else {
  171 + /* invalidate existing TLB entry for flash */
  172 + disable_tlb(flash_esel);
  173 + }
168 174  
169 175 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
170 176 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
Diff comments   View file @ d5f8a6d
... ... @@ -288,7 +288,7 @@
288 288 int board_early_init_r(void)
289 289 {
290 290 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
291   - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  291 + int flash_esel = find_tlb_idx((void *)flashbase, 1);
292 292  
293 293 /*
294 294 * Remap Boot flash region to caching-inhibited
... ... @@ -299,8 +299,14 @@
299 299 flush_dcache();
300 300 invalidate_icache();
301 301  
302   - /* invalidate existing TLB entry for flash */
303   - disable_tlb(flash_esel);
  302 + if (flash_esel == -1) {
  303 + /* very unlikely unless something is messed up */
  304 + puts("Error: Could not find TLB for FLASH BASE\n");
  305 + flash_esel = 2; /* give our best effort to continue */
  306 + } else {
  307 + /* invalidate existing TLB entry for flash */
  308 + disable_tlb(flash_esel);
  309 + }
304 310  
305 311 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
306 312 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */
board/freescale/p1_twr/p1_twr.c
Diff comments   View file @ d5f8a6d
... ... @@ -155,7 +155,7 @@
155 155 int board_early_init_r(void)
156 156 {
157 157 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
158   - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  158 + int flash_esel = find_tlb_idx((void *)flashbase, 1);
159 159  
160 160 /*
161 161 * Remap Boot flash region to caching-inhibited
... ... @@ -166,8 +166,14 @@
166 166 flush_dcache();
167 167 invalidate_icache();
168 168  
169   - /* invalidate existing TLB entry for flash */
170   - disable_tlb(flash_esel);
  169 + if (flash_esel == -1) {
  170 + /* very unlikely unless something is messed up */
  171 + puts("Error: Could not find TLB for FLASH BASE\n");
  172 + flash_esel = 2; /* give our best effort to continue */
  173 + } else {
  174 + /* invalidate existing TLB entry for flash */
  175 + disable_tlb(flash_esel);
  176 + }
171 177  
172 178 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
173 179 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
board/freescale/p2020ds/p2020ds.c
Diff comments   View file @ d5f8a6d
... ... @@ -159,7 +159,7 @@
159 159 int board_early_init_r(void)
160 160 {
161 161 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
162   - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  162 + int flash_esel = find_tlb_idx((void *)flashbase, 1);
163 163  
164 164 /*
165 165 * Remap Boot flash + PROMJET region to caching-inhibited
... ... @@ -170,8 +170,14 @@
170 170 flush_dcache();
171 171 invalidate_icache();
172 172  
173   - /* invalidate existing TLB entry for flash + promjet */
174   - disable_tlb(flash_esel);
  173 + if (flash_esel == -1) {
  174 + /* very unlikely unless something is messed up */
  175 + puts("Error: Could not find TLB for FLASH BASE\n");
  176 + flash_esel = 2; /* give our best effort to continue */
  177 + } else {
  178 + /* invalidate existing TLB entry for flash + promjet */
  179 + disable_tlb(flash_esel);
  180 + }
175 181  
176 182 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
177 183 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
board/freescale/p2041rdb/p2041rdb.c
Diff comments   View file @ d5f8a6d
... ... @@ -116,7 +116,7 @@
116 116 int board_early_init_r(void)
117 117 {
118 118 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
119   - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  119 + int flash_esel = find_tlb_idx((void *)flashbase, 1);
120 120  
121 121 /*
122 122 * Remap Boot flash + PROMJET region to caching-inhibited
... ... @@ -127,8 +127,14 @@
127 127 flush_dcache();
128 128 invalidate_icache();
129 129  
130   - /* invalidate existing TLB entry for flash + promjet */
131   - disable_tlb(flash_esel);
  130 + if (flash_esel == -1) {
  131 + /* very unlikely unless something is messed up */
  132 + puts("Error: Could not find TLB for FLASH BASE\n");
  133 + flash_esel = 2; /* give our best effort to continue */
  134 + } else {
  135 + /* invalidate existing TLB entry for flash + promjet */
  136 + disable_tlb(flash_esel);
  137 + }
132 138  
133 139 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
134 140 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
board/freescale/t1040qds/eth.c
Diff comments   View file @ d5f8a6d
... ... @@ -355,7 +355,9 @@
355 355 {
356 356 u8 brdcfg9;
357 357 brdcfg9 = QIXIS_READ(brdcfg[9]);
358   - brdcfg9 |= (1 << 5);
  358 +/* Initializing EPHY2 clock to RGMII mode */
  359 + brdcfg9 &= ~(BRDCFG9_EPHY2_MASK);
  360 + brdcfg9 |= (BRDCFG9_EPHY2_VAL);
359 361 QIXIS_WRITE(brdcfg[9], brdcfg9);
360 362 }
361 363  
board/freescale/t1040qds/t1040qds.c
Diff comments   View file @ d5f8a6d
... ... @@ -119,7 +119,7 @@
119 119 {
120 120 #ifdef CONFIG_SYS_FLASH_BASE
121 121 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
122   - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  122 + int flash_esel = find_tlb_idx((void *)flashbase, 1);
123 123  
124 124 /*
125 125 * Remap Boot flash + PROMJET region to caching-inhibited
... ... @@ -130,8 +130,14 @@
130 130 flush_dcache();
131 131 invalidate_icache();
132 132  
133   - /* invalidate existing TLB entry for flash + promjet */
134   - disable_tlb(flash_esel);
  133 + if (flash_esel == -1) {
  134 + /* very unlikely unless something is messed up */
  135 + puts("Error: Could not find TLB for FLASH BASE\n");
  136 + flash_esel = 2; /* give our best effort to continue */
  137 + } else {
  138 + /* invalidate existing TLB entry for flash + promjet */
  139 + disable_tlb(flash_esel);
  140 + }
135 141  
136 142 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
137 143 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
board/freescale/t1040qds/t1040qds_qixis.h
Diff comments   View file @ d5f8a6d
... ... @@ -17,6 +17,10 @@
17 17 #define BRDCFG5_IMX_MASK 0xC0
18 18 #define BRDCFG5_IMX_DIU 0x80
19 19  
  20 +/* BRDCFG9[2] controls EPHY2 Clock */
  21 +#define BRDCFG9_EPHY2_MASK 0x20
  22 +#define BRDCFG9_EPHY2_VAL 0x00
  23 +
20 24 /* BRDCFG15[3] controls LCD Panel Powerdown*/
21 25 #define BRDCFG15_LCDPD_MASK 0x10
22 26 #define BRDCFG15_LCDPD_ENABLED 0x00
board/freescale/t104xrdb/t104xrdb.c
Diff comments   View file @ d5f8a6d
... ... @@ -48,7 +48,7 @@
48 48 {
49 49 #ifdef CONFIG_SYS_FLASH_BASE
50 50 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
51   - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  51 + int flash_esel = find_tlb_idx((void *)flashbase, 1);
52 52  
53 53 /*
54 54 * Remap Boot flash region to caching-inhibited
... ... @@ -59,8 +59,14 @@
59 59 flush_dcache();
60 60 invalidate_icache();
61 61  
62   - /* invalidate existing TLB entry for flash */
63   - disable_tlb(flash_esel);
  62 + if (flash_esel == -1) {
  63 + /* very unlikely unless something is messed up */
  64 + puts("Error: Could not find TLB for FLASH BASE\n");
  65 + flash_esel = 2; /* give our best effort to continue */
  66 + } else {
  67 + /* invalidate existing TLB entry for flash */
  68 + disable_tlb(flash_esel);
  69 + }
64 70  
65 71 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
66 72 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
board/freescale/t208xqds/t208xqds.c
Diff comments   View file @ d5f8a6d
... ... @@ -326,7 +326,7 @@
326 326 int board_early_init_r(void)
327 327 {
328 328 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
329   - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  329 + int flash_esel = find_tlb_idx((void *)flashbase, 1);
330 330  
331 331 /*
332 332 * Remap Boot flash + PROMJET region to caching-inhibited
... ... @@ -337,8 +337,14 @@
337 337 flush_dcache();
338 338 invalidate_icache();
339 339  
340   - /* invalidate existing TLB entry for flash + promjet */
341   - disable_tlb(flash_esel);
  340 + if (flash_esel == -1) {
  341 + /* very unlikely unless something is messed up */
  342 + puts("Error: Could not find TLB for FLASH BASE\n");
  343 + flash_esel = 2; /* give our best effort to continue */
  344 + } else {
  345 + /* invalidate existing TLB entry for flash + promjet */
  346 + disable_tlb(flash_esel);
  347 + }
342 348  
343 349 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
344 350 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
board/freescale/t208xrdb/t208xrdb.c
Diff comments   View file @ d5f8a6d
... ... @@ -58,7 +58,7 @@
58 58 int board_early_init_r(void)
59 59 {
60 60 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
61   - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  61 + int flash_esel = find_tlb_idx((void *)flashbase, 1);
62 62 /*
63 63 * Remap Boot flash + PROMJET region to caching-inhibited
64 64 * so that flash can be erased properly.
... ... @@ -67,9 +67,14 @@
67 67 /* Flush d-cache and invalidate i-cache of any FLASH data */
68 68 flush_dcache();
69 69 invalidate_icache();
70   -
71   - /* invalidate existing TLB entry for flash + promjet */
72   - disable_tlb(flash_esel);
  70 + if (flash_esel == -1) {
  71 + /* very unlikely unless something is messed up */
  72 + puts("Error: Could not find TLB for FLASH BASE\n");
  73 + flash_esel = 2; /* give our best effort to continue */
  74 + } else {
  75 + /* invalidate existing TLB entry for flash + promjet */
  76 + disable_tlb(flash_esel);
  77 + }
73 78  
74 79 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
75 80 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
board/freescale/t4qds/t4240emu.c
Diff comments   View file @ d5f8a6d
... ... @@ -32,7 +32,7 @@
32 32 int board_early_init_r(void)
33 33 {
34 34 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
35   - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  35 + int flash_esel = find_tlb_idx((void *)flashbase, 1);
36 36  
37 37 /*
38 38 * Remap Boot flash + PROMJET region to caching-inhibited
... ... @@ -43,8 +43,14 @@
43 43 flush_dcache();
44 44 invalidate_icache();
45 45  
46   - /* invalidate existing TLB entry for flash */
47   - disable_tlb(flash_esel);
  46 + if (flash_esel == -1) {
  47 + /* very unlikely unless something is messed up */
  48 + puts("Error: Could not find TLB for FLASH BASE\n");
  49 + flash_esel = 2; /* give our best effort to continue */
  50 + } else {
  51 + /* invalidate existing TLB entry for flash */
  52 + disable_tlb(flash_esel);
  53 + }
48 54  
49 55 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
50 56 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
board/freescale/t4qds/t4240qds.c
Diff comments   View file @ d5f8a6d
... ... @@ -528,7 +528,7 @@
528 528 int board_early_init_r(void)
529 529 {
530 530 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
531   - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  531 + int flash_esel = find_tlb_idx((void *)flashbase, 1);
532 532  
533 533 /*
534 534 * Remap Boot flash + PROMJET region to caching-inhibited
... ... @@ -539,8 +539,14 @@
539 539 flush_dcache();
540 540 invalidate_icache();
541 541  
542   - /* invalidate existing TLB entry for flash + promjet */
543   - disable_tlb(flash_esel);
  542 + if (flash_esel == -1) {
  543 + /* very unlikely unless something is messed up */
  544 + puts("Error: Could not find TLB for FLASH BASE\n");
  545 + flash_esel = 2; /* give our best effort to continue */
  546 + } else {
  547 + /* invalidate existing TLB entry for flash + promjet */
  548 + disable_tlb(flash_esel);
  549 + }
544 550  
545 551 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
546 552 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
547 553  
... ... @@ -638,9 +644,10 @@
638 644 int misc_init_r(void)
639 645 {
640 646 u8 sw;
641   - serdes_corenet_t *srds_regs =
642   - (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  647 + void *srds_base = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  648 + serdes_corenet_t *srds_regs;
643 649 u32 actual[MAX_SERDES];
  650 + u32 pllcr0, expected;
644 651 unsigned int i;
645 652  
646 653 sw = QIXIS_READ(brdcfg[2]);
... ... @@ -663,8 +670,9 @@
663 670 }
664 671  
665 672 for (i = 0; i < MAX_SERDES; i++) {
666   - u32 pllcr0 = srds_regs->bank[i].pllcr0;
667   - u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
  673 + srds_regs = srds_base + i * 0x1000;
  674 + pllcr0 = srds_regs->bank[0].pllcr0;
  675 + expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
668 676 if (expected != actual[i]) {
669 677 printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n",
670 678 i + 1, serdes_clock_to_string(expected),
board/freescale/t4rdb/t4240rdb.c
Diff comments   View file @ d5f8a6d
... ... @@ -39,7 +39,7 @@
39 39 int board_early_init_r(void)
40 40 {
41 41 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
42   - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  42 + int flash_esel = find_tlb_idx((void *)flashbase, 1);
43 43  
44 44 /*
45 45 * Remap Boot flash + PROMJET region to caching-inhibited
... ... @@ -50,8 +50,14 @@
50 50 flush_dcache();
51 51 invalidate_icache();
52 52  
53   - /* invalidate existing TLB entry for flash + promjet */
54   - disable_tlb(flash_esel);
  53 + if (flash_esel == -1) {
  54 + /* very unlikely unless something is messed up */
  55 + puts("Error: Could not find TLB for FLASH BASE\n");
  56 + flash_esel = 2; /* give our best effort to continue */
  57 + } else {
  58 + /* invalidate existing TLB entry for flash + promjet */
  59 + disable_tlb(flash_esel);
  60 + }
55 61  
56 62 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
57 63 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
... ... @@ -830,7 +830,6 @@
830 830 Active powerpc mpc85xx - freescale p1022ds P1022DS_SDCARD P1022DS:SDCARD Timur Tabi <timur@freescale.com>
831 831 Active powerpc mpc85xx - freescale p1022ds P1022DS_SPIFLASH P1022DS:SPIFLASH Timur Tabi <timur@freescale.com>
832 832 Active powerpc mpc85xx - freescale p1023rdb P1023RDB - -
833   -Active powerpc mpc85xx - freescale p1023rds P1023RDS - Roy Zang <tie-fei.zang@freescale.com>
834 833 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB P1_P2_RDB:P1011RDB -
835 834 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT P1_P2_RDB:P1011RDB,36BIT -
836 835 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT_SDCARD P1_P2_RDB:P1011RDB,36BIT,SDCARD -
drivers/bootcount/bootcount.c
Diff comments   View file @ d5f8a6d
... ... @@ -36,7 +36,7 @@
36 36 #endif /* defined(CONFIG_MPC8260) */
37 37  
38 38 #if defined(CONFIG_QE)
39   -#include <asm/immap_qe.h>
  39 +#include <linux/immap_qe.h>
40 40  
41 41 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + 0x110000 + \
42 42 QE_MURAM_SIZE - 2 * sizeof(u32))
drivers/ddr/fsl/ctrl_regs.c
Diff comments   View file @ d5f8a6d
... ... @@ -1857,6 +1857,9 @@
1857 1857  
1858 1858 acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps);
1859 1859 wrtord_bg = max(4, picos_to_mclk(7500));
  1860 + if (popts->otf_burst_chop_en)
  1861 + wrtord_bg += 2;
  1862 +
1860 1863 pre_all_rec = 0;
1861 1864  
1862 1865 ddr->timing_cfg_8 = (0
drivers/ddr/fsl/fsl_ddr_gen4.c
Diff comments   View file @ d5f8a6d
... ... @@ -8,6 +8,7 @@
8 8 #include <asm/io.h>
9 9 #include <fsl_ddr_sdram.h>
10 10 #include <asm/processor.h>
  11 +#include <fsl_immap.h>
11 12 #include <fsl_ddr.h>
12 13  
13 14 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
14 15  
... ... @@ -183,12 +184,14 @@
183 184 * we choose the max, that is 500 us for all of case.
184 185 */
185 186 udelay(500);
186   - asm volatile("sync;isync");
  187 + mb();
  188 + isb();
187 189  
188 190 /* Let the controller go */
189 191 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
190 192 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
191   - asm volatile("sync;isync");
  193 + mb();
  194 + isb();
192 195  
193 196 total_gb_size_per_controller = 0;
194 197 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
drivers/mtd/nand/fsl_ifc_nand.c
Diff comments   View file @ d5f8a6d
... ... @@ -19,8 +19,11 @@
19 19 #include <asm/errno.h>
20 20 #include <fsl_ifc.h>
21 21  
22   -#define FSL_IFC_V1_1_0 0x01010000
23   -#define MAX_BANKS 4
  22 +#ifndef CONFIG_SYS_FSL_IFC_BANK_COUNT
  23 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
  24 +#endif
  25 +
  26 +#define MAX_BANKS CONFIG_SYS_FSL_IFC_BANK_COUNT
24 27 #define ERR_BYTE 0xFF /* Value returned for read bytes
25 28 when read failed */
26 29 #define IFC_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for IFC
27 30  
28 31  
... ... @@ -802,12 +805,30 @@
802 805 {
803 806 }
804 807  
805   -static void fsl_ifc_sram_init(void)
  808 +static int fsl_ifc_sram_init(uint32_t ver)
806 809 {
807 810 struct fsl_ifc *ifc = ifc_ctrl->regs;
808 811 uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0;
  812 + uint32_t ncfgr = 0;
809 813 long long end_tick;
810 814  
  815 + if (ver > FSL_IFC_V1_1_0) {
  816 + ncfgr = ifc_in32(&ifc->ifc_nand.ncfgr);
  817 + ifc_out32(&ifc->ifc_nand.ncfgr, ncfgr | IFC_NAND_SRAM_INIT_EN);
  818 +
  819 + /* wait for SRAM_INIT bit to be clear or timeout */
  820 + end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
  821 + while (end_tick > get_ticks()) {
  822 + ifc_ctrl->status =
  823 + ifc_in32(&ifc->ifc_nand.nand_evter_stat);
  824 +
  825 + if (!(ifc_ctrl->status & IFC_NAND_SRAM_INIT_EN))
  826 + return 0;
  827 + }
  828 + printf("fsl-ifc: Failed to Initialise SRAM\n");
  829 + return 1;
  830 + }
  831 +
811 832 cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT;
812 833  
813 834 /* Save CSOR and CSOR_ext */
814 835  
... ... @@ -850,11 +871,18 @@
850 871 break;
851 872 }
852 873  
  874 + if (ifc_ctrl->status != IFC_NAND_EVTER_STAT_OPC) {
  875 + printf("fsl-ifc: Failed to Initialise SRAM\n");
  876 + return 1;
  877 + }
  878 +
853 879 ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
854 880  
855 881 /* Restore CSOR and CSOR_ext */
856 882 ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor);
857 883 ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext);
  884 +
  885 + return 0;
858 886 }
859 887  
860 888 static int fsl_ifc_chip_init(int devnum, u8 *addr)
... ... @@ -864,7 +892,7 @@
864 892 struct fsl_ifc_mtd *priv;
865 893 struct nand_ecclayout *layout;
866 894 uint32_t cspr = 0, csor = 0, ver = 0;
867   - int ret;
  895 + int ret = 0;
868 896  
869 897 if (!ifc_ctrl) {
870 898 fsl_ifc_ctrl_init();
... ... @@ -1006,8 +1034,13 @@
1006 1034 }
1007 1035  
1008 1036 ver = ifc_in32(&ifc_ctrl->regs->ifc_rev);
1009   - if (ver == FSL_IFC_V1_1_0)
1010   - fsl_ifc_sram_init();
  1037 + if (ver >= FSL_IFC_V1_1_0)
  1038 + ret = fsl_ifc_sram_init(ver);
  1039 + if (ret)
  1040 + return ret;
  1041 +
  1042 + if (ver >= FSL_IFC_V2_0_0)
  1043 + priv->bufnum_mask = (priv->bufnum_mask * 2) + 1;
1011 1044  
1012 1045 ret = nand_scan_ident(mtd, 1, NULL);
1013 1046 if (ret)
drivers/mtd/nand/fsl_ifc_spl.c
Diff comments   View file @ d5f8a6d
... ... @@ -97,7 +97,7 @@
97 97 int pages_per_blk;
98 98 int blk_size;
99 99 int bad_marker = 0;
100   - int bufnum_mask, bufnum;
  100 + int bufnum_mask, bufnum, ver = 0;
101 101  
102 102 int csor, cspr;
103 103 int pos = 0;
... ... @@ -129,6 +129,10 @@
129 129 if (port_size == 8)
130 130 bad_marker = 5;
131 131 }
  132 +
  133 + ver = ifc_in32(&ifc->ifc_rev);
  134 + if (ver >= FSL_IFC_V2_0_0)
  135 + bufnum_mask = (bufnum_mask * 2) + 1;
132 136  
133 137 pages_per_blk =
134 138 32 << ((csor & CSOR_NAND_PB_MASK) >> CSOR_NAND_PB_SHIFT);
... ... @@ -143,7 +143,8 @@
143 143 #define MAX_RXBUF_LOG2 11
144 144 #define MAX_RXBUF_LEN (1 << MAX_RXBUF_LOG2)
145 145  
146   -#define PORT_IS_ENABLED(port) fm_info[fm_port_to_index(port)].enabled
  146 +#define PORT_IS_ENABLED(port) (fm_port_to_index(port) == -1 ? \
  147 + 0 : fm_info[fm_port_to_index(port)].enabled)
147 148  
148 149 #endif /* __FM_H__ */
drivers/net/fm/init.c
Diff comments   View file @ d5f8a6d
... ... @@ -147,6 +147,9 @@
147 147 {
148 148 int i = fm_port_to_index(port);
149 149  
  150 + if (i == -1)
  151 + return;
  152 +
150 153 fm_info[i].enabled = 0;
151 154 fman_disable_port(port);
152 155 }
... ... @@ -154,6 +157,9 @@
154 157 void fm_enable_port(enum fm_port port)
155 158 {
156 159 int i = fm_port_to_index(port);
  160 +
  161 + if (i == -1)
  162 + return;
157 163  
158 164 fm_info[i].enabled = 1;
159 165 fman_enable_port(port);
drivers/pci/fsl_pci_init.c
Diff comments   View file @ d5f8a6d
... ... @@ -504,8 +504,14 @@
504 504 }
505 505 #endif
506 506 if (!enabled) {
507   - /* Let the user know there's no PCIe link */
508   - printf("no link, regs @ 0x%lx\n", pci_info->regs);
  507 + /* Let the user know there's no PCIe link for root
  508 + * complex. for endpoint, the link may not setup, so
  509 + * print undetermined.
  510 + */
  511 + if (fsl_is_pci_agent(hose))
  512 + printf("undetermined, regs @ 0x%lx\n", pci_info->regs);
  513 + else
  514 + printf("no link, regs @ 0x%lx\n", pci_info->regs);
509 515 hose->last_busno = hose->first_busno;
510 516 return;
511 517 }
... ... @@ -11,7 +11,7 @@
11 11 #include <command.h>
12 12 #include "asm/errno.h"
13 13 #include "asm/io.h"
14   -#include "asm/immap_qe.h"
  14 +#include "linux/immap_qe.h"
15 15 #include "qe.h"
16 16  
17 17 #define MPC85xx_DEVDISR_QE_DISABLE 0x1
... ... @@ -11,7 +11,7 @@
11 11 #include "malloc.h"
12 12 #include "asm/errno.h"
13 13 #include "asm/io.h"
14   -#include "asm/immap_qe.h"
  14 +#include "linux/immap_qe.h"
15 15 #include "qe.h"
16 16 #include "uccf.h"
17 17  
... ... @@ -12,7 +12,7 @@
12 12  
13 13 #include "common.h"
14 14 #include "qe.h"
15   -#include "asm/immap_qe.h"
  15 +#include "linux/immap_qe.h"
16 16  
17 17 /* Fast or Giga ethernet
18 18 */
... ... @@ -11,7 +11,7 @@
11 11 #include "malloc.h"
12 12 #include "asm/errno.h"
13 13 #include "asm/io.h"
14   -#include "asm/immap_qe.h"
  14 +#include "linux/immap_qe.h"
15 15 #include "qe.h"
16 16 #include "uccf.h"
17 17 #include "uec.h"
drivers/qe/uec_phy.c
Diff comments   View file @ d5f8a6d
... ... @@ -14,7 +14,7 @@
14 14 #include "net.h"
15 15 #include "malloc.h"
16 16 #include "asm/errno.h"
17   -#include "asm/immap_qe.h"
  17 +#include "linux/immap_qe.h"
18 18 #include "asm/io.h"
19 19 #include "qe.h"
20 20 #include "uccf.h"
include/configs/B4860QDS.h
Diff comments   View file @ d5f8a6d
... ... @@ -340,7 +340,7 @@
340 340 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
341 341 FTIM1_GPCM_TRAD(0x1f))
342 342 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
343   - FTIM2_GPCM_TCH(0x0) | \
  343 + FTIM2_GPCM_TCH(0x8) | \
344 344 FTIM2_GPCM_TWP(0x1f))
345 345 #define CONFIG_SYS_CS3_FTIM3 0x0
346 346  
include/configs/BSC9132QDS.h
Diff comments   View file @ d5f8a6d
... ... @@ -354,7 +354,7 @@
354 354 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
355 355 FTIM1_GPCM_TRAD(0x1f))
356 356 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
357   - FTIM2_GPCM_TCH(0x0) | \
  357 + FTIM2_GPCM_TCH(0x8) | \
358 358 FTIM2_GPCM_TWP(0x1f))
359 359 #define CONFIG_SYS_CS2_FTIM3 0x0
360 360 #endif
include/configs/C29XPCIE.h
Diff comments   View file @ d5f8a6d
... ... @@ -319,7 +319,7 @@
319 319 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
320 320 FTIM1_GPCM_TRAD(0x1f))
321 321 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
322   - FTIM2_GPCM_TCH(0x0) | \
  322 + FTIM2_GPCM_TCH(0x8) | \
323 323 FTIM2_GPCM_TWP(0x1f))
324 324 #define CONFIG_SYS_CS2_FTIM3 0x0
325 325  
include/configs/P1010RDB.h
Diff comments   View file @ d5f8a6d
... ... @@ -537,7 +537,7 @@
537 537 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
538 538 FTIM1_GPCM_TRAD(0x1f))
539 539 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
540   - FTIM2_GPCM_TCH(0x0) | \
  540 + FTIM2_GPCM_TCH(0x8) | \
541 541 FTIM2_GPCM_TWP(0x1f))
542 542 #define CONFIG_SYS_CS3_FTIM3 0x0
543 543  
include/configs/P1023RDS.h
View file @ d5f8a6d
1   -/*
2   - * Copyright 2010-2012 Freescale Semiconductor, Inc.
3   - *
4   - * Authors: Roy Zang <tie-fei.zang@freescale.com>
5   - * Chunhe Lan <b25806@freescale.com>
6   - *
7   - * SPDX-License-Identifier: GPL-2.0+
8   - */
9   -
10   -/*
11   - * p1023rds board configuration file
12   - *
13   - */
14   -#ifndef __CONFIG_H
15   -#define __CONFIG_H
16   -
17   -#ifndef CONFIG_SYS_TEXT_BASE
18   -#define CONFIG_SYS_TEXT_BASE 0xeff40000
19   -#endif
20   -
21   -#ifndef CONFIG_SYS_MONITOR_BASE
22   -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
23   -#endif
24   -
25   -#ifndef CONFIG_RESET_VECTOR_ADDRESS
26   -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
27   -#endif
28   -
29   -/* High Level Configuration Options */
30   -#define CONFIG_BOOKE /* BOOKE */
31   -#define CONFIG_E500 /* BOOKE e500 family */
32   -#define CONFIG_P1023
33   -#define CONFIG_P1023RDS
34   -#define CONFIG_MP /* support multiple processors */
35   -
36   -#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
37   -#define CONFIG_PCI /* Enable PCI/PCIE */
38   -#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
39   -#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
40   -#define CONFIG_PCIE3 /* PCIE controler 3 (slot 3) */
41   -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
42   -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
43   -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
44   -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
45   -#define CONFIG_FSL_LAW /* Use common FSL init code */
46   -
47   -#ifndef __ASSEMBLY__
48   -extern unsigned long get_clock_freq(void);
49   -#endif
50   -
51   -#define CONFIG_SYS_CLK_FREQ 66666666
52   -#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
53   -
54   -/*
55   - * These can be toggled for performance analysis, otherwise use default.
56   - */
57   -#define CONFIG_L2_CACHE /* toggle L2 cache */
58   -#define CONFIG_BTB /* toggle branch predition */
59   -#define CONFIG_HWCONFIG
60   -
61   -#define CONFIG_ENABLE_36BIT_PHYS
62   -
63   -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
64   -#define CONFIG_SYS_MEMTEST_END 0x1fffffff /* fix me, only 1G */
65   -#define CONFIG_PANIC_HANG /* do not reset board on panic */
66   -
67   -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* Implement conversion of
68   - addresses in the LBC */
69   -
70   -/* DDR Setup */
71   -#define CONFIG_VERY_BIG_RAM
72   -
73   -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
74   -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
75   -
76   -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
77   -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
78   -
79   -#define CONFIG_DIMM_SLOTS_PER_CTLR 1
80   -#define CONFIG_CHIP_SELECTS_PER_CTRL 2
81   -
82   -/* These are used when DDR doesn't use SPD. */
83   -#define CONFIG_SYS_SDRAM_SIZE 2048u /* DDR is 2GB */
84   -
85   -/* Default settings for "stable" mode */
86   -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
87   -#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
88   -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
89   -#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
90   -#define CONFIG_SYS_DDR_TIMING_3 0x00020000
91   -#define CONFIG_SYS_DDR_TIMING_0 0x40110104
92   -#define CONFIG_SYS_DDR_TIMING_1 0x5C59E544
93   -#define CONFIG_SYS_DDR_TIMING_2 0x0fA888CA
94   -#define CONFIG_SYS_DDR_MODE_1 0x00441210
95   -#define CONFIG_SYS_DDR_MODE_2 0x00000000
96   -#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000
97   -#define CONFIG_SYS_DDR_INTERVAL 0x0A280100
98   -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
99   -#define CONFIG_SYS_DDR_CLK_CTRL 0x01800000
100   -#define CONFIG_SYS_DDR_TIMING_4 0x00000001
101   -#define CONFIG_SYS_DDR_TIMING_5 0x01401400
102   -#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
103   -#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F605
104   -#define CONFIG_SYS_DDR_CONTROL 0xC70C0008 /* Type = DDR3: No Interleaving */
105   -#define CONFIG_SYS_DDR_CONTROL2 0x24401010
106   -#define CONFIG_SYS_DDR_CDR1 0x00000000
107   -#define CONFIG_SYS_DDR_CDR2 0x00000000
108   -
109   -#define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000
110   -#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
111   -#define CONFIG_SYS_DDR_SBE 0x00000000
112   -
113   -/* Settings that differ for "performance" mode */
114   -#define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */
115   -#define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */
116   -#define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014302
117   -#define CONFIG_SYS_DDR_TIMING_1_PERF 0x5C58E544
118   -#define CONFIG_SYS_DDR_TIMING_2_PERF 0x0FA888CA
119   -/* Type = DDR3: cs0-cs1 interleaving */
120   -#define CONFIG_SYS_DDR_CONTROL_PERF 0xC70C4008
121   -#define CONFIG_SYS_DDR_CDR_1 0x00000000
122   -#define CONFIG_SYS_DDR_CDR_2 0x00000000
123   -
124   -
125   -/*
126   - * Memory map
127   - *
128   - * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
129   - * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
130   - * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
131   - * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
132   - *
133   - * Localbus non-cacheable
134   - * 0xe000_0000 0xe003_ffff BCSR 256K BCSR
135   - * 0xee00_0000 0xefff_ffff NOR flash 32M NOR flash
136   - * 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M
137   - * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable
138   - * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
139   - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
140   - */
141   -
142   -/*
143   - * Local Bus Definitions
144   - */
145   -#define CONFIG_SYS_BCSR_BASE 0xe0000000 /* start of on board FPGA */
146   -#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
147   -
148   -#define CONFIG_SYS_FLASH_BASE 0xee000000 /* start of FLASH 32M */
149   -
150   -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
151   -
152   -#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
153   - | BR_PS_16 | BR_V)
154   -#define CONFIG_FLASH_OR_PRELIM 0xfe000ff7
155   -
156   -#define CONFIG_FLASH_CFI_DRIVER
157   -#define CONFIG_SYS_FLASH_CFI
158   -#define CONFIG_SYS_FLASH_EMPTY_INFO
159   -
160   -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
161   -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
162   -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
163   -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
164   -
165   -#if defined(CONFIG_SYS_SPL)
166   -#define CONFIG_SYS_RAMBOOT
167   -#endif
168   -
169   -#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f function */
170   -#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
171   -
172   -#define CONFIG_SYS_INIT_RAM_LOCK
173   -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
174   -#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
175   -
176   -#define CONFIG_SYS_GBL_DATA_OFFSET \
177   - (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
178   -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
179   -
180   -#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
181   -#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
182   -
183   -#ifndef CONFIG_NAND_SPL
184   -#define CONFIG_SYS_NAND_BASE 0xffa00000
185   -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
186   -#else
187   -#define CONFIG_SYS_NAND_BASE 0xfff00000
188   -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
189   -#endif
190   -
191   -#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
192   -#define CONFIG_SYS_MAX_NAND_DEVICE 1
193   -#define CONFIG_MTD_NAND_VERIFY_WRITE
194   -#define CONFIG_CMD_NAND
195   -#define CONFIG_NAND_FSL_ELBC
196   -#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
197   -
198   -/* NAND boot: 4K NAND loader config */
199   -#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
200   -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + CONFIG_SYS_NAND_SPL_SIZE)
201   -#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE)
202   -#define CONFIG_SYS_NAND_U_BOOT_START 0x11000000
203   -#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
204   -#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
205   -#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
206   -
207   -/* NAND flash config */
208   -#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
209   - | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
210   - | BR_PS_8 /* Port Size = 8bit */ \
211   - | BR_MS_FCM /* MSEL = FCM */ \
212   - | BR_V) /* valid */
213   -#define CONFIG_SYS_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \
214   - | OR_FCM_CSCT \
215   - | OR_FCM_CST \
216   - | OR_FCM_CHT \
217   - | OR_FCM_SCY_1 \
218   - | OR_FCM_TRLX \
219   - | OR_FCM_EHTR)
220   -
221   -#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
222   -#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
223   -/* chip select 1 - BCSR */
224   -#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_BCSR_BASE_PHYS) \
225   - | BR_MS_GPCM | BR_PS_8 | BR_V)
226   -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \
227   - | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
228   - | OR_GPCM_EAD)
229   -
230   -/* Serial Port
231   - * open - index 2
232   - * shorted - index 1
233   - */
234   -#define CONFIG_CONS_INDEX 1
235   -#undef CONFIG_SERIAL_SOFTWARE_FIFO
236   -#define CONFIG_SYS_NS16550
237   -#define CONFIG_SYS_NS16550_SERIAL
238   -#define CONFIG_SYS_NS16550_REG_SIZE 1
239   -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
240   -#ifdef CONFIG_NAND_SPL
241   -#define CONFIG_NS16550_MIN_FUNCTIONS
242   -#endif
243   -
244   -#define CONFIG_SYS_BAUDRATE_TABLE \
245   - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
246   -
247   -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
248   -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
249   -
250   -/* Use the HUSH parser */
251   -#define CONFIG_SYS_HUSH_PARSER
252   -
253   -/*
254   - * Pass open firmware flat tree
255   - */
256   -#define CONFIG_OF_LIBFDT
257   -#define CONFIG_OF_BOARD_SETUP
258   -#define CONFIG_OF_STDOUT_VIA_ALIAS
259   -
260   -/* new uImage format support */
261   -#define CONFIG_FIT
262   -#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
263   -
264   -/* I2C */
265   -#define CONFIG_SYS_I2C
266   -#define CONFIG_SYS_I2C_FSL
267   -#define CONFIG_SYS_FSL_I2C_SPEED 400000
268   -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
269   -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
270   -#define CONFIG_SYS_FSL_I2C2_SPEED 400000
271   -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
272   -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
273   -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
274   -
275   -/*
276   - * I2C2 EEPROM
277   - */
278   -#define CONFIG_ID_EEPROM
279   -#ifdef CONFIG_ID_EEPROM
280   -#define CONFIG_SYS_I2C_EEPROM_NXID
281   -#endif
282   -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
283   -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
284   -#define CONFIG_SYS_EEPROM_BUS_NUM 0
285   -
286   -#define CONFIG_CMD_I2C
287   -
288   -/*
289   - * eSPI - Enhanced SPI
290   - */
291   -#define CONFIG_SPI_FLASH
292   -#define CONFIG_SPI_FLASH_ATMEL
293   -
294   -#define CONFIG_HARD_SPI
295   -#define CONFIG_FSL_ESPI
296   -
297   -#define CONFIG_CMD_SF
298   -#define CONFIG_SF_DEFAULT_SPEED 10000000
299   -#define CONFIG_SF_DEFAULT_MODE 0
300   -
301   -/*
302   - * General PCI
303   - * Memory space is mapped 1-1, but I/O space must start from 0.
304   - */
305   -
306   -/* controller 3, Slot 1, tgtid 3, Base address b000 */
307   -#define CONFIG_SYS_PCIE3_NAME "Slot 3"
308   -#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
309   -#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
310   -#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
311   -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
312   -#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
313   -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
314   -#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
315   -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
316   -
317   -/* controller 2, direct to uli, tgtid 2, Base address 9000 */
318   -#define CONFIG_SYS_PCIE2_NAME "Slot 2"
319   -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
320   -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
321   -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
322   -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
323   -#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
324   -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
325   -#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
326   -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
327   -
328   -/* controller 1, Slot 2, tgtid 1, Base address a000 */
329   -#define CONFIG_SYS_PCIE1_NAME "Slot 1"
330   -#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
331   -#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
332   -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
333   -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
334   -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
335   -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
336   -#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
337   -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
338   -
339   -#if defined(CONFIG_PCI)
340   -#define CONFIG_E1000 /* Defind e1000 pci Ethernet card */
341   -#define CONFIG_PCI_PNP /* do pci plug-and-play */
342   -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
343   -#endif /* CONFIG_PCI */
344   -
345   -/*
346   - * Environment
347   - */
348   -#define CONFIG_ENV_OVERWRITE
349   -
350   -#if defined(CONFIG_SYS_RAMBOOT)
351   -#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
352   -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x4000)
353   -#define CONFIG_ENV_SIZE 0x2000
354   -#else
355   -#define CONFIG_ENV_IS_IN_FLASH
356   -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
357   -#define CONFIG_ENV_SIZE 0x2000
358   -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
359   -#endif
360   -
361   -#define CONFIG_LOADS_ECHO /* echo on for serial download */
362   -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
363   -
364   -/*
365   - * Command line configuration.
366   - */
367   -#include <config_cmd_default.h>
368   -
369   -#define CONFIG_CMD_IRQ
370   -#define CONFIG_CMD_PING
371   -#define CONFIG_CMD_MII
372   -#define CONFIG_CMD_ELF
373   -#define CONFIG_CMD_SETEXPR
374   -#define CONFIG_CMD_REGINFO
375   -
376   -#if defined(CONFIG_PCI)
377   -#define CONFIG_CMD_PCI
378   -#define CONFIG_CMD_NET
379   -#endif
380   -
381   -/*
382   - * USB
383   - */
384   -#define CONFIG_HAS_FSL_DR_USB
385   -#ifdef CONFIG_HAS_FSL_DR_USB
386   -#define CONFIG_USB_EHCI
387   -
388   -#ifdef CONFIG_USB_EHCI
389   -#define CONFIG_CMD_USB
390   -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
391   -#define CONFIG_USB_EHCI_FSL
392   -#define CONFIG_USB_STORAGE
393   -#define CONFIG_CMD_FAT
394   -#define CONFIG_CMD_EXT2
395   -#define CONFIG_CMD_FAT
396   -#define CONFIG_DOS_PARTITION
397   -#endif
398   -#endif
399   -
400   -/*
401   - * Miscellaneous configurable options
402   - */
403   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
404   -#define CONFIG_CMDLINE_EDITING /* Command-line editing */
405   -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
406   -#if defined(CONFIG_CMD_KGDB)
407   -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
408   -#else
409   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
410   -#endif
411   -/* Print Buffer Size */
412   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
413   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
414   -/* Boot Argument Buffer Size */
415   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
416   -
417   -/*
418   - * For booting Linux, the board info and command line data
419   - * have to be in the first 16 MB of memory, since this is
420   - * the maximum mapped by the Linux kernel during initialization.
421   - */
422   -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
423   -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
424   -
425   -#if defined(CONFIG_CMD_KGDB)
426   -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
427   -#endif
428   -
429   -/*
430   - * Environment Configuration
431   - */
432   -#define CONFIG_BOOTFILE "uImage"
433   -#define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */
434   -
435   -/* default location for tftp and bootm */
436   -#define CONFIG_LOADADDR 1000000
437   -
438   -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
439   -
440   -#define CONFIG_BAUDRATE 115200
441   -
442   -/* Qman/Bman */
443   -#define CONFIG_SYS_DPAA_QBMAN /* support Q/Bman */
444   -#define CONFIG_SYS_QMAN_MEM_BASE 0xff000000
445   -#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
446   -#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
447   -#define CONFIG_SYS_BMAN_MEM_BASE 0xff200000
448   -#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
449   -#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
450   -
451   -/* For FM */
452   -#define CONFIG_SYS_DPAA_FMAN
453   -#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
454   -
455   -#ifdef CONFIG_SYS_DPAA_FMAN
456   -#define CONFIG_FMAN_ENET
457   -#define CONFIG_PHY_MARVELL
458   -#endif
459   -
460   -/* Default address of microcode for the Linux Fman driver */
461   -/* QE microcode/firmware address */
462   -#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
463   -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
464   -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
465   -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
466   -
467   -#ifdef CONFIG_FMAN_ENET
468   -#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
469   -#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x7
470   -
471   -#define CONFIG_SYS_TBIPA_VALUE 8
472   -#define CONFIG_MII /* MII PHY management */
473   -#define CONFIG_ETHPRIME "FM1@DTSEC1"
474   -#endif
475   -
476   -#define CONFIG_EXTRA_ENV_SETTINGS \
477   - "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
478   -
479   -#endif /* __CONFIG_H */
include/configs/T1040QDS.h
Diff comments   View file @ d5f8a6d
... ... @@ -445,11 +445,17 @@
445 445 #define CONFIG_SYS_I2C
446 446 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
447 447 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
  448 +#define CONFIG_SYS_FSL_I2C2_SPEED 50000
  449 +#define CONFIG_SYS_FSL_I2C3_SPEED 50000
  450 +#define CONFIG_SYS_FSL_I2C4_SPEED 50000
448 451 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
449   -#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
450 452 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  453 +#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
  454 +#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
451 455 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
452   -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
  456 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  457 +#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
  458 +#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
453 459  
454 460 #define I2C_MUX_PCA_ADDR 0x77
455 461 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
include/configs/T104xRDB.h
Diff comments   View file @ d5f8a6d
... ... @@ -286,7 +286,7 @@
286 286 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
287 287 FTIM1_GPCM_TRAD(0x1f))
288 288 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
289   - FTIM2_GPCM_TCH(0x0) | \
  289 + FTIM2_GPCM_TCH(0x8) | \
290 290 FTIM2_GPCM_TWP(0x1f))
291 291 #define CONFIG_SYS_CS2_FTIM3 0x0
292 292  
293 293  
294 294  
295 295  
... ... @@ -443,11 +443,17 @@
443 443 #define CONFIG_SYS_I2C
444 444 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
445 445 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
  446 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000
  447 +#define CONFIG_SYS_FSL_I2C3_SPEED 400000
  448 +#define CONFIG_SYS_FSL_I2C4_SPEED 400000
446 449 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
447   -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
448 450 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  451 +#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
  452 +#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
449 453 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
450   -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
  454 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  455 +#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
  456 +#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
451 457  
452 458 /* I2C bus multiplexer */
453 459 #define I2C_MUX_PCA_ADDR 0x70
include/configs/T208xQDS.h
Diff comments   View file @ d5f8a6d
... ... @@ -11,6 +11,8 @@
11 11 #ifndef __T208xQDS_H
12 12 #define __T208xQDS_H
13 13  
  14 +#define CONFIG_SYS_GENERIC_BOARD
  15 +#define CONFIG_DISPLAY_BOARDINFO
14 16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
15 17 #define CONFIG_MMC
16 18 #define CONFIG_SPI_FLASH
... ... @@ -537,7 +539,7 @@
537 539 #ifdef CONFIG_SPI_FLASH
538 540 #define CONFIG_FSL_ESPI
539 541 #define CONFIG_SPI_FLASH_STMICRO
540   -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_RAMBOOT_PBL)
  542 +#ifndef CONFIG_SPL_BUILD
541 543 #define CONFIG_SPI_FLASH_SST
542 544 #define CONFIG_SPI_FLASH_EON
543 545 #endif
include/configs/T208xRDB.h
Diff comments   View file @ d5f8a6d
... ... @@ -11,6 +11,8 @@
11 11 #ifndef __T2080RDB_H
12 12 #define __T2080RDB_H
13 13  
  14 +#define CONFIG_SYS_GENERIC_BOARD
  15 +#define CONFIG_DISPLAY_BOARDINFO
14 16 #define CONFIG_T2080RDB
15 17 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
16 18 #define CONFIG_MMC
... ... @@ -283,7 +285,7 @@
283 285 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
284 286 FTIM1_GPCM_TRAD(0x1f))
285 287 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
286   - FTIM2_GPCM_TCH(0x0) | \
  288 + FTIM2_GPCM_TCH(0x8) | \
287 289 FTIM2_GPCM_TWP(0x1f))
288 290 #define CONFIG_SYS_CS2_FTIM3 0x0
289 291  
include/configs/T4240QDS.h
Diff comments   View file @ d5f8a6d
... ... @@ -237,7 +237,7 @@
237 237 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
238 238 FTIM1_GPCM_TRAD(0x3f))
239 239 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
240   - FTIM2_GPCM_TCH(0x0) | \
  240 + FTIM2_GPCM_TCH(0x8) | \
241 241 FTIM2_GPCM_TWP(0x1f))
242 242 #define CONFIG_SYS_CS3_FTIM3 0x0
243 243  
... ... @@ -12,6 +12,8 @@
12 12 #include <config.h>
13 13 #include <common.h>
14 14  
  15 +#define FSL_IFC_V1_1_0 0x01010000
  16 +#define FSL_IFC_V2_0_0 0x02000000
15 17  
16 18 #ifdef CONFIG_SYS_FSL_IFC_LE
17 19 #define ifc_in32(a) in_le32(a)
... ... @@ -367,6 +369,8 @@
367 369 */
368 370 /* Auto Boot Mode */
369 371 #define IFC_NAND_NCFGR_BOOT 0x80000000
  372 +/* SRAM INIT EN */
  373 +#define IFC_NAND_SRAM_INIT_EN 0x20000000
370 374 /* Addressing Mode-ROW0+n/COL0 */
371 375 #define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000
372 376 /* Addressing Mode-ROW0+n/COL0+n */
include/linux/immap_qe.h
Diff comments   View file @ d5f8a6d
  1 +/*
  2 + * QUICC Engine (QE) Internal Memory Map.
  3 + * The Internal Memory Map for devices with QE on them. This
  4 + * is the superset of all QE devices (8360, etc.).
  5 + *
  6 + * Copyright (c) 2006-2009, 2011 Freescale Semiconductor, Inc.
  7 + * Author: Shlomi Gridih <gridish@freescale.com>
  8 + *
  9 + * SPDX-License-Identifier: GPL-2.0+
  10 + */
  11 +
  12 +#ifndef __IMMAP_QE_H__
  13 +#define __IMMAP_QE_H__
  14 +
  15 +#ifdef CONFIG_MPC83xx
  16 +#if defined(CONFIG_MPC8360)
  17 +#define QE_MURAM_SIZE 0xc000UL
  18 +#define MAX_QE_RISC 2
  19 +#define QE_NUM_OF_SNUM 28
  20 +#elif defined(CONFIG_MPC832x) || defined(CONFIG_MPC8309)
  21 +#define QE_MURAM_SIZE 0x4000UL
  22 +#define MAX_QE_RISC 1
  23 +#define QE_NUM_OF_SNUM 28
  24 +#endif
  25 +#endif
  26 +
  27 +/* QE I-RAM */
  28 +typedef struct qe_iram {
  29 + u32 iadd; /* I-RAM Address Register */
  30 + u32 idata; /* I-RAM Data Register */
  31 + u8 res0[0x4];
  32 + u32 iready;
  33 + u8 res1[0x70];
  34 +} __attribute__ ((packed)) qe_iram_t;
  35 +
  36 +/* QE Interrupt Controller */
  37 +typedef struct qe_ic {
  38 + u32 qicr;
  39 + u32 qivec;
  40 + u32 qripnr;
  41 + u32 qipnr;
  42 + u32 qipxcc;
  43 + u32 qipycc;
  44 + u32 qipwcc;
  45 + u32 qipzcc;
  46 + u32 qimr;
  47 + u32 qrimr;
  48 + u32 qicnr;
  49 + u8 res0[0x4];
  50 + u32 qiprta;
  51 + u32 qiprtb;
  52 + u8 res1[0x4];
  53 + u32 qricr;
  54 + u8 res2[0x20];
  55 + u32 qhivec;
  56 + u8 res3[0x1C];
  57 +} __attribute__ ((packed)) qe_ic_t;
  58 +
  59 +/* Communications Processor */
  60 +typedef struct cp_qe {
  61 + u32 cecr; /* QE command register */
  62 + u32 ceccr; /* QE controller configuration register */
  63 + u32 cecdr; /* QE command data register */
  64 + u8 res0[0xA];
  65 + u16 ceter; /* QE timer event register */
  66 + u8 res1[0x2];
  67 + u16 cetmr; /* QE timers mask register */
  68 + u32 cetscr; /* QE time-stamp timer control register */
  69 + u32 cetsr1; /* QE time-stamp register 1 */
  70 + u32 cetsr2; /* QE time-stamp register 2 */
  71 + u8 res2[0x8];
  72 + u32 cevter; /* QE virtual tasks event register */
  73 + u32 cevtmr; /* QE virtual tasks mask register */
  74 + u16 cercr; /* QE RAM control register */
  75 + u8 res3[0x2];
  76 + u8 res4[0x24];
  77 + u16 ceexe1; /* QE external request 1 event register */
  78 + u8 res5[0x2];
  79 + u16 ceexm1; /* QE external request 1 mask register */
  80 + u8 res6[0x2];
  81 + u16 ceexe2; /* QE external request 2 event register */
  82 + u8 res7[0x2];
  83 + u16 ceexm2; /* QE external request 2 mask register */
  84 + u8 res8[0x2];
  85 + u16 ceexe3; /* QE external request 3 event register */
  86 + u8 res9[0x2];
  87 + u16 ceexm3; /* QE external request 3 mask register */
  88 + u8 res10[0x2];
  89 + u16 ceexe4; /* QE external request 4 event register */
  90 + u8 res11[0x2];
  91 + u16 ceexm4; /* QE external request 4 mask register */
  92 + u8 res12[0x2];
  93 + u8 res13[0x280];
  94 +} __attribute__ ((packed)) cp_qe_t;
  95 +
  96 +/* QE Multiplexer */
  97 +typedef struct qe_mux {
  98 + u32 cmxgcr; /* CMX general clock route register */
  99 + u32 cmxsi1cr_l; /* CMX SI1 clock route low register */
  100 + u32 cmxsi1cr_h; /* CMX SI1 clock route high register */
  101 + u32 cmxsi1syr; /* CMX SI1 SYNC route register */
  102 + u32 cmxucr1; /* CMX UCC1, UCC3 clock route register */
  103 + u32 cmxucr2; /* CMX UCC5, UCC7 clock route register */
  104 + u32 cmxucr3; /* CMX UCC2, UCC4 clock route register */
  105 + u32 cmxucr4; /* CMX UCC6, UCC8 clock route register */
  106 + u32 cmxupcr; /* CMX UPC clock route register */
  107 + u8 res0[0x1C];
  108 +} __attribute__ ((packed)) qe_mux_t;
  109 +
  110 +/* QE Timers */
  111 +typedef struct qe_timers {
  112 + u8 gtcfr1; /* Timer 1 2 global configuration register */
  113 + u8 res0[0x3];
  114 + u8 gtcfr2; /* Timer 3 4 global configuration register */
  115 + u8 res1[0xB];
  116 + u16 gtmdr1; /* Timer 1 mode register */
  117 + u16 gtmdr2; /* Timer 2 mode register */
  118 + u16 gtrfr1; /* Timer 1 reference register */
  119 + u16 gtrfr2; /* Timer 2 reference register */
  120 + u16 gtcpr1; /* Timer 1 capture register */
  121 + u16 gtcpr2; /* Timer 2 capture register */
  122 + u16 gtcnr1; /* Timer 1 counter */
  123 + u16 gtcnr2; /* Timer 2 counter */
  124 + u16 gtmdr3; /* Timer 3 mode register */
  125 + u16 gtmdr4; /* Timer 4 mode register */
  126 + u16 gtrfr3; /* Timer 3 reference register */
  127 + u16 gtrfr4; /* Timer 4 reference register */
  128 + u16 gtcpr3; /* Timer 3 capture register */
  129 + u16 gtcpr4; /* Timer 4 capture register */
  130 + u16 gtcnr3; /* Timer 3 counter */
  131 + u16 gtcnr4; /* Timer 4 counter */
  132 + u16 gtevr1; /* Timer 1 event register */
  133 + u16 gtevr2; /* Timer 2 event register */
  134 + u16 gtevr3; /* Timer 3 event register */
  135 + u16 gtevr4; /* Timer 4 event register */
  136 + u16 gtps; /* Timer 1 prescale register */
  137 + u8 res2[0x46];
  138 +} __attribute__ ((packed)) qe_timers_t;
  139 +
  140 +/* BRG */
  141 +typedef struct qe_brg {
  142 + u32 brgc1; /* BRG1 configuration register */
  143 + u32 brgc2; /* BRG2 configuration register */
  144 + u32 brgc3; /* BRG3 configuration register */
  145 + u32 brgc4; /* BRG4 configuration register */
  146 + u32 brgc5; /* BRG5 configuration register */
  147 + u32 brgc6; /* BRG6 configuration register */
  148 + u32 brgc7; /* BRG7 configuration register */
  149 + u32 brgc8; /* BRG8 configuration register */
  150 + u32 brgc9; /* BRG9 configuration register */
  151 + u32 brgc10; /* BRG10 configuration register */
  152 + u32 brgc11; /* BRG11 configuration register */
  153 + u32 brgc12; /* BRG12 configuration register */
  154 + u32 brgc13; /* BRG13 configuration register */
  155 + u32 brgc14; /* BRG14 configuration register */
  156 + u32 brgc15; /* BRG15 configuration register */
  157 + u32 brgc16; /* BRG16 configuration register */
  158 + u8 res0[0x40];
  159 +} __attribute__ ((packed)) qe_brg_t;
  160 +
  161 +/* SPI */
  162 +typedef struct spi {
  163 + u8 res0[0x20];
  164 + u32 spmode; /* SPI mode register */
  165 + u8 res1[0x2];
  166 + u8 spie; /* SPI event register */
  167 + u8 res2[0x1];
  168 + u8 res3[0x2];
  169 + u8 spim; /* SPI mask register */
  170 + u8 res4[0x1];
  171 + u8 res5[0x1];
  172 + u8 spcom; /* SPI command register */
  173 + u8 res6[0x2];
  174 + u32 spitd; /* SPI transmit data register (cpu mode) */
  175 + u32 spird; /* SPI receive data register (cpu mode) */
  176 + u8 res7[0x8];
  177 +} __attribute__ ((packed)) spi_t;
  178 +
  179 +/* SI */
  180 +typedef struct si1 {
  181 + u16 siamr1; /* SI1 TDMA mode register */
  182 + u16 sibmr1; /* SI1 TDMB mode register */
  183 + u16 sicmr1; /* SI1 TDMC mode register */
  184 + u16 sidmr1; /* SI1 TDMD mode register */
  185 + u8 siglmr1_h; /* SI1 global mode register high */
  186 + u8 res0[0x1];
  187 + u8 sicmdr1_h; /* SI1 command register high */
  188 + u8 res2[0x1];
  189 + u8 sistr1_h; /* SI1 status register high */
  190 + u8 res3[0x1];
  191 + u16 sirsr1_h; /* SI1 RAM shadow address register high */
  192 + u8 sitarc1; /* SI1 RAM counter Tx TDMA */
  193 + u8 sitbrc1; /* SI1 RAM counter Tx TDMB */
  194 + u8 sitcrc1; /* SI1 RAM counter Tx TDMC */
  195 + u8 sitdrc1; /* SI1 RAM counter Tx TDMD */
  196 + u8 sirarc1; /* SI1 RAM counter Rx TDMA */
  197 + u8 sirbrc1; /* SI1 RAM counter Rx TDMB */
  198 + u8 sircrc1; /* SI1 RAM counter Rx TDMC */
  199 + u8 sirdrc1; /* SI1 RAM counter Rx TDMD */
  200 + u8 res4[0x8];
  201 + u16 siemr1; /* SI1 TDME mode register 16 bits */
  202 + u16 sifmr1; /* SI1 TDMF mode register 16 bits */
  203 + u16 sigmr1; /* SI1 TDMG mode register 16 bits */
  204 + u16 sihmr1; /* SI1 TDMH mode register 16 bits */
  205 + u8 siglmg1_l; /* SI1 global mode register low 8 bits */
  206 + u8 res5[0x1];
  207 + u8 sicmdr1_l; /* SI1 command register low 8 bits */
  208 + u8 res6[0x1];
  209 + u8 sistr1_l; /* SI1 status register low 8 bits */
  210 + u8 res7[0x1];
  211 + u16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits */
  212 + u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */
  213 + u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */
  214 + u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */
  215 + u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */
  216 + u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */
  217 + u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */
  218 + u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */
  219 + u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */
  220 + u8 res8[0x8];
  221 + u32 siml1; /* SI1 multiframe limit register */
  222 + u8 siedm1; /* SI1 extended diagnostic mode register */
  223 + u8 res9[0xBB];
  224 +} __attribute__ ((packed)) si1_t;
  225 +
  226 +/* SI Routing Tables */
  227 +typedef struct sir {
  228 + u8 tx[0x400];
  229 + u8 rx[0x400];
  230 + u8 res0[0x800];
  231 +} __attribute__ ((packed)) sir_t;
  232 +
  233 +/* USB Controller. */
  234 +typedef struct usb_ctlr {
  235 + u8 usb_usmod;
  236 + u8 usb_usadr;
  237 + u8 usb_uscom;
  238 + u8 res1[1];
  239 + u16 usb_usep1;
  240 + u16 usb_usep2;
  241 + u16 usb_usep3;
  242 + u16 usb_usep4;
  243 + u8 res2[4];
  244 + u16 usb_usber;
  245 + u8 res3[2];
  246 + u16 usb_usbmr;
  247 + u8 res4[1];
  248 + u8 usb_usbs;
  249 + u16 usb_ussft;
  250 + u8 res5[2];
  251 + u16 usb_usfrn;
  252 + u8 res6[0x22];
  253 +} __attribute__ ((packed)) usb_t;
  254 +
  255 +/* MCC */
  256 +typedef struct mcc {
  257 + u32 mcce; /* MCC event register */
  258 + u32 mccm; /* MCC mask register */
  259 + u32 mccf; /* MCC configuration register */
  260 + u32 merl; /* MCC emergency request level register */
  261 + u8 res0[0xF0];
  262 +} __attribute__ ((packed)) mcc_t;
  263 +
  264 +/* QE UCC Slow */
  265 +typedef struct ucc_slow {
  266 + u32 gumr_l; /* UCCx general mode register (low) */
  267 + u32 gumr_h; /* UCCx general mode register (high) */
  268 + u16 upsmr; /* UCCx protocol-specific mode register */
  269 + u8 res0[0x2];
  270 + u16 utodr; /* UCCx transmit on demand register */
  271 + u16 udsr; /* UCCx data synchronization register */
  272 + u16 ucce; /* UCCx event register */
  273 + u8 res1[0x2];
  274 + u16 uccm; /* UCCx mask register */
  275 + u8 res2[0x1];
  276 + u8 uccs; /* UCCx status register */
  277 + u8 res3[0x24];
  278 + u16 utpt;
  279 + u8 guemr; /* UCC general extended mode register */
  280 + u8 res4[0x200 - 0x091];
  281 +} __attribute__ ((packed)) ucc_slow_t;
  282 +
  283 +typedef struct ucc_mii_mng {
  284 + u32 miimcfg; /* MII management configuration reg */
  285 + u32 miimcom; /* MII management command reg */
  286 + u32 miimadd; /* MII management address reg */
  287 + u32 miimcon; /* MII management control reg */
  288 + u32 miimstat; /* MII management status reg */
  289 + u32 miimind; /* MII management indication reg */
  290 + u32 ifctl; /* interface control reg */
  291 + u32 ifstat; /* interface statux reg */
  292 +} __attribute__ ((packed))uec_mii_t;
  293 +
  294 +typedef struct ucc_ethernet {
  295 + u32 maccfg1; /* mac configuration reg. 1 */
  296 + u32 maccfg2; /* mac configuration reg. 2 */
  297 + u32 ipgifg; /* interframe gap reg. */
  298 + u32 hafdup; /* half-duplex reg. */
  299 + u8 res1[0x10];
  300 + u32 miimcfg; /* MII management configuration reg */
  301 + u32 miimcom; /* MII management command reg */
  302 + u32 miimadd; /* MII management address reg */
  303 + u32 miimcon; /* MII management control reg */
  304 + u32 miimstat; /* MII management status reg */
  305 + u32 miimind; /* MII management indication reg */
  306 + u32 ifctl; /* interface control reg */
  307 + u32 ifstat; /* interface statux reg */
  308 + u32 macstnaddr1; /* mac station address part 1 reg */
  309 + u32 macstnaddr2; /* mac station address part 2 reg */
  310 + u8 res2[0x8];
  311 + u32 uempr; /* UCC Ethernet Mac parameter reg */
  312 + u32 utbipar; /* UCC tbi address reg */
  313 + u16 uescr; /* UCC Ethernet statistics control reg */
  314 + u8 res3[0x180 - 0x15A];
  315 + u32 tx64; /* Total number of frames (including bad
  316 + * frames) transmitted that were exactly
  317 + * of the minimal length (64 for un tagged,
  318 + * 68 for tagged, or with length exactly
  319 + * equal to the parameter MINLength */
  320 + u32 tx127; /* Total number of frames (including bad
  321 + * frames) transmitted that were between
  322 + * MINLength (Including FCS length==4)
  323 + * and 127 octets */
  324 + u32 tx255; /* Total number of frames (including bad
  325 + * frames) transmitted that were between
  326 + * 128 (Including FCS length==4) and 255
  327 + * octets */
  328 + u32 rx64; /* Total number of frames received including
  329 + * bad frames that were exactly of the
  330 + * mninimal length (64 bytes) */
  331 + u32 rx127; /* Total number of frames (including bad
  332 + * frames) received that were between
  333 + * MINLength (Including FCS length==4)
  334 + * and 127 octets */
  335 + u32 rx255; /* Total number of frames (including
  336 + * bad frames) received that were between
  337 + * 128 (Including FCS length==4) and 255
  338 + * octets */
  339 + u32 txok; /* Total number of octets residing in frames
  340 + * that where involved in succesfull
  341 + * transmission */
  342 + u16 txcf; /* Total number of PAUSE control frames
  343 + * transmitted by this MAC */
  344 + u8 res4[0x2];
  345 + u32 tmca; /* Total number of frames that were transmitted
  346 + * succesfully with the group address bit set
  347 + * that are not broadcast frames */
  348 + u32 tbca; /* Total number of frames transmitted
  349 + * succesfully that had destination address
  350 + * field equal to the broadcast address */
  351 + u32 rxfok; /* Total number of frames received OK */
  352 + u32 rxbok; /* Total number of octets received OK */
  353 + u32 rbyt; /* Total number of octets received including
  354 + * octets in bad frames. Must be implemented
  355 + * in HW because it includes octets in frames
  356 + * that never even reach the UCC */
  357 + u32 rmca; /* Total number of frames that were received
  358 + * succesfully with the group address bit set
  359 + * that are not broadcast frames */
  360 + u32 rbca; /* Total number of frames received succesfully
  361 + * that had destination address equal to the
  362 + * broadcast address */
  363 + u32 scar; /* Statistics carry register */
  364 + u32 scam; /* Statistics caryy mask register */
  365 + u8 res5[0x200 - 0x1c4];
  366 +} __attribute__ ((packed)) uec_t;
  367 +
  368 +/* QE UCC Fast */
  369 +typedef struct ucc_fast {
  370 + u32 gumr; /* UCCx general mode register */
  371 + u32 upsmr; /* UCCx protocol-specific mode register */
  372 + u16 utodr; /* UCCx transmit on demand register */
  373 + u8 res0[0x2];
  374 + u16 udsr; /* UCCx data synchronization register */
  375 + u8 res1[0x2];
  376 + u32 ucce; /* UCCx event register */
  377 + u32 uccm; /* UCCx mask register. */
  378 + u8 uccs; /* UCCx status register */
  379 + u8 res2[0x7];
  380 + u32 urfb; /* UCC receive FIFO base */
  381 + u16 urfs; /* UCC receive FIFO size */
  382 + u8 res3[0x2];
  383 + u16 urfet; /* UCC receive FIFO emergency threshold */
  384 + u16 urfset; /* UCC receive FIFO special emergency
  385 + * threshold */
  386 + u32 utfb; /* UCC transmit FIFO base */
  387 + u16 utfs; /* UCC transmit FIFO size */
  388 + u8 res4[0x2];
  389 + u16 utfet; /* UCC transmit FIFO emergency threshold */
  390 + u8 res5[0x2];
  391 + u16 utftt; /* UCC transmit FIFO transmit threshold */
  392 + u8 res6[0x2];
  393 + u16 utpt; /* UCC transmit polling timer */
  394 + u8 res7[0x2];
  395 + u32 urtry; /* UCC retry counter register */
  396 + u8 res8[0x4C];
  397 + u8 guemr; /* UCC general extended mode register */
  398 + u8 res9[0x100 - 0x091];
  399 + uec_t ucc_eth;
  400 +} __attribute__ ((packed)) ucc_fast_t;
  401 +
  402 +/* QE UCC */
  403 +typedef struct ucc_common {
  404 + u8 res1[0x90];
  405 + u8 guemr;
  406 + u8 res2[0x200 - 0x091];
  407 +} __attribute__ ((packed)) ucc_common_t;
  408 +
  409 +typedef struct ucc {
  410 + union {
  411 + ucc_slow_t slow;
  412 + ucc_fast_t fast;
  413 + ucc_common_t common;
  414 + };
  415 +} __attribute__ ((packed)) ucc_t;
  416 +
  417 +/* MultiPHY UTOPIA POS Controllers (UPC) */
  418 +typedef struct upc {
  419 + u32 upgcr; /* UTOPIA/POS general configuration register */
  420 + u32 uplpa; /* UTOPIA/POS last PHY address */
  421 + u32 uphec; /* ATM HEC register */
  422 + u32 upuc; /* UTOPIA/POS UCC configuration */
  423 + u32 updc1; /* UTOPIA/POS device 1 configuration */
  424 + u32 updc2; /* UTOPIA/POS device 2 configuration */
  425 + u32 updc3; /* UTOPIA/POS device 3 configuration */
  426 + u32 updc4; /* UTOPIA/POS device 4 configuration */
  427 + u32 upstpa; /* UTOPIA/POS STPA threshold */
  428 + u8 res0[0xC];
  429 + u32 updrs1_h; /* UTOPIA/POS device 1 rate select */
  430 + u32 updrs1_l; /* UTOPIA/POS device 1 rate select */
  431 + u32 updrs2_h; /* UTOPIA/POS device 2 rate select */
  432 + u32 updrs2_l; /* UTOPIA/POS device 2 rate select */
  433 + u32 updrs3_h; /* UTOPIA/POS device 3 rate select */
  434 + u32 updrs3_l; /* UTOPIA/POS device 3 rate select */
  435 + u32 updrs4_h; /* UTOPIA/POS device 4 rate select */
  436 + u32 updrs4_l; /* UTOPIA/POS device 4 rate select */
  437 + u32 updrp1; /* UTOPIA/POS device 1 receive priority low */
  438 + u32 updrp2; /* UTOPIA/POS device 2 receive priority low */
  439 + u32 updrp3; /* UTOPIA/POS device 3 receive priority low */
  440 + u32 updrp4; /* UTOPIA/POS device 4 receive priority low */
  441 + u32 upde1; /* UTOPIA/POS device 1 event */
  442 + u32 upde2; /* UTOPIA/POS device 2 event */
  443 + u32 upde3; /* UTOPIA/POS device 3 event */
  444 + u32 upde4; /* UTOPIA/POS device 4 event */
  445 + u16 uprp1;
  446 + u16 uprp2;
  447 + u16 uprp3;
  448 + u16 uprp4;
  449 + u8 res1[0x8];
  450 + u16 uptirr1_0; /* Device 1 transmit internal rate 0 */
  451 + u16 uptirr1_1; /* Device 1 transmit internal rate 1 */
  452 + u16 uptirr1_2; /* Device 1 transmit internal rate 2 */
  453 + u16 uptirr1_3; /* Device 1 transmit internal rate 3 */
  454 + u16 uptirr2_0; /* Device 2 transmit internal rate 0 */
  455 + u16 uptirr2_1; /* Device 2 transmit internal rate 1 */
  456 + u16 uptirr2_2; /* Device 2 transmit internal rate 2 */
  457 + u16 uptirr2_3; /* Device 2 transmit internal rate 3 */
  458 + u16 uptirr3_0; /* Device 3 transmit internal rate 0 */
  459 + u16 uptirr3_1; /* Device 3 transmit internal rate 1 */
  460 + u16 uptirr3_2; /* Device 3 transmit internal rate 2 */
  461 + u16 uptirr3_3; /* Device 3 transmit internal rate 3 */
  462 + u16 uptirr4_0; /* Device 4 transmit internal rate 0 */
  463 + u16 uptirr4_1; /* Device 4 transmit internal rate 1 */
  464 + u16 uptirr4_2; /* Device 4 transmit internal rate 2 */
  465 + u16 uptirr4_3; /* Device 4 transmit internal rate 3 */
  466 + u32 uper1; /* Device 1 port enable register */
  467 + u32 uper2; /* Device 2 port enable register */
  468 + u32 uper3; /* Device 3 port enable register */
  469 + u32 uper4; /* Device 4 port enable register */
  470 + u8 res2[0x150];
  471 +} __attribute__ ((packed)) upc_t;
  472 +
  473 +/* SDMA */
  474 +typedef struct sdma {
  475 + u32 sdsr; /* Serial DMA status register */
  476 + u32 sdmr; /* Serial DMA mode register */
  477 + u32 sdtr1; /* SDMA system bus threshold register */
  478 + u32 sdtr2; /* SDMA secondary bus threshold register */
  479 + u32 sdhy1; /* SDMA system bus hysteresis register */
  480 + u32 sdhy2; /* SDMA secondary bus hysteresis register */
  481 + u32 sdta1; /* SDMA system bus address register */
  482 + u32 sdta2; /* SDMA secondary bus address register */
  483 + u32 sdtm1; /* SDMA system bus MSNUM register */
  484 + u32 sdtm2; /* SDMA secondary bus MSNUM register */
  485 + u8 res0[0x10];
  486 + u32 sdaqr; /* SDMA address bus qualify register */
  487 + u32 sdaqmr; /* SDMA address bus qualify mask register */
  488 + u8 res1[0x4];
  489 + u32 sdwbcr; /* SDMA CAM entries base register */
  490 + u8 res2[0x38];
  491 +} __attribute__ ((packed)) sdma_t;
  492 +
  493 +/* Debug Space */
  494 +typedef struct dbg {
  495 + u32 bpdcr; /* Breakpoint debug command register */
  496 + u32 bpdsr; /* Breakpoint debug status register */
  497 + u32 bpdmr; /* Breakpoint debug mask register */
  498 + u32 bprmrr0; /* Breakpoint request mode risc register 0 */
  499 + u32 bprmrr1; /* Breakpoint request mode risc register 1 */
  500 + u8 res0[0x8];
  501 + u32 bprmtr0; /* Breakpoint request mode trb register 0 */
  502 + u32 bprmtr1; /* Breakpoint request mode trb register 1 */
  503 + u8 res1[0x8];
  504 + u32 bprmir; /* Breakpoint request mode immediate register */
  505 + u32 bprmsr; /* Breakpoint request mode serial register */
  506 + u32 bpemr; /* Breakpoint exit mode register */
  507 + u8 res2[0x48];
  508 +} __attribute__ ((packed)) dbg_t;
  509 +
  510 +/*
  511 + * RISC Special Registers (Trap and Breakpoint). These are described in
  512 + * the QE Developer's Handbook.
  513 +*/
  514 +typedef struct rsp {
  515 + u32 tibcr[16]; /* Trap/instruction breakpoint control regs */
  516 + u8 res0[64];
  517 + u32 ibcr0;
  518 + u32 ibs0;
  519 + u32 ibcnr0;
  520 + u8 res1[4];
  521 + u32 ibcr1;
  522 + u32 ibs1;
  523 + u32 ibcnr1;
  524 + u32 npcr;
  525 + u32 dbcr;
  526 + u32 dbar;
  527 + u32 dbamr;
  528 + u32 dbsr;
  529 + u32 dbcnr;
  530 + u8 res2[12];
  531 + u32 dbdr_h;
  532 + u32 dbdr_l;
  533 + u32 dbdmr_h;
  534 + u32 dbdmr_l;
  535 + u32 bsr;
  536 + u32 bor;
  537 + u32 bior;
  538 + u8 res3[4];
  539 + u32 iatr[4];
  540 + u32 eccr; /* Exception control configuration register */
  541 + u32 eicr;
  542 + u8 res4[0x100-0xf8];
  543 +} __attribute__ ((packed)) rsp_t;
  544 +
  545 +typedef struct qe_immap {
  546 + qe_iram_t iram; /* I-RAM */
  547 + qe_ic_t ic; /* Interrupt Controller */
  548 + cp_qe_t cp; /* Communications Processor */
  549 + qe_mux_t qmx; /* QE Multiplexer */
  550 + qe_timers_t qet; /* QE Timers */
  551 + spi_t spi[0x2]; /* spi */
  552 + mcc_t mcc; /* mcc */
  553 + qe_brg_t brg; /* brg */
  554 + usb_t usb; /* USB */
  555 + si1_t si1; /* SI */
  556 + u8 res11[0x800];
  557 + sir_t sir; /* SI Routing Tables */
  558 + ucc_t ucc1; /* ucc1 */
  559 + ucc_t ucc3; /* ucc3 */
  560 + ucc_t ucc5; /* ucc5 */
  561 + ucc_t ucc7; /* ucc7 */
  562 + u8 res12[0x600];
  563 + upc_t upc1; /* MultiPHY UTOPIA POS Controller 1 */
  564 + ucc_t ucc2; /* ucc2 */
  565 + ucc_t ucc4; /* ucc4 */
  566 + ucc_t ucc6; /* ucc6 */
  567 + ucc_t ucc8; /* ucc8 */
  568 + u8 res13[0x600];
  569 + upc_t upc2; /* MultiPHY UTOPIA POS Controller 2 */
  570 + sdma_t sdma; /* SDMA */
  571 + dbg_t dbg; /* Debug Space */
  572 + rsp_t rsp[0x2]; /* RISC Special Registers
  573 + * (Trap and Breakpoint) */
  574 + u8 res14[0x300];
  575 + u8 res15[0x3A00];
  576 + u8 res16[0x8000]; /* 0x108000 - 0x110000 */
  577 + u8 muram[QE_MURAM_SIZE];
  578 +} __attribute__ ((packed)) qe_map_t;
  579 +
  580 +extern qe_map_t *qe_immr;
  581 +
  582 +#endif /* __IMMAP_QE_H__ */
... ... @@ -38,7 +38,7 @@
38 38 #define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR)
39 39  
40 40 #elif defined(CONFIG_MPC8360)
41   -#include <asm/immap_qe.h>
  41 +#include <linux/immap_qe.h>
42 42 #define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR)
43 43  
44 44 #elif defined (CONFIG_MPC85xx)