Eric Lee / smarc-uboot

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Commit d5f904fc3c48871e084fdcea9de38aa1c3579122

Authored by Ye Li
1 parent 24066e390f
Exists in smarc-n7.1.2_2.0.0-ga and in 4 other branches smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m

MLK-14326-3 mx6qsabreauto: Enable OF_CONTROL and DM driver 

Enable OF_CONTROL and DM driver on mx6qsabreauto.
1. Add the imx6qsabreauto relevant DTS file for using DTB.
2. Modify PMIC initialization codes to use DM PMIC driver.
3. Modify to use PCA953X DM driver
4. Remove NAND from default, since the default imx6q-sabreauto.dts disabled
   the nand. The pins are conflicted with UART3, while UART3 is enabled.
5. For NAND build configuration, remove the USB, since the imx6q-sabreauto-gpmi-weim.dts
   will have pin conflicts on steer logic.
6. GPIO requests added.

Signed-off-by: Ye Li <ye.li@nxp.com>

Showing 14 changed files with 1650 additions and 91 deletions Side-by-side Diff

arch/arm/dts/Makefile
Diff comments   View file @ d5f904f
... ... @@ -319,6 +319,9 @@
319 319 imx6dl-sabresd.dtb \
320 320 imx6q-icore.dtb \
321 321 imx6q-icore-rqs.dtb \
  322 + imx6q-sabreauto.dtb \
  323 + imx6q-sabreauto-ecspi.dtb \
  324 + imx6q-sabreauto-gpmi-weim.dtb \
322 325 imx6sx-sabreauto.dtb \
323 326 imx6q-sabresd.dtb \
324 327 imx6qp-sabresd.dtb \
arch/arm/dts/imx6q-sabreauto-ecspi.dts
Diff comments   View file @ d5f904f
  1 +/*
  2 + * Copyright (C) 2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * This program is free software; you can redistribute it and/or modify
  5 + * it under the terms of the GNU General Public License version 2 as
  6 + * published by the Free Software Foundation.
  7 + */
  8 +
  9 +#include "imx6q-sabreauto.dts"
  10 +
  11 +&ecspi1 {
  12 + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
  13 + status = "okay";
  14 +};
  15 +
  16 +&can2 {
  17 + /* max7310_c on i2c3 is gone */
  18 + status = "disabled";
  19 +};
  20 +
  21 +&i2c3 {
  22 + /* pin conflict with ecspi1 */
  23 + status = "disabled";
  24 +};
  25 +
  26 +&uart3 {
  27 + /* the uart3 depends on the i2c3, so disable it too. */
  28 + status = "disabled";
  29 +};
  30 +
  31 +&usbh1 {
  32 + /* max7310_b on i2c3 is gone */
  33 + status = "disabled";
  34 +};
  35 +
  36 +&usbotg {
  37 + /* max7310_c on i2c3 is gone */
  38 + status = "okay";
  39 + dr_mode = "peripheral";
  40 +};
arch/arm/dts/imx6q-sabreauto-gpmi-weim.dts
Diff comments   View file @ d5f904f
  1 +/*
  2 + * Copyright (C) 2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * This program is free software; you can redistribute it and/or modify
  5 + * it under the terms of the GNU General Public License version 2 as
  6 + * published by the Free Software Foundation.
  7 + */
  8 +
  9 +#include "imx6q-sabreauto.dts"
  10 +
  11 +&ecspi1 {
  12 + /* pin conflict with weim */
  13 + status = "disabled";
  14 +};
  15 +
  16 +&can2 {
  17 + /* max7310_c on i2c3 is gone */
  18 + status = "disabled";
  19 +};
  20 +
  21 +&gpmi {
  22 + status = "okay";
  23 +};
  24 +
  25 +&i2c3 {
  26 + /* pin conflict with weim */
  27 + status = "disabled";
  28 +};
  29 +
  30 +&uart3 {
  31 + /* pin conflict with gpmi and weim */
  32 + status = "disabled";
  33 +};
  34 +
  35 +&usbh1 {
  36 + /* max7310_b on i2c3 is gone */
  37 + status = "disabled";
  38 +};
  39 +
  40 +&usbotg {
  41 + /* max7310_c on i2c3 is gone */
  42 + status = "okay";
  43 + dr_mode = "peripheral";
  44 +};
  45 +
  46 +&weim {
  47 + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
  48 + status = "okay";
  49 +};
arch/arm/dts/imx6q-sabreauto.dts
Diff comments   View file @ d5f904f
  1 +/*
  2 + * Copyright 2012-2015 Freescale Semiconductor, Inc.
  3 + * Copyright 2011 Linaro Ltd.
  4 + *
  5 + * The code contained herein is licensed under the GNU General Public
  6 + * License. You may obtain a copy of the GNU General Public License
  7 + * Version 2 or later at the following locations:
  8 + *
  9 + * http://www.opensource.org/licenses/gpl-license.html
  10 + * http://www.gnu.org/copyleft/gpl.html
  11 + */
  12 +
  13 +/dts-v1/;
  14 +
  15 +#include "imx6q.dtsi"
  16 +#include "imx6qdl-sabreauto.dtsi"
  17 +
  18 +/ {
  19 + model = "Freescale i.MX6 Quad SABRE Automotive Board";
  20 + compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
  21 +};
  22 +
  23 +&ldb {
  24 + lvds-channel@0 {
  25 + crtc = "ipu2-di0";
  26 + };
  27 + lvds-channel@1 {
  28 + crtc = "ipu2-di1";
  29 + };
  30 +};
  31 +&mxcfb1 {
  32 + status = "okay";
  33 +};
  34 +&mxcfb2 {
  35 + status = "okay";
  36 +};
  37 +&mxcfb3 {
  38 + status = "okay";
  39 +};
  40 +&mxcfb4 {
  41 + status = "okay";
  42 +};
  43 +&sata {
  44 + status = "okay";
  45 +};
arch/arm/dts/imx6qdl-sabreauto.dtsi
Diff comments   View file @ d5f904f
Changes suppressed. Click to show
  1 +/*
  2 + * Copyright 2012-2015 Freescale Semiconductor, Inc.
  3 + * Copyright 2011 Linaro Ltd.
  4 + *
  5 + * The code contained herein is licensed under the GNU General Public
  6 + * License. You may obtain a copy of the GNU General Public License
  7 + * Version 2 or later at the following locations:
  8 + *
  9 + * http://www.opensource.org/licenses/gpl-license.html
  10 + * http://www.gnu.org/copyleft/gpl.html
  11 + */
  12 +
  13 +#include <dt-bindings/gpio/gpio.h>
  14 +#include <dt-bindings/input/input.h>
  15 +
  16 +/ {
  17 + aliases {
  18 + mxcfb0 = &mxcfb1;
  19 + mxcfb1 = &mxcfb2;
  20 + mxcfb2 = &mxcfb3;
  21 + mxcfb3 = &mxcfb4;
  22 + };
  23 +
  24 + gpio-keys {
  25 + compatible = "gpio-keys1";
  26 + pinctrl-names = "default";
  27 + pinctrl-0 = <&pinctrl_gpio_keys>;
  28 +
  29 + home {
  30 + label = "Home";
  31 + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
  32 + gpio-key,wakeup;
  33 + linux,code = <KEY_HOME>;
  34 + };
  35 +
  36 + back {
  37 + label = "Back";
  38 + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
  39 + gpio-key,wakeup;
  40 + linux,code = <KEY_BACK>;
  41 + };
  42 +
  43 + program {
  44 + label = "Program";
  45 + gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
  46 + gpio-key,wakeup;
  47 + linux,code = <KEY_PROGRAM>;
  48 + };
  49 +
  50 + volume-up {
  51 + label = "Volume Up";
  52 + gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
  53 + gpio-key,wakeup;
  54 + linux,code = <KEY_VOLUMEUP>;
  55 + };
  56 +
  57 + volume-down {
  58 + label = "Volume Down";
  59 + gpios = <&gpio5 14 GPIO_ACTIVE_LOW>;
  60 + gpio-key,wakeup;
  61 + linux,code = <KEY_VOLUMEDOWN>;
  62 + };
  63 + };
  64 +
  65 + memory: memory {
  66 + reg = <0x10000000 0x80000000>;
  67 + };
  68 +
  69 + leds {
  70 + compatible = "gpio-leds";
  71 + pinctrl-names = "default";
  72 + pinctrl-0 = <&pinctrl_gpio_leds>;
  73 +
  74 + user {
  75 + label = "debug";
  76 + gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
  77 + };
  78 + };
  79 +
  80 + regulators {
  81 + compatible = "simple-bus";
  82 + #address-cells = <1>;
  83 + #size-cells = <0>;
  84 +
  85 + reg_usb_h1_vbus: regulator@0 {
  86 + compatible = "regulator-fixed";
  87 + reg = <0>;
  88 + regulator-name = "usb_h1_vbus";
  89 + regulator-min-microvolt = <5000000>;
  90 + regulator-max-microvolt = <5000000>;
  91 + gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
  92 + enable-active-high;
  93 + };
  94 +
  95 + reg_usb_otg_vbus: regulator@1 {
  96 + compatible = "regulator-fixed";
  97 + reg = <1>;
  98 + regulator-name = "usb_otg_vbus";
  99 + regulator-min-microvolt = <5000000>;
  100 + regulator-max-microvolt = <5000000>;
  101 + gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
  102 + enable-active-high;
  103 + };
  104 +
  105 + reg_audio: regulator@2 {
  106 + compatible = "regulator-fixed";
  107 + reg = <2>;
  108 + regulator-name = "cs42888_supply";
  109 + regulator-min-microvolt = <3300000>;
  110 + regulator-max-microvolt = <3300000>;
  111 + regulator-always-on;
  112 + };
  113 +
  114 + reg_3p3v: 3p3v {
  115 + compatible = "regulator-fixed";
  116 + regulator-name = "3P3V";
  117 + regulator-min-microvolt = <3300000>;
  118 + regulator-max-microvolt = <3300000>;
  119 + regulator-always-on;
  120 + };
  121 +
  122 + reg_si4763_vio1: regulator@3 {
  123 + compatible = "regulator-fixed";
  124 + reg = <3>;
  125 + regulator-name = "vio1";
  126 + regulator-min-microvolt = <3300000>;
  127 + regulator-max-microvolt = <3300000>;
  128 + regulator-always-on;
  129 + };
  130 +
  131 + reg_si4763_vio2: regulator@4 {
  132 + compatible = "regulator-fixed";
  133 + reg = <4>;
  134 + regulator-name = "vio2";
  135 + regulator-min-microvolt = <3300000>;
  136 + regulator-max-microvolt = <3300000>;
  137 + regulator-always-on;
  138 + };
  139 +
  140 + reg_si4763_vd: regulator@5 {
  141 + compatible = "regulator-fixed";
  142 + reg = <5>;
  143 + regulator-name = "vd";
  144 + regulator-min-microvolt = <3300000>;
  145 + regulator-max-microvolt = <3300000>;
  146 + regulator-always-on;
  147 + };
  148 +
  149 + reg_si4763_va: regulator@6 {
  150 + compatible = "regulator-fixed";
  151 + reg = <6>;
  152 + regulator-name = "va";
  153 + regulator-min-microvolt = <5000000>;
  154 + regulator-max-microvolt = <5000000>;
  155 + regulator-always-on;
  156 + };
  157 +
  158 + reg_sd3_vmmc: regulator@7 {
  159 + compatible = "regulator-fixed";
  160 + regulator-name = "P3V3_SDa_SWITCHED";
  161 + regulator-min-microvolt = <3300000>;
  162 + regulator-max-microvolt = <3300000>;
  163 + gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
  164 + enable-active-high;
  165 + /* remove below line to enable this regulator */
  166 + status = "disabled";
  167 + };
  168 +
  169 + reg_can_en: regulator@8 {
  170 + compatible = "regulator-fixed";
  171 + reg = <8>;
  172 + regulator-name = "can-en";
  173 + regulator-min-microvolt = <3300000>;
  174 + regulator-max-microvolt = <3300000>;
  175 + gpio = <&max7310_b 6 GPIO_ACTIVE_HIGH>;
  176 + enable-active-high;
  177 + };
  178 +
  179 + reg_can_stby: regulator@9 {
  180 + compatible = "regulator-fixed";
  181 + reg = <9>;
  182 + regulator-name = "can-stby";
  183 + regulator-min-microvolt = <3300000>;
  184 + regulator-max-microvolt = <3300000>;
  185 + gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>;
  186 + enable-active-high;
  187 + vin-supply = <&reg_can_en>;
  188 + };
  189 + };
  190 +
  191 + hannstar_cabc {
  192 + compatible = "hannstar,cabc";
  193 +
  194 + lvds_share {
  195 + gpios = <&max7310_a 0 GPIO_ACTIVE_HIGH>;
  196 + };
  197 + };
  198 +
  199 + sound-hdmi {
  200 + compatible = "fsl,imx6q-audio-hdmi",
  201 + "fsl,imx-audio-hdmi";
  202 + model = "imx-audio-hdmi";
  203 + hdmi-controller = <&hdmi_audio>;
  204 + };
  205 +
  206 + mxcfb1: fb@0 {
  207 + compatible = "fsl,mxc_sdc_fb";
  208 + disp_dev = "ldb";
  209 + interface_pix_fmt = "RGB666";
  210 + default_bpp = <16>;
  211 + int_clk = <0>;
  212 + late_init = <0>;
  213 + status = "disabled";
  214 + };
  215 +
  216 + mxcfb2: fb@1 {
  217 + compatible = "fsl,mxc_sdc_fb";
  218 + disp_dev = "hdmi";
  219 + interface_pix_fmt = "RGB24";
  220 + mode_str ="1920x1080M@60";
  221 + default_bpp = <24>;
  222 + int_clk = <0>;
  223 + late_init = <0>;
  224 + status = "disabled";
  225 + };
  226 +
  227 + mxcfb3: fb@2 {
  228 + compatible = "fsl,mxc_sdc_fb";
  229 + disp_dev = "lcd";
  230 + interface_pix_fmt = "RGB565";
  231 + mode_str ="CLAA-WVGA";
  232 + default_bpp = <16>;
  233 + int_clk = <0>;
  234 + late_init = <0>;
  235 + status = "disabled";
  236 + };
  237 +
  238 + mxcfb4: fb@3 {
  239 + compatible = "fsl,mxc_sdc_fb";
  240 + disp_dev = "ldb";
  241 + interface_pix_fmt = "RGB666";
  242 + default_bpp = <16>;
  243 + int_clk = <0>;
  244 + late_init = <0>;
  245 + status = "disabled";
  246 + };
  247 +
  248 + clocks {
  249 + codec_osc: anaclk2 {
  250 + compatible = "fixed-clock";
  251 + #clock-cells = <0>;
  252 + clock-frequency = <24576000>;
  253 + };
  254 + };
  255 +
  256 + sound-cs42888 {
  257 + compatible = "fsl,imx6-sabreauto-cs42888",
  258 + "fsl,imx-audio-cs42888";
  259 + model = "imx-cs42888";
  260 + esai-controller = <&esai>;
  261 + asrc-controller = <&asrc>;
  262 + audio-codec = <&codec>;
  263 + };
  264 +
  265 + sound-fm {
  266 + compatible = "fsl,imx-audio-si476x",
  267 + "fsl,imx-tuner-si476x";
  268 + model = "imx-radio-si4763";
  269 + ssi-controller = <&ssi2>;
  270 + fm-controller = <&si476x_codec>;
  271 + mux-int-port = <2>;
  272 + mux-ext-port = <5>;
  273 + };
  274 +
  275 + sound-spdif {
  276 + compatible = "fsl,imx-audio-spdif",
  277 + "fsl,imx-sabreauto-spdif";
  278 + model = "imx-spdif";
  279 + spdif-controller = <&spdif>;
  280 + spdif-in;
  281 + };
  282 +
  283 + backlight {
  284 + compatible = "pwm-backlight";
  285 + pwms = <&pwm3 0 5000000>;
  286 + brightness-levels = <0 4 8 16 32 64 128 255>;
  287 + default-brightness-level = <7>;
  288 + status = "okay";
  289 + };
  290 +
  291 + v4l2_cap_0 {
  292 + compatible = "fsl,imx6q-v4l2-capture";
  293 + ipu_id = <0>;
  294 + csi_id = <0>;
  295 + mclk_source = <0>;
  296 + status = "okay";
  297 + };
  298 +
  299 + v4l2_out {
  300 + compatible = "fsl,mxc_v4l2_output";
  301 + status = "okay";
  302 + };
  303 +};
  304 +
  305 +&audmux {
  306 + pinctrl-names = "default";
  307 + pinctrl-0 = <&pinctrl_audmux>;
  308 + status = "okay";
  309 +};
  310 +
  311 +&clks {
  312 + assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
  313 + <&clks IMX6QDL_PLL4_BYPASS>,
  314 + <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
  315 + assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
  316 + <&clks IMX6QDL_PLL4_BYPASS_SRC>;
  317 + assigned-clock-rates = <0>, <0>, <24576000>;
  318 + fsl,ldb-di0-parent = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
  319 + fsl,ldb-di1-parent = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
  320 +};
  321 +
  322 +&dcic1 {
  323 + dcic_id = <0>;
  324 + dcic_mux = "dcic-hdmi";
  325 + status = "okay";
  326 +};
  327 +
  328 +&dcic2 {
  329 + dcic_id = <1>;
  330 + dcic_mux = "dcic-lvds0";
  331 + status = "okay";
  332 +};
  333 +
  334 +&ecspi1 {
  335 + fsl,spi-num-chipselects = <1>;
  336 + cs-gpios = <&gpio3 19 0>;
  337 + pinctrl-names = "default";
  338 + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
  339 + status = "disabled"; /* pin conflict with WEIM NOR */
  340 +
  341 + flash: m25p80@0 {
  342 + #address-cells = <1>;
  343 + #size-cells = <1>;
  344 + compatible = "st,m25p32";
  345 + spi-max-frequency = <20000000>;
  346 + reg = <0>;
  347 + };
  348 +};
  349 +
  350 +&esai {
  351 + pinctrl-names = "default";
  352 + pinctrl-0 = <&pinctrl_esai>;
  353 + assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>,
  354 + <&clks IMX6QDL_CLK_ESAI_EXTAL>;
  355 + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
  356 + assigned-clock-rates = <0>, <24576000>;
  357 + status = "okay";
  358 +};
  359 +
  360 +&fec {
  361 + pinctrl-names = "default";
  362 + pinctrl-0 = <&pinctrl_enet>;
  363 + phy-mode = "rgmii";
  364 + fsl,magic-packet;
  365 + status = "okay";
  366 +};
  367 +
  368 +&can1 {
  369 + pinctrl-names = "default";
  370 + pinctrl-0 = <&pinctrl_flexcan1>;
  371 + pinctrl-assert-gpios = <&max7310_b 3 GPIO_ACTIVE_HIGH>; /* TX */
  372 + xceiver-supply = <&reg_can_stby>;
  373 + status = "disabled"; /* pin conflict with fec */
  374 +};
  375 +
  376 +&can2 {
  377 + pinctrl-names = "default";
  378 + pinctrl-0 = <&pinctrl_flexcan2>;
  379 + xceiver-supply = <&reg_can_stby>;
  380 + status = "okay";
  381 +};
  382 +
  383 +&gpmi {
  384 + pinctrl-names = "default";
  385 + pinctrl-0 = <&pinctrl_gpmi_nand>;
  386 + status = "disabled"; /* pin conflict with uart3 */
  387 + nand-on-flash-bbt;
  388 +};
  389 +
  390 +&hdmi_audio {
  391 + status = "okay";
  392 +};
  393 +
  394 +&hdmi_cec {
  395 + pinctrl-names = "default";
  396 + pinctrl-0 = <&pinctrl_hdmi_cec>;
  397 + status = "okay";
  398 +};
  399 +
  400 +&hdmi_core {
  401 + ipu_id = <0>;
  402 + disp_id = <1>;
  403 + status = "okay";
  404 +};
  405 +
  406 +&hdmi_video {
  407 + fsl,phy_reg_vlev = <0x0294>;
  408 + fsl,phy_reg_cksymtx = <0x800d>;
  409 + status = "okay";
  410 +};
  411 +
  412 +&i2c2 {
  413 + clock-frequency = <100000>;
  414 + pinctrl-names = "default";
  415 + pinctrl-0 = <&pinctrl_i2c2>;
  416 + status = "okay";
  417 +
  418 + egalax_ts@04 {
  419 + compatible = "eeti,egalax_ts";
  420 + reg = <0x04>;
  421 + pinctrl-names = "default";
  422 + pinctrl-0 = <&pinctrl_egalax_int>;
  423 + interrupt-parent = <&gpio2>;
  424 + interrupts = <28 2>;
  425 + wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
  426 + };
  427 +
  428 + pmic: pfuze100@08 {
  429 + compatible = "fsl,pfuze100";
  430 + reg = <0x08>;
  431 +
  432 + regulators {
  433 + sw1a_reg: sw1ab {
  434 + regulator-min-microvolt = <300000>;
  435 + regulator-max-microvolt = <1875000>;
  436 + regulator-boot-on;
  437 + regulator-always-on;
  438 + regulator-ramp-delay = <6250>;
  439 + };
  440 +
  441 + sw1c_reg: sw1c {
  442 + regulator-min-microvolt = <300000>;
  443 + regulator-max-microvolt = <1875000>;
  444 + regulator-boot-on;
  445 + regulator-always-on;
  446 + regulator-ramp-delay = <6250>;
  447 + };
  448 +
  449 + sw2_reg: sw2 {
  450 + regulator-min-microvolt = <800000>;
  451 + regulator-max-microvolt = <3300000>;
  452 + regulator-boot-on;
  453 + regulator-always-on;
  454 + };
  455 +
  456 + sw3a_reg: sw3a {
  457 + regulator-min-microvolt = <400000>;
  458 + regulator-max-microvolt = <1975000>;
  459 + regulator-boot-on;
  460 + regulator-always-on;
  461 + };
  462 +
  463 + sw3b_reg: sw3b {
  464 + regulator-min-microvolt = <400000>;
  465 + regulator-max-microvolt = <1975000>;
  466 + regulator-boot-on;
  467 + regulator-always-on;
  468 + };
  469 +
  470 + sw4_reg: sw4 {
  471 + regulator-min-microvolt = <800000>;
  472 + regulator-max-microvolt = <3300000>;
  473 + };
  474 +
  475 + swbst_reg: swbst {
  476 + regulator-min-microvolt = <5000000>;
  477 + regulator-max-microvolt = <5150000>;
  478 + };
  479 +
  480 + snvs_reg: vsnvs {
  481 + regulator-min-microvolt = <1000000>;
  482 + regulator-max-microvolt = <3000000>;
  483 + regulator-boot-on;
  484 + regulator-always-on;
  485 + };
  486 +
  487 + vref_reg: vrefddr {
  488 + regulator-boot-on;
  489 + regulator-always-on;
  490 + };
  491 +
  492 + vgen1_reg: vgen1 {
  493 + regulator-min-microvolt = <800000>;
  494 + regulator-max-microvolt = <1550000>;
  495 + };
  496 +
  497 + vgen2_reg: vgen2 {
  498 + regulator-min-microvolt = <800000>;
  499 + regulator-max-microvolt = <1550000>;
  500 + };
  501 +
  502 + vgen3_reg: vgen3 {
  503 + regulator-min-microvolt = <1800000>;
  504 + regulator-max-microvolt = <3300000>;
  505 + };
  506 +
  507 + vgen4_reg: vgen4 {
  508 + regulator-min-microvolt = <1800000>;
  509 + regulator-max-microvolt = <3300000>;
  510 + regulator-always-on;
  511 + };
  512 +
  513 + vgen5_reg: vgen5 {
  514 + regulator-min-microvolt = <1800000>;
  515 + regulator-max-microvolt = <3300000>;
  516 + regulator-always-on;
  517 + };
  518 +
  519 + vgen6_reg: vgen6 {
  520 + regulator-min-microvolt = <1800000>;
  521 + regulator-max-microvolt = <3300000>;
  522 + regulator-always-on;
  523 + };
  524 + };
  525 + };
  526 +
  527 + hdmi: edid@50 {
  528 + compatible = "fsl,imx6-hdmi-i2c";
  529 + reg = <0x50>;
  530 + };
  531 +
  532 + codec: cs42888@48 {
  533 + compatible = "cirrus,cs42888";
  534 + reg = <0x48>;
  535 + clocks = <&codec_osc>;
  536 + clock-names = "mclk";
  537 + VA-supply = <&reg_audio>;
  538 + VD-supply = <&reg_audio>;
  539 + VLS-supply = <&reg_audio>;
  540 + VLC-supply = <&reg_audio>;
  541 + };
  542 +
  543 + si4763: si4763@63 {
  544 + compatible = "si4761";
  545 + reg = <0x63>;
  546 + va-supply = <&reg_si4763_va>;
  547 + vd-supply = <&reg_si4763_vd>;
  548 + vio1-supply = <&reg_si4763_vio1>;
  549 + vio2-supply = <&reg_si4763_vio2>;
  550 + revision-a10; /* set to default A10 compatible command set */
  551 +
  552 + si476x_codec: si476x-codec {
  553 + compatible = "si476x-codec";
  554 + };
  555 + };
  556 +};
  557 +
  558 +&i2c3 {
  559 + pinctrl-names = "default";
  560 + pinctrl-0 = <&pinctrl_i2c3>;
  561 + status = "okay";
  562 +
  563 + adv7180: adv7180@21 {
  564 + compatible = "adv,adv7180";
  565 + reg = <0x21>;
  566 + pinctrl-names = "default";
  567 + pinctrl-0 = <&pinctrl_ipu1_1>;
  568 + clocks = <&clks IMX6QDL_CLK_CKO>;
  569 + clock-names = "csi_mclk";
  570 + DOVDD-supply = <&reg_3p3v>; /* 3.3v, enabled via 2.8 VGEN6 */
  571 + AVDD-supply = <&reg_3p3v>; /* 1.8v */
  572 + DVDD-supply = <&reg_3p3v>; /* 1.8v */
  573 + PVDD-supply = <&reg_3p3v>; /* 1.8v */
  574 + pwn-gpios = <&max7310_b 2 0>;
  575 + csi_id = <0>;
  576 + mclk = <24000000>;
  577 + mclk_source = <0>;
  578 + cvbs = <1>;
  579 + };
  580 +
  581 + isl29023@44 {
  582 + compatible = "fsl,isl29023";
  583 + reg = <0x44>;
  584 + rext = <499>;
  585 + interrupt-parent = <&gpio5>;
  586 + interrupts = <17 2>;
  587 + };
  588 +
  589 + max7310_a: gpio@30 {
  590 + compatible = "maxim,max7310";
  591 + reg = <0x30>;
  592 + gpio-controller;
  593 + #gpio-cells = <2>;
  594 + };
  595 +
  596 + max7310_b: gpio@32 {
  597 + compatible = "maxim,max7310";
  598 + reg = <0x32>;
  599 + gpio-controller;
  600 + #gpio-cells = <2>;
  601 + };
  602 +
  603 + max7310_c: gpio@34 {
  604 + compatible = "maxim,max7310";
  605 + reg = <0x34>;
  606 + gpio-controller;
  607 + #gpio-cells = <2>;
  608 + };
  609 +
  610 + mag3110@0e {
  611 + compatible = "fsl,mag3110";
  612 + reg = <0x0e>;
  613 + position = <2>;
  614 + interrupt-parent = <&gpio2>;
  615 + interrupts = <29 1>;
  616 + };
  617 +
  618 + mma8451@1c {
  619 + compatible = "fsl,mma8451";
  620 + reg = <0x1c>;
  621 + position = <7>;
  622 + interrupt-parent = <&gpio6>;
  623 + interrupts = <31 8>;
  624 + interrupt-route = <1>;
  625 + };
  626 +};
  627 +
  628 +&iomuxc {
  629 + pinctrl-names = "default";
  630 + pinctrl-0 = <&pinctrl_hog>;
  631 +
  632 + imx6qdl-sabreauto {
  633 + pinctrl_audmux: audmux {
  634 + fsl,pins = <
  635 + MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0
  636 + MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
  637 + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
  638 + >;
  639 + };
  640 +
  641 + pinctrl_hog: hoggrp {
  642 + fsl,pins = <
  643 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1f059
  644 + MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
  645 + MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
  646 + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x80000000
  647 + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x80000000
  648 + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x80000000
  649 + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x80000000
  650 + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x80000000
  651 + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000
  652 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x17059
  653 + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x17059
  654 + >;
  655 + };
  656 +
  657 + pinctrl_ecspi1: ecspi1grp {
  658 + fsl,pins = <
  659 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
  660 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
  661 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
  662 + >;
  663 + };
  664 +
  665 + pinctrl_ecspi1_cs: ecspi1cs {
  666 + fsl,pins = <
  667 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
  668 + >;
  669 + };
  670 +
  671 + pinctrl_egalax_int: egalax_intgrp {
  672 + fsl,pins = <
  673 + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x80000000
  674 + >;
  675 + };
  676 +
  677 + pinctrl_enet: enetgrp {
  678 + fsl,pins = <
  679 + MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
  680 + MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
  681 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
  682 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
  683 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
  684 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
  685 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
  686 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
  687 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  688 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
  689 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
  690 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
  691 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
  692 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
  693 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
  694 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  695 + >;
  696 + };
  697 +
  698 + pinctrl_enet_irq: enetirqgrp {
  699 + fsl,pins = <
  700 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
  701 + >;
  702 + };
  703 +
  704 + pinctrl_esai: esaigrp {
  705 + fsl,pins = <
  706 + MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
  707 + MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
  708 + MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
  709 + MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
  710 + MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
  711 + MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
  712 + MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
  713 + MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
  714 + MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
  715 + MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
  716 + >;
  717 + };
  718 +
  719 + pinctrl_flexcan1: flexcan1grp {
  720 + fsl,pins = <
  721 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x17059
  722 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x17059
  723 + >;
  724 + };
  725 +
  726 + pinctrl_flexcan2: flexcan2grp {
  727 + fsl,pins = <
  728 + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x17059
  729 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x17059
  730 + >;
  731 + };
  732 +
  733 + pinctrl_gpio_keys: gpio_keysgrp {
  734 + fsl,pins = <
  735 + MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0
  736 + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
  737 + MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0
  738 + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0
  739 + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
  740 + >;
  741 + };
  742 +
  743 + pinctrl_gpio_leds: gpioledsgrp {
  744 + fsl,pins = <
  745 + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000
  746 + >;
  747 + };
  748 +
  749 + pinctrl_gpmi_nand: gpminandgrp {
  750 + fsl,pins = <
  751 + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
  752 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
  753 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
  754 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
  755 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
  756 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
  757 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
  758 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
  759 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
  760 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
  761 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
  762 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
  763 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
  764 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
  765 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
  766 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
  767 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
  768 + >;
  769 + };
  770 +
  771 + pinctrl_i2c2: i2c2grp {
  772 + fsl,pins = <
  773 + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
  774 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  775 + >;
  776 + };
  777 +
  778 + pinctrl_ipu1_1: ipu1grp-1 { /* parallel port 16-bit */
  779 + fsl,pins = <
  780 + MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000
  781 + MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000
  782 + MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000
  783 + MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000
  784 + MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000
  785 + MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000
  786 + MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000
  787 + MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000
  788 + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
  789 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
  790 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
  791 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
  792 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
  793 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
  794 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
  795 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
  796 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
  797 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
  798 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
  799 + >;
  800 + };
  801 +
  802 + pinctrl_i2c3: i2c3grp {
  803 + fsl,pins = <
  804 + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  805 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
  806 + >;
  807 + };
  808 +
  809 + pinctrl_mlb: mlb {
  810 + fsl,pins = <
  811 + MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x80000000
  812 + MX6QDL_PAD_GPIO_6__MLB_SIG 0x80000000
  813 + MX6QDL_PAD_GPIO_2__MLB_DATA 0x80000000
  814 + >;
  815 + };
  816 +
  817 + pinctrl_pwm3: pwm1grp {
  818 + fsl,pins = <
  819 + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
  820 + >;
  821 + };
  822 +
  823 + pinctrl_spdif: spdifgrp {
  824 + fsl,pins = <
  825 + MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
  826 + >;
  827 + };
  828 +
  829 + pinctrl_uart3_1: uart3grp-1 {
  830 + fsl,pins = <
  831 + MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
  832 + MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
  833 + MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
  834 + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
  835 + >;
  836 + };
  837 +
  838 + pinctrl_uart3dte_1: uart3dtegrp-1 {
  839 + fsl,pins = <
  840 + MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1
  841 + MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1
  842 + MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1
  843 + MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1b0b1
  844 + >;
  845 + };
  846 +
  847 + pinctrl_uart4: uart4grp {
  848 + fsl,pins = <
  849 + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
  850 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
  851 + >;
  852 + };
  853 +
  854 + pinctrl_usbotg: usbotggrp {
  855 + fsl,pins = <
  856 + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
  857 + >;
  858 + };
  859 +
  860 + pinctrl_usdhc1: usdhc1grp {
  861 + fsl,pins = <
  862 + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
  863 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
  864 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
  865 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
  866 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
  867 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
  868 + >;
  869 + };
  870 +
  871 + pinctrl_usdhc3: usdhc3grp {
  872 + fsl,pins = <
  873 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  874 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  875 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  876 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  877 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  878 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  879 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
  880 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
  881 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
  882 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
  883 + >;
  884 + };
  885 +
  886 + pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
  887 + fsl,pins = <
  888 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
  889 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
  890 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
  891 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
  892 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
  893 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
  894 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
  895 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
  896 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
  897 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
  898 + >;
  899 + };
  900 +
  901 + pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
  902 + fsl,pins = <
  903 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
  904 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
  905 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
  906 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
  907 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
  908 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
  909 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
  910 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
  911 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
  912 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
  913 + >;
  914 + };
  915 +
  916 + pinctrl_weim_cs0: weimcs0grp {
  917 + fsl,pins = <
  918 + MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
  919 + >;
  920 + };
  921 +
  922 + pinctrl_weim_nor: weimnorgrp {
  923 + fsl,pins = <
  924 + MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
  925 + MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
  926 + MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
  927 + MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
  928 + MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
  929 + MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
  930 + MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
  931 + MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
  932 + MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
  933 + MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
  934 + MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
  935 + MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
  936 + MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
  937 + MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
  938 + MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
  939 + MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
  940 + MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
  941 + MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
  942 + MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
  943 + MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
  944 + MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
  945 + MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
  946 + MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
  947 + MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
  948 + MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
  949 + MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
  950 + MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
  951 + MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
  952 + MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
  953 + MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
  954 + MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
  955 + MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
  956 + MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
  957 + MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
  958 + MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
  959 + MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
  960 + MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
  961 + MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
  962 + MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
  963 + MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
  964 + MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
  965 + MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
  966 + MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
  967 + >;
  968 + };
  969 +
  970 + pinctrl_hdmi_cec: hdmicecgrp {
  971 + fsl,pins = <
  972 + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
  973 + >;
  974 + };
  975 + };
  976 +};
  977 +
  978 +&ldb {
  979 + status = "okay";
  980 +
  981 + lvds-channel@0 {
  982 + fsl,data-mapping = "spwg";
  983 + fsl,data-width = <18>;
  984 + primary;
  985 + status = "okay";
  986 +
  987 + display-timings {
  988 + native-mode = <&timing0>;
  989 + timing0: hsd100pxn1 {
  990 + clock-frequency = <65000000>;
  991 + hactive = <1024>;
  992 + vactive = <768>;
  993 + hback-porch = <220>;
  994 + hfront-porch = <40>;
  995 + vback-porch = <21>;
  996 + vfront-porch = <7>;
  997 + hsync-len = <60>;
  998 + vsync-len = <10>;
  999 + };
  1000 + };
  1001 + };
  1002 +
  1003 + lvds-channel@1 {
  1004 + fsl,data-mapping = "spwg";
  1005 + fsl,data-width = <18>;
  1006 + status = "okay";
  1007 +
  1008 + display-timings {
  1009 + native-mode = <&timing1>;
  1010 + timing1: hsd100pxn1 {
  1011 + clock-frequency = <65000000>;
  1012 + hactive = <1024>;
  1013 + vactive = <768>;
  1014 + hback-porch = <220>;
  1015 + hfront-porch = <40>;
  1016 + vback-porch = <21>;
  1017 + vfront-porch = <7>;
  1018 + hsync-len = <60>;
  1019 + vsync-len = <10>;
  1020 + };
  1021 + };
  1022 + };
  1023 +};
  1024 +
  1025 +&mlb {
  1026 + pinctrl-names = "default";
  1027 + pinctrl-0 = <&pinctrl_mlb>;
  1028 + status = "okay";
  1029 +};
  1030 +
  1031 +&pwm3 {
  1032 + pinctrl-names = "default";
  1033 + pinctrl-0 = <&pinctrl_pwm3>;
  1034 + status = "okay";
  1035 +};
  1036 +
  1037 +&pcie {
  1038 + status = "okay";
  1039 +};
  1040 +
  1041 +&spdif {
  1042 + pinctrl-names = "default";
  1043 + pinctrl-0 = <&pinctrl_spdif>;
  1044 + assigned-clocks = <&clks IMX6QDL_CLK_SPDIF_SEL>,
  1045 + <&clks IMX6QDL_CLK_SPDIF_PODF>;
  1046 + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_PFD3_454M>;
  1047 + assigned-clock-rates = <0>, <227368421>;
  1048 + status = "okay";
  1049 +};
  1050 +
  1051 +&snvs_poweroff {
  1052 + status = "okay";
  1053 +};
  1054 +
  1055 +&ssi2 {
  1056 + assigned-clocks = <&clks IMX6QDL_CLK_SSI2_SEL>;
  1057 + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
  1058 + assigned-clock-rates = <0>;
  1059 + fsl,mode = "i2s-master";
  1060 + status = "okay";
  1061 +};
  1062 +
  1063 +&uart3 {
  1064 + pinctrl-names = "default";
  1065 + pinctrl-0 = <&pinctrl_uart3_1>;
  1066 + pinctrl-assert-gpios = <&max7310_b 4 GPIO_ACTIVE_HIGH>, /* CTS */
  1067 + <&max7310_c 3 GPIO_ACTIVE_HIGH>; /* RXD and TXD */
  1068 + fsl,uart-has-rtscts;
  1069 + status = "okay";
  1070 + /* for DTE mode, add below change */
  1071 + /* fsl,dte-mode; */
  1072 + /* pinctrl-0 = <&pinctrl_uart3dte_1>; */
  1073 +};
  1074 +
  1075 +&uart4 {
  1076 + pinctrl-names = "default";
  1077 + pinctrl-0 = <&pinctrl_uart4>;
  1078 + status = "okay";
  1079 +};
  1080 +
  1081 +&usbh1 {
  1082 + vbus-supply = <&reg_usb_h1_vbus>;
  1083 + status = "okay";
  1084 +};
  1085 +
  1086 +&usbotg {
  1087 + vbus-supply = <&reg_usb_otg_vbus>;
  1088 + pinctrl-names = "default";
  1089 + pinctrl-0 = <&pinctrl_usbotg>;
  1090 + srp-disable;
  1091 + hnp-disable;
  1092 + adp-disable;
  1093 + status = "okay";
  1094 +};
  1095 +
  1096 +&usdhc1 {
  1097 + pinctrl-names = "default";
  1098 + pinctrl-0 = <&pinctrl_usdhc1>;
  1099 + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
  1100 + no-1-8-v;
  1101 + keep-power-in-suspend;
  1102 + enable-sdio-wakeup;
  1103 + status = "okay";
  1104 +};
  1105 +
  1106 +&usdhc3 {
  1107 + pinctrl-names = "default", "state_100mhz", "state_200mhz";
  1108 + pinctrl-0 = <&pinctrl_usdhc3>;
  1109 + pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  1110 + pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  1111 + cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
  1112 + wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
  1113 + /*
  1114 + * Due to board issue, we can not use external regulator for card slot
  1115 + * by default since the card power is shared with card detect pullup.
  1116 + * Disabling the vmmc regulator will cause unexpected card detect
  1117 + * interrupts.
  1118 + * HW rework is needed to fix this isssue. Remove R695 first, then you
  1119 + * can open below line to enable the using of external regulator.
  1120 + * Then you will be able to power off the card during suspend. This is
  1121 + * especially needed for a SD3.0 card re-enumeration working on UHS mode
  1122 + * Note: reg_sd3_vmmc is also need to be enabled
  1123 + */
  1124 + /* vmmc-supply = <&reg_sd3_vmmc>; */
  1125 + keep-power-in-suspend;
  1126 + enable-sdio-wakeup;
  1127 + status = "okay";
  1128 +};
  1129 +
  1130 +&weim {
  1131 + pinctrl-names = "default";
  1132 + pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
  1133 + #address-cells = <2>;
  1134 + #size-cells = <1>;
  1135 + ranges = <0 0 0x08000000 0x08000000>;
  1136 + status = "disabled"; /* pin conflict with SPI NOR */
  1137 +
  1138 + nor@0,0 {
  1139 + compatible = "cfi-flash";
  1140 + reg = <0 0 0x02000000>;
  1141 + #address-cells = <1>;
  1142 + #size-cells = <1>;
  1143 + bank-width = <2>;
  1144 + fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
  1145 + 0x0000c000 0x1404a38e 0x00000000>;
  1146 + };
  1147 +};
board/freescale/mx6qsabreauto/Kconfig
Diff comments   View file @ d5f904f
... ... @@ -9,5 +9,10 @@
9 9 config SYS_CONFIG_NAME
10 10 default "mx6qsabreauto"
11 11  
  12 +config NOR
  13 + bool "Support for NOR flash"
  14 + help
  15 + The i.MX SoC supports having a NOR flash connected to the WEIM.
  16 + Need to set this for NOR_BOOT.
12 17 endif
board/freescale/mx6qsabreauto/mx6qsabreauto.c
Diff comments   View file @ d5f904f
... ... @@ -109,6 +109,7 @@
109 109 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
110 110 };
111 111  
  112 +#ifdef CONFIG_SYS_I2C
112 113 /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
113 114 static struct i2c_pads_info i2c_pad_info1 = {
114 115 .scl = {
... ... @@ -122,6 +123,7 @@
122 123 .gp = IMX_GPIO_NR(4, 13)
123 124 }
124 125 };
  126 +#endif
125 127  
126 128 #ifndef CONFIG_SYS_FLASH_CFI
127 129 /*
... ... @@ -150,6 +152,8 @@
150 152 MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
151 153 };
152 154  
  155 +#ifdef CONFIG_PCA953X
  156 +
153 157 /*Define for building port exp gpio, pin starts from 0*/
154 158 #define PORTEXP_IO_NR(chip, pin) \
155 159 ((chip << 5) + pin)
... ... @@ -187,6 +191,7 @@
187 191  
188 192 return 0;
189 193 }
  194 +#endif
190 195  
191 196 #ifdef CONFIG_MTD_NOR_FLASH
192 197 static iomux_v3_cfg_t const eimnor_pads[] = {
193 198  
... ... @@ -388,12 +393,14 @@
388 393 case 0:
389 394 imx_iomux_v3_setup_multiple_pads(
390 395 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
  396 + gpio_request(USDHC1_CD_GPIO, "usdhc1 cd");
391 397 gpio_direction_input(USDHC1_CD_GPIO);
392 398 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
393 399 break;
394 400 case 1:
395 401 imx_iomux_v3_setup_multiple_pads(
396 402 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  403 + gpio_request(USDHC3_CD_GPIO, "usdhc3 cd");
397 404 gpio_direction_input(USDHC3_CD_GPIO);
398 405 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
399 406 break;
... ... @@ -607,6 +614,7 @@
607 614  
608 615 static void setup_iomux_backlight(void)
609 616 {
  617 + gpio_request(IMX_GPIO_NR(2, 9), "backlight");
610 618 gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
611 619 imx_iomux_v3_setup_multiple_pads(backlight_pads,
612 620 ARRAY_SIZE(backlight_pads));
... ... @@ -690,6 +698,8 @@
690 698 {
691 699 imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
692 700 ARRAY_SIZE(ecspi1_pads));
  701 +
  702 + gpio_request(IMX_GPIO_NR(3, 19), "escpi cs");
693 703 gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
694 704 gpio_direction_output(IMX_GPIO_NR(3, 19), 0);
695 705 }
... ... @@ -700,6 +710,108 @@
700 710 }
701 711 #endif
702 712  
  713 +#ifdef CONFIG_USB_EHCI_MX6
  714 +
  715 +iomux_v3_cfg_t const usb_otg_pads[] = {
  716 + MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
  717 +};
  718 +
  719 +static void setup_usb(void)
  720 +{
  721 + imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
  722 + ARRAY_SIZE(usb_otg_pads));
  723 +
  724 + /*
  725 + * Set daisy chain for otg_pin_id on 6q.
  726 + * For 6dl, this bit is reserved.
  727 + */
  728 + imx_iomux_set_gpr_register(1, 13, 1, 0);
  729 +
  730 +#ifdef CONFIG_DM_PCA953X
  731 + struct gpio_desc desc;
  732 + int ret;
  733 +
  734 + ret = dm_gpio_lookup_name("gpio@32_7", &desc);
  735 + if (ret)
  736 + return;
  737 +
  738 + ret = dm_gpio_request(&desc, "usb_host1_pwr");
  739 + if (ret)
  740 + return;
  741 +
  742 + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
  743 +
  744 + ret = dm_gpio_lookup_name("gpio@34_1", &desc);
  745 + if (ret)
  746 + return;
  747 +
  748 + ret = dm_gpio_request(&desc, "usb_otg_pwr");
  749 + if (ret)
  750 + return;
  751 +
  752 + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
  753 +#endif
  754 +
  755 +}
  756 +
  757 +int board_ehci_power(int port, int on)
  758 +{
  759 +#ifdef CONFIG_PCA953X
  760 +
  761 +#define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7)
  762 +#define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1)
  763 +
  764 + switch (port) {
  765 + case 0:
  766 + if (on)
  767 + port_exp_direction_output(USB_OTG_PWR, 1);
  768 + else
  769 + port_exp_direction_output(USB_OTG_PWR, 0);
  770 + break;
  771 + case 1:
  772 + if (on)
  773 + port_exp_direction_output(USB_HOST1_PWR, 1);
  774 + else
  775 + port_exp_direction_output(USB_HOST1_PWR, 0);
  776 + break;
  777 + default:
  778 + printf("MXC USB port %d not yet supported\n", port);
  779 + return -EINVAL;
  780 + }
  781 +#elif defined(CONFIG_DM_PCA953X)
  782 + struct gpio_desc desc;
  783 + int ret;
  784 +
  785 + switch (port) {
  786 + case 0:
  787 + ret = dm_gpio_lookup_name("gpio@34_1", &desc);
  788 + if (ret)
  789 + return ret;
  790 +
  791 + if (on)
  792 + dm_gpio_set_value(&desc, 1);
  793 + else
  794 + dm_gpio_set_value(&desc, 0);
  795 + break;
  796 + case 1:
  797 + ret = dm_gpio_lookup_name("gpio@32_7", &desc);
  798 + if (ret)
  799 + return ret;
  800 +
  801 + if (on)
  802 + dm_gpio_set_value(&desc, 1);
  803 + else
  804 + dm_gpio_set_value(&desc, 0);
  805 + break;
  806 + default:
  807 + printf("MXC USB port %d not yet supported\n", port);
  808 + return -EINVAL;
  809 + }
  810 +#endif
  811 + return 0;
  812 +}
  813 +#endif
  814 +
703 815 int board_early_init_f(void)
704 816 {
705 817 setup_iomux_uart();
706 818  
707 819  
708 820  
709 821  
... ... @@ -716,14 +828,21 @@
716 828 /* address of boot parameters */
717 829 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
718 830  
  831 +#ifdef CONFIG_SYS_I2C
719 832 /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
720 833 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  834 +#endif
  835 +
721 836 /* I2C 3 Steer */
  837 + gpio_request(IMX_GPIO_NR(5, 4), "steer logic");
722 838 gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
723 839 imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
  840 +
724 841 #ifndef CONFIG_SYS_FLASH_CFI
725 842 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
726 843 #endif
  844 +
  845 + gpio_request(IMX_GPIO_NR(1, 15), "expander en");
727 846 gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
728 847 imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
729 848  
730 849  
... ... @@ -751,9 +870,14 @@
751 870 setup_fec();
752 871 #endif
753 872  
  873 +#ifdef CONFIG_USB_EHCI_MX6
  874 + setup_usb();
  875 +#endif
  876 +
754 877 return 0;
755 878 }
756 879  
  880 +#ifdef CONFIG_POWER
757 881 int power_init_board(void)
758 882 {
759 883 struct pmic *pfuze;
760 884  
761 885  
... ... @@ -824,8 +948,80 @@
824 948  
825 949 return 0;
826 950 }
  951 +#elif defined(CONFIG_DM_PMIC_PFUZE100)
  952 +int power_init_board(void)
  953 +{
  954 + struct udevice *dev;
  955 + unsigned int reg;
  956 + int ret;
827 957  
  958 + dev = pfuze_common_init();
  959 + if (!dev)
  960 + return -ENODEV;
  961 +
  962 + if (is_mx6dqp())
  963 + ret = pfuze_mode_init(dev, APS_APS);
  964 + else
  965 + ret = pfuze_mode_init(dev, APS_PFM);
  966 + if (ret < 0)
  967 + return ret;
  968 +
  969 + if (is_mx6dqp()) {
  970 + /* set SW1C staby volatage 1.075V*/
  971 + reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
  972 + reg &= ~0x3f;
  973 + reg |= 0x1f;
  974 + pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
  975 +
  976 + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
  977 + reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
  978 + reg &= ~0xc0;
  979 + reg |= 0x40;
  980 + pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
  981 +
  982 + /* set SW2/VDDARM staby volatage 0.975V*/
  983 + reg = pmic_reg_read(dev, PFUZE100_SW2STBY);
  984 + reg &= ~0x3f;
  985 + reg |= 0x17;
  986 + pmic_reg_write(dev, PFUZE100_SW2STBY, reg);
  987 +
  988 + /* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */
  989 + reg = pmic_reg_read(dev, PFUZE100_SW2CONF);
  990 + reg &= ~0xc0;
  991 + reg |= 0x40;
  992 + pmic_reg_write(dev, PFUZE100_SW2CONF, reg);
  993 + } else {
  994 + /* set SW1AB staby volatage 0.975V*/
  995 + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
  996 + reg &= ~0x3f;
  997 + reg |= 0x1b;
  998 + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
  999 +
  1000 + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
  1001 + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
  1002 + reg &= ~0xc0;
  1003 + reg |= 0x40;
  1004 + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
  1005 +
  1006 + /* set SW1C staby volatage 0.975V*/
  1007 + reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
  1008 + reg &= ~0x3f;
  1009 + reg |= 0x1b;
  1010 + pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
  1011 +
  1012 + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
  1013 + reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
  1014 + reg &= ~0xc0;
  1015 + reg |= 0x40;
  1016 + pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
  1017 + }
  1018 +
  1019 + return 0;
  1020 +}
  1021 +#endif
  1022 +
828 1023 #ifdef CONFIG_LDO_BYPASS_CHECK
  1024 +#ifdef CONFIG_POWER
829 1025 void ldo_mode_set(int ldo_bypass)
830 1026 {
831 1027 unsigned int value;
832 1028  
... ... @@ -861,7 +1057,36 @@
861 1057 pmic_reg_write(p, PFUZE100_SW1CVOL, value);
862 1058 }
863 1059 }
  1060 +#elif defined(CONFIG_DM_PMIC_PFUZE100)
  1061 +void ldo_mode_set(int ldo_bypass)
  1062 +{
  1063 + struct udevice *dev;
  1064 + int ret;
  1065 +
  1066 + ret = pmic_get("pfuze100", &dev);
  1067 + if (ret == -ENODEV) {
  1068 + printf("No PMIC found!\n");
  1069 + return;
  1070 + }
  1071 +
  1072 + /* increase VDDARM/VDDSOC to support 1.2G chip */
  1073 + if (check_1_2G()) {
  1074 + ldo_bypass = 0; /* ldo_enable on 1.2G chip */
  1075 + printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n");
  1076 +
  1077 + if (is_mx6dqp()) {
  1078 + /* increase VDDARM to 1.425V */
  1079 + pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x29);
  1080 + } else {
  1081 + /* increase VDDARM to 1.425V */
  1082 + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x2d);
  1083 + }
  1084 + /* increase VDDSOC to 1.425V */
  1085 + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x2d);
  1086 + }
  1087 +}
864 1088 #endif
  1089 +#endif
865 1090  
866 1091 #ifdef CONFIG_CMD_BMODE
867 1092 static const struct boot_mode board_boot_modes[] = {
... ... @@ -914,58 +1139,4 @@
914 1139  
915 1140 return 0;
916 1141 }
917   -
918   -#ifdef CONFIG_USB_EHCI_MX6
919   -#define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7)
920   -#define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1)
921   -
922   -iomux_v3_cfg_t const usb_otg_pads[] = {
923   - MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
924   -};
925   -
926   -int board_ehci_hcd_init(int port)
927   -{
928   - switch (port) {
929   - case 0:
930   - imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
931   - ARRAY_SIZE(usb_otg_pads));
932   -
933   - /*
934   - * Set daisy chain for otg_pin_id on 6q.
935   - * For 6dl, this bit is reserved.
936   - */
937   - imx_iomux_set_gpr_register(1, 13, 1, 0);
938   - break;
939   - case 1:
940   - break;
941   - default:
942   - printf("MXC USB port %d not yet supported\n", port);
943   - return -EINVAL;
944   - }
945   - return 0;
946   -}
947   -
948   -int board_ehci_power(int port, int on)
949   -{
950   - switch (port) {
951   - case 0:
952   - if (on)
953   - port_exp_direction_output(USB_OTG_PWR, 1);
954   - else
955   - port_exp_direction_output(USB_OTG_PWR, 0);
956   - break;
957   - case 1:
958   - if (on)
959   - port_exp_direction_output(USB_HOST1_PWR, 1);
960   - else
961   - port_exp_direction_output(USB_HOST1_PWR, 0);
962   - break;
963   - default:
964   - printf("MXC USB port %d not yet supported\n", port);
965   - return -EINVAL;
966   - }
967   -
968   - return 0;
969   -}
970   -#endif
configs/mx6qsabreauto_defconfig
Diff comments   View file @ d5f904f
... ... @@ -37,5 +37,24 @@
37 37 CONFIG_G_DNL_VENDOR_NUM=0x0525
38 38 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
39 39 # CONFIG_VIDEO_SW_CURSOR is not set
40   -CONFIG_OF_LIBFDT=y
  40 +# CONFIG_OF_LIBFDT=y
  41 +
  42 +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto"
  43 +CONFIG_OF_CONTROL=y
  44 +# CONFIG_BLK is not set
  45 +CONFIG_DM_GPIO=y
  46 +CONFIG_DM_PCA953X=y
  47 +CONFIG_DM_I2C=y
  48 +CONFIG_DM_MMC=y
  49 +# CONFIG_DM_MMC_OPS is not set
  50 +CONFIG_PINCTRL=y
  51 +CONFIG_PINCTRL_IMX6=y
  52 +CONFIG_DM_PMIC=y
  53 +CONFIG_DM_PMIC_PFUZE100=y
  54 +CONFIG_DM_REGULATOR=y
  55 +CONFIG_DM_REGULATOR_PFUZE100=y
  56 +CONFIG_DM_REGULATOR_FIXED=y
  57 +CONFIG_DM_REGULATOR_GPIO=y
  58 +CONFIG_DM_ETH=y
  59 +CONFIG_DM_USB=y
configs/mx6qsabreauto_eimnor_defconfig
Diff comments   View file @ d5f904f
... ... @@ -3,6 +3,7 @@
3 3 CONFIG_TARGET_MX6QSABREAUTO=y
4 4 CONFIG_VIDEO=y
5 5 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q"
  6 +CONFIG_NOR=y
6 7 CONFIG_NOR_BOOT=y
7 8 CONFIG_BOOTDELAY=3
8 9 # CONFIG_CONSOLE_MUX is not set
... ... @@ -11,7 +12,6 @@
11 12 CONFIG_HUSH_PARSER=y
12 13 CONFIG_CMD_BOOTZ=y
13 14 # CONFIG_CMD_IMLS is not set
14   -# CONFIG_CMD_FLASH is not set
15 15 CONFIG_CMD_MEMTEST=y
16 16 CONFIG_CMD_MMC=y
17 17 CONFIG_CMD_I2C=y
... ... @@ -26,5 +26,23 @@
26 26 CONFIG_CMD_FAT=y
27 27 CONFIG_CMD_FS_GENERIC=y
28 28 # CONFIG_VIDEO_SW_CURSOR is not set
29   -CONFIG_OF_LIBFDT=y
  29 +# CONFIG_OF_LIBFDT=y
  30 +
  31 +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto-gpmi-weim"
  32 +CONFIG_OF_CONTROL=y
  33 +# CONFIG_BLK is not set
  34 +CONFIG_DM_GPIO=y
  35 +CONFIG_DM_PCA953X=y
  36 +CONFIG_DM_I2C=y
  37 +CONFIG_DM_MMC=y
  38 +# CONFIG_DM_MMC_OPS is not set
  39 +CONFIG_PINCTRL=y
  40 +CONFIG_PINCTRL_IMX6=y
  41 +CONFIG_DM_PMIC=y
  42 +CONFIG_DM_PMIC_PFUZE100=y
  43 +CONFIG_DM_REGULATOR=y
  44 +CONFIG_DM_REGULATOR_PFUZE100=y
  45 +CONFIG_DM_REGULATOR_FIXED=y
  46 +CONFIG_DM_REGULATOR_GPIO=y
  47 +CONFIG_DM_ETH=y
configs/mx6qsabreauto_nand_defconfig
Diff comments   View file @ d5f904f
... ... @@ -15,9 +15,6 @@
15 15 CONFIG_CMD_MEMTEST=y
16 16 CONFIG_CMD_MMC=y
17 17 CONFIG_CMD_I2C=y
18   -CONFIG_CMD_USB=y
19   -CONFIG_CMD_DFU=y
20   -CONFIG_CMD_USB_MASS_STORAGE=y
21 18 CONFIG_CMD_GPIO=y
22 19 CONFIG_CMD_DHCP=y
23 20 CONFIG_CMD_MII=y
24 21  
... ... @@ -28,15 +25,23 @@
28 25 CONFIG_CMD_EXT4_WRITE=y
29 26 CONFIG_CMD_FAT=y
30 27 CONFIG_CMD_FS_GENERIC=y
31   -CONFIG_DFU_MMC=y
32   -CONFIG_USB=y
33   -CONFIG_USB_STORAGE=y
34   -CONFIG_USB_GADGET=y
35   -CONFIG_CI_UDC=y
36   -CONFIG_USB_GADGET_DOWNLOAD=y
37   -CONFIG_G_DNL_MANUFACTURER="FSL"
38   -CONFIG_G_DNL_VENDOR_NUM=0x0525
39   -CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
40 28 # CONFIG_VIDEO_SW_CURSOR is not set
41   -CONFIG_OF_LIBFDT=y
  29 +# CONFIG_OF_LIBFDT=y
  30 +
  31 +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto-gpmi-weim"
  32 +CONFIG_OF_CONTROL=y
  33 +# CONFIG_BLK is not set
  34 +CONFIG_DM_GPIO=y
  35 +CONFIG_DM_I2C=y
  36 +CONFIG_DM_MMC=y
  37 +# CONFIG_DM_MMC_OPS is not set
  38 +CONFIG_PINCTRL=y
  39 +CONFIG_PINCTRL_IMX6=y
  40 +CONFIG_DM_PMIC=y
  41 +CONFIG_DM_PMIC_PFUZE100=y
  42 +CONFIG_DM_REGULATOR=y
  43 +CONFIG_DM_REGULATOR_PFUZE100=y
  44 +CONFIG_DM_REGULATOR_FIXED=y
  45 +CONFIG_DM_REGULATOR_GPIO=y
  46 +CONFIG_DM_ETH=y
configs/mx6qsabreauto_plugin_defconfig
Diff comments   View file @ d5f904f
... ... @@ -38,5 +38,24 @@
38 38 CONFIG_G_DNL_VENDOR_NUM=0x0525
39 39 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
40 40 # CONFIG_VIDEO_SW_CURSOR is not set
41   -CONFIG_OF_LIBFDT=y
  41 +# CONFIG_OF_LIBFDT=y
  42 +
  43 +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto"
  44 +CONFIG_OF_CONTROL=y
  45 +# CONFIG_BLK is not set
  46 +CONFIG_DM_GPIO=y
  47 +CONFIG_DM_PCA953X=y
  48 +CONFIG_DM_I2C=y
  49 +CONFIG_DM_MMC=y
  50 +# CONFIG_DM_MMC_OPS is not set
  51 +CONFIG_PINCTRL=y
  52 +CONFIG_PINCTRL_IMX6=y
  53 +CONFIG_DM_PMIC=y
  54 +CONFIG_DM_PMIC_PFUZE100=y
  55 +CONFIG_DM_REGULATOR=y
  56 +CONFIG_DM_REGULATOR_PFUZE100=y
  57 +CONFIG_DM_REGULATOR_FIXED=y
  58 +CONFIG_DM_REGULATOR_GPIO=y
  59 +CONFIG_DM_ETH=y
  60 +CONFIG_DM_USB=y
configs/mx6qsabreauto_sata_defconfig
Diff comments   View file @ d5f904f
... ... @@ -38,5 +38,24 @@
38 38 CONFIG_G_DNL_VENDOR_NUM=0x0525
39 39 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
40 40 # CONFIG_VIDEO_SW_CURSOR is not set
41   -CONFIG_OF_LIBFDT=y
  41 +# CONFIG_OF_LIBFDT=y
  42 +
  43 +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto"
  44 +CONFIG_OF_CONTROL=y
  45 +# CONFIG_BLK is not set
  46 +CONFIG_DM_GPIO=y
  47 +CONFIG_DM_PCA953X=y
  48 +CONFIG_DM_I2C=y
  49 +CONFIG_DM_MMC=y
  50 +# CONFIG_DM_MMC_OPS is not set
  51 +CONFIG_PINCTRL=y
  52 +CONFIG_PINCTRL_IMX6=y
  53 +CONFIG_DM_PMIC=y
  54 +CONFIG_DM_PMIC_PFUZE100=y
  55 +CONFIG_DM_REGULATOR=y
  56 +CONFIG_DM_REGULATOR_PFUZE100=y
  57 +CONFIG_DM_REGULATOR_FIXED=y
  58 +CONFIG_DM_REGULATOR_GPIO=y
  59 +CONFIG_DM_ETH=y
  60 +CONFIG_DM_USB=y
configs/mx6qsabreauto_spinor_defconfig
Diff comments   View file @ d5f904f
... ... @@ -26,5 +26,23 @@
26 26 CONFIG_CMD_FAT=y
27 27 CONFIG_CMD_FS_GENERIC=y
28 28 # CONFIG_VIDEO_SW_CURSOR is not set
29   -CONFIG_OF_LIBFDT=y
  29 +# CONFIG_OF_LIBFDT=y
  30 +
  31 +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto-ecspi"
  32 +CONFIG_OF_CONTROL=y
  33 +# CONFIG_BLK is not set
  34 +CONFIG_DM_GPIO=y
  35 +CONFIG_DM_PCA953X=y
  36 +CONFIG_DM_I2C=y
  37 +CONFIG_DM_MMC=y
  38 +# CONFIG_DM_MMC_OPS is not set
  39 +CONFIG_PINCTRL=y
  40 +CONFIG_PINCTRL_IMX6=y
  41 +CONFIG_DM_PMIC=y
  42 +CONFIG_DM_PMIC_PFUZE100=y
  43 +CONFIG_DM_REGULATOR=y
  44 +CONFIG_DM_REGULATOR_PFUZE100=y
  45 +CONFIG_DM_REGULATOR_FIXED=y
  46 +CONFIG_DM_REGULATOR_GPIO=y
  47 +CONFIG_DM_ETH=y
include/configs/mx6qsabreauto.h
Diff comments   View file @ d5f904f
... ... @@ -19,24 +19,6 @@
19 19 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
20 20 #endif
21 21  
22   -/*Since the pin conflicts on EIM D18, disable the USB host if the NOR flash is enabled */
23   -#if !defined(CONFIG_CMD_SF) && !defined(CONFIG_MTD_NOR_FLASH)
24   -/* USB Configs */
25   -#define CONFIG_USB_EHCI
26   -#define CONFIG_USB_EHCI_MX6
27   -#define CONFIG_USB_HOST_ETHER
28   -#define CONFIG_USB_ETHER_ASIX
29   -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
30   -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
31   -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
32   -#define CONFIG_MXC_USB_FLAGS 0
33   -
34   -#define CONFIG_PCA953X
35   -#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} }
36   -#endif
37   -
38   -#define CONFIG_CMD_NAND
39   -
40 22 #include "mx6sabre_common.h"
41 23  
42 24 #undef MFG_NAND_PARTITION
... ... @@ -52,6 +34,25 @@
52 34  
53 35 #ifdef CONFIG_CMD_SF
54 36 #define CONFIG_SF_DEFAULT_CS 1
  37 +#endif
  38 +
  39 +/*Since the pin conflicts on EIM D18, disable the USB host if the NOR flash is enabled */
  40 +#ifdef CONFIG_USB
  41 +/* USB Configs */
  42 +#define CONFIG_USB_EHCI
  43 +#define CONFIG_USB_EHCI_MX6
  44 +#define CONFIG_USB_HOST_ETHER
  45 +#define CONFIG_USB_ETHER_ASIX
  46 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  47 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
  48 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
  49 +#define CONFIG_MXC_USB_FLAGS 0
  50 +
  51 +#if !defined(CONFIG_DM_PCA953X) && defined(CONFIG_SYS_I2C)
  52 +#define CONFIG_PCA953X
  53 +#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} }
  54 +#endif
  55 +
55 56 #endif
56 57  
57 58 #endif /* __MX6QSABREAUTO_CONFIG_H */