Eric Lee / smarc-uboot

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Commit d65e34d12514de2bbe3b8f519761d641c081bad0

Authored by Yoshihiro Shimoda
Committed by Ben Warren
1 parent ca9c8a1e10
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

rtl8169: fix PCI system memory address 

When PCI device use system memory, some PCI host controller should be
set physical memory address.

Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>

Showing 1 changed file with 8 additions and 5 deletions Side-by-side Diff

drivers/net/rtl8169.c
Diff comments   View file @ d65e34d
... ... @@ -110,6 +110,9 @@
110 110 #define ETH_ALEN MAC_ADDR_LEN
111 111 #define ETH_ZLEN 60
112 112  
  113 +#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, (pci_addr_t)a)
  114 +#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, (phys_addr_t)a)
  115 +
113 116 enum RTL8169_registers {
114 117 MAC0 = 0, /* Ethernet hardware address. */
115 118 MAR0 = 8, /* Multicast filter. */
... ... @@ -438,7 +441,7 @@
438 441 tpc->RxDescArray[cur_rx].status =
439 442 cpu_to_le32(OWNbit + RX_BUF_SIZE);
440 443 tpc->RxDescArray[cur_rx].buf_addr =
441   - cpu_to_le32((unsigned long)tpc->RxBufferRing[cur_rx]);
  444 + cpu_to_le32(bus_to_phys(tpc->RxBufferRing[cur_rx]));
442 445 flush_cache((unsigned long)tpc->RxBufferRing[cur_rx],
443 446 RX_BUF_SIZE);
444 447 } else {
... ... @@ -488,7 +491,7 @@
488 491 ptxb[len++] = '\0';
489 492  
490 493 tpc->TxDescArray[entry].buf_Haddr = 0;
491   - tpc->TxDescArray[entry].buf_addr = cpu_to_le32((unsigned long)ptxb);
  494 + tpc->TxDescArray[entry].buf_addr = cpu_to_le32(bus_to_phys(ptxb));
492 495 if (entry != (NUM_TX_DESC - 1)) {
493 496 tpc->TxDescArray[entry].status =
494 497 cpu_to_le32((OWNbit | FSbit | LSbit) |
495 498  
... ... @@ -593,9 +596,9 @@
593 596  
594 597 tpc->cur_rx = 0;
595 598  
596   - RTL_W32(TxDescStartAddrLow, (unsigned long)tpc->TxDescArray);
  599 + RTL_W32(TxDescStartAddrLow, bus_to_phys(tpc->TxDescArray));
597 600 RTL_W32(TxDescStartAddrHigh, (unsigned long)0);
598   - RTL_W32(RxDescStartAddrLow, (unsigned long)tpc->RxDescArray);
  601 + RTL_W32(RxDescStartAddrLow, bus_to_phys(tpc->RxDescArray));
599 602 RTL_W32(RxDescStartAddrHigh, (unsigned long)0);
600 603  
601 604 /* RTL-8169sc/8110sc or later version */
... ... @@ -646,7 +649,7 @@
646 649  
647 650 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
648 651 tpc->RxDescArray[i].buf_addr =
649   - cpu_to_le32((unsigned long)tpc->RxBufferRing[i]);
  652 + cpu_to_le32(bus_to_phys(tpc->RxBufferRing[i]));
650 653 flush_cache((unsigned long)tpc->RxBufferRing[i], RX_BUF_SIZE);
651 654 }
652 655