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Commit d6fdec211f7913c97917ba262fa257fdcb6b000e

Authored by Priyanka Jain
Committed by York Sun
1 parent db1e3df7ce
Exists in smarc_8mq_lf_v2020.04 and in 11 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

armv8:fsl-layerscape: Add support for Chassis 3.2 

NXP layerscape architecture Chassis 3.2 builds upon chassis3
architecture with changes like DDR Memory map change,
removal of IFC and support of upto 8 I2C controller.

Patch add README.lsch3_2 and the above changes under
macro CONFIG_NXP_LSCH3_2.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

Showing 5 changed files with 68 additions and 5 deletions Side-by-side Diff

arch/arm/cpu/armv8/fsl-layerscape/Kconfig
Diff comments   View file @ d6fdec2
... ... @@ -180,6 +180,9 @@
180 180 config FSL_LSCH3
181 181 bool
182 182  
  183 +config NXP_LSCH3_2
  184 + bool
  185 +
183 186 config FSL_MC_ENET
184 187 bool "Management Complex network"
185 188 depends on ARCH_LS2080A || ARCH_LS1088A
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
Diff comments   View file @ d6fdec2
... ... @@ -120,6 +120,13 @@
120 120 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
121 121 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
122 122 },
  123 +#ifdef CONFIG_SYS_FSL_DRAM_BASE3
  124 + { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
  125 + CONFIG_SYS_FSL_DRAM_SIZE3,
  126 + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
  127 + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
  128 + },
  129 +#endif
123 130 #elif defined(CONFIG_FSL_LSCH2)
124 131 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
125 132 CONFIG_SYS_FSL_CCSR_SIZE,
... ... @@ -266,6 +273,13 @@
266 273 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
267 274 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
268 275 },
  276 +#ifdef CONFIG_SYS_FSL_DRAM_BASE3
  277 + { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
  278 + CONFIG_SYS_FSL_DRAM_SIZE3,
  279 + PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  280 + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
  281 + },
  282 +#endif
269 283 #elif defined(CONFIG_FSL_LSCH2)
270 284 { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
271 285 CONFIG_SYS_FSL_BOOTROM_SIZE,
272 286  
... ... @@ -595,13 +609,13 @@
595 609 {
596 610 enum boot_src src = BOOT_SOURCE_RESERVED;
597 611 u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
598   -#if !defined(CONFIG_FSL_LSCH3_2)
  612 +#if !defined(CONFIG_NXP_LSCH3_2)
599 613 u32 val;
600 614 #endif
601 615 debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
602 616  
603 617 #if defined(CONFIG_FSL_LSCH3)
604   -#if defined(CONFIG_FSL_LSCH3_2)
  618 +#if defined(CONFIG_NXP_LSCH3_2)
605 619 switch (rcw_src) {
606 620 case RCW_SRC_SDHC1_VAL:
607 621 src = BOOT_SOURCE_SD_MMC;
arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3_2
Diff comments   View file @ d6fdec2
  1 +#
  2 +# Copyright 2018 NXP
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +#
  6 +
  7 +NXP LayerScape with Chassis Generation 3.2
  8 +
  9 +This architecture supports NXP ARMv8 SoCs with Chassis generation 3.2
  10 +for example LX2160A.
  11 +
  12 +This architecture is enhancement over Chassis Generation 3 with
  13 +few differences mentioned below
  14 +
  15 +1)DDR Layout
  16 +============
  17 +Entire DDR region splits into three regions.
  18 + - Region 1 is at address 0x8000_0000 to 0xffff_ffff.
  19 + - Region 2 is at address 0x20_8000_0000 to 0x3f_ffff_ffff,
  20 + - Region 3 is at address 0x60_0000_0000 to the top of memory,
  21 + for example 140GB, 0x63_7fff_ffff.
  22 +
  23 +All DDR memory is marked as cache-enabled.
  24 +
  25 +2)IFC is removed
  26 +
  27 +3)Number of I2C controllers increased to 8
arch/arm/include/asm/arch-fsl-layerscape/cpu.h
Diff comments   View file @ d6fdec2
1 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 2 /*
3   - * Copyright 2017 NXP
  3 + * Copyright 2017-2018 NXP
4 4 * Copyright 2014-2015, Freescale Semiconductor
5 5 */
6 6  
7 7  
8 8  
9 9  
... ... @@ -12,15 +12,19 @@
12 12 #define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
13 13 #define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
14 14 #define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
  15 +#ifndef CONFIG_NXP_LSCH3_2
15 16 #define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
16 17 #define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
17 18 #define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
  19 +#endif
18 20 #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
19 21 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
20 22 #define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
21 23 #define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
  24 +#ifndef CONFIG_NXP_LSCH3_2
22 25 #define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
23 26 #define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000
  27 +#endif
24 28 #define CONFIG_SYS_FSL_DCSR_BASE 0x700000000
25 29 #define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000
26 30 #define CONFIG_SYS_FSL_MC_BASE 0x80c000000
27 31  
... ... @@ -40,8 +44,15 @@
40 44 #define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
41 45 #define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
42 46 #define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
  47 +#ifdef CONFIG_NXP_LSCH3_2
  48 +#define CONFIG_SYS_FSL_DRAM_BASE2 0x2080000000
  49 +#define CONFIG_SYS_FSL_DRAM_SIZE2 0x1F80000000
  50 +#define CONFIG_SYS_FSL_DRAM_BASE3 0x6000000000
  51 +#define CONFIG_SYS_FSL_DRAM_SIZE3 0x2000000000
  52 +#else
43 53 #define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000
44 54 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000
  55 +#endif
45 56 #elif defined(CONFIG_FSL_LSCH2)
46 57 #define CONFIG_SYS_FSL_BOOTROM_BASE 0x0
47 58 #define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
Diff comments   View file @ d6fdec2
... ... @@ -2,7 +2,7 @@
2 2 /*
3 3 * LayerScape Internal Memory Map
4 4 *
5   - * Copyright (C) 2017 NXP Semiconductors
  5 + * Copyright 2017-2018 NXP
6 6 * Copyright 2014 Freescale Semiconductor, Inc.
7 7 */
8 8  
9 9  
... ... @@ -21,7 +21,9 @@
21 21 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
22 22 #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000)
23 23 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
  24 +#ifndef CONFIG_NXP_LSCH3_2
24 25 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
  26 +#endif
25 27 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
26 28 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
27 29 #define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000
... ... @@ -45,6 +47,12 @@
45 47 #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
46 48 #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
47 49 #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
  50 +#ifdef CONFIG_NXP_LSCH3_2
  51 +#define I2C5_BASE_ADDR (CONFIG_SYS_IMMR + 0x01040000)
  52 +#define I2C6_BASE_ADDR (CONFIG_SYS_IMMR + 0x01050000)
  53 +#define I2C7_BASE_ADDR (CONFIG_SYS_IMMR + 0x01060000)
  54 +#define I2C8_BASE_ADDR (CONFIG_SYS_IMMR + 0x01070000)
  55 +#endif
48 56 #define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01330000)
49 57 #define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0)
50 58 #define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8)
... ... @@ -83,7 +91,7 @@
83 91 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
84 92  
85 93 #ifdef CONFIG_TFABOOT
86   -#ifdef CONFIG_FSL_LSCH3_2
  94 +#ifdef CONFIG_NXP_LSCH3_2
87 95 /* RCW_SRC field in Power-On Reset Control Register 1 */
88 96 #define RCW_SRC_MASK 0x07800000
89 97 #define RCW_SRC_BIT 23