Eric Lee / smarc-uboot

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Commit d81b27a24507c578764270865606ee6a91036616

Authored by Stefano Babic
1 parent a3cbc3969d
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

MX35: add support for woodburn board 

The woodburn board is based on the MX35 SOC.
Support for both external (NOR) and internal
(SD Card) boot mode are added. It uses the
generic SPL framework to implement the internal boot
mode.

The following peripherals are supported:
- Ethernet (FEC)
- SD Card
- NAND (512 MB)
- NOR Flash

In the internal boot mode, a simple imximage header
is generated to set the address in internal RAM
where the SOC must copy the SPL code. The initial setup
is then demanded to the SPL itself.

Signed-off-by: Stefano Babic <sbabic@denx.de>

Showing 12 changed files with 896 additions and 0 deletions Side-by-side Diff

... ... @@ -584,6 +584,7 @@
584 584 trizepsiv xscale/pxa
585 585 twister omap3
586 586 vision2 i.MX51
  587 + woodburn i.MX35
587 588  
588 589 Jason Liu <r64343@freescale.com>
589 590  
arch/arm/cpu/arm1136/mx35/Makefile
Diff comments   View file @ d81b27a
... ... @@ -30,6 +30,7 @@
30 30 COBJS += generic.o
31 31 COBJS += timer.o
32 32 COBJS += iomux.o
  33 +COBJS += mx35_sdram.o
33 34  
34 35 SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
35 36 OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
arch/arm/cpu/arm1136/mx35/mx35_sdram.c
Diff comments   View file @ d81b27a
  1 +/*
  2 + * Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
  3 + *
  4 + * See file CREDITS for list of people who contributed to this
  5 + * project.
  6 + *
  7 + * This program is free software; you can redistribute it and/or
  8 + * modify it under the terms of the GNU General Public License as
  9 + * published by the Free Software Foundation; either version 2 of
  10 + * the License, or (at your option) any later version.
  11 + *
  12 + * This program is distributed in the hope that it will be useful,
  13 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * GNU General Public License for more details.
  16 + *
  17 + * You should have received a copy of the GNU General Public License
  18 + * along with this program; if not, write to the Free Software
  19 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 + * MA 02111-1307 USA
  21 + */
  22 +
  23 +#include <asm/io.h>
  24 +#include <asm/errno.h>
  25 +#include <asm/arch/imx-regs.h>
  26 +#include <linux/types.h>
  27 +#include <asm/arch/sys_proto.h>
  28 +
  29 +#define ESDCTL_DDR2_EMR2 0x04000000
  30 +#define ESDCTL_DDR2_EMR3 0x06000000
  31 +#define ESDCTL_PRECHARGE 0x00000400
  32 +#define ESDCTL_DDR2_EN_DLL 0x02000400
  33 +#define ESDCTL_DDR2_RESET_DLL 0x00000333
  34 +#define ESDCTL_DDR2_MR 0x00000233
  35 +#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
  36 +
  37 +enum {
  38 + SMODE_NORMAL = 0,
  39 + SMODE_PRECHARGE,
  40 + SMODE_AUTO_REFRESH,
  41 + SMODE_LOAD_REG,
  42 + SMODE_MANUAL_REFRESH
  43 +};
  44 +
  45 +#define set_mode(x, en, m) (x | (en << 31) | (m << 28))
  46 +
  47 +static inline void dram_wait(unsigned int count)
  48 +{
  49 + volatile unsigned int wait = count;
  50 +
  51 + while (wait--)
  52 + ;
  53 +
  54 +}
  55 +
  56 +void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config,
  57 + u32 row, u32 col, u32 dsize, u32 refresh)
  58 +{
  59 + struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
  60 + u32 *cfg_reg, *ctl_reg;
  61 + u32 val;
  62 + u32 ctlval;
  63 +
  64 + switch (start_address) {
  65 + case CSD0_BASE_ADDR:
  66 + cfg_reg = &esdc->esdcfg0;
  67 + ctl_reg = &esdc->esdctl0;
  68 + break;
  69 + case CSD1_BASE_ADDR:
  70 + cfg_reg = &esdc->esdcfg1;
  71 + ctl_reg = &esdc->esdctl1;
  72 + break;
  73 + default:
  74 + return;
  75 + }
  76 +
  77 + /* The MX35 supports 11 up to 14 rows */
  78 + if (row < 11 || row > 14 || col < 8 || col > 10)
  79 + return;
  80 + ctlval = (row - 11) << 24 | (col - 8) << 20 | (dsize << 16);
  81 +
  82 + /* Initialize MISC register for DDR2 */
  83 + val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
  84 + ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
  85 + writel(val, &esdc->esdmisc);
  86 + val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
  87 + writel(val, &esdc->esdmisc);
  88 +
  89 + /*
  90 + * according to DDR2 specs, wait a while before
  91 + * the PRECHARGE_ALL command
  92 + */
  93 + dram_wait(0x20000);
  94 +
  95 + /* Load DDR2 config and timing */
  96 + writel(ddr2_config, cfg_reg);
  97 +
  98 + /* Precharge ALL */
  99 + writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
  100 + ctl_reg);
  101 + writel(0xda, start_address + ESDCTL_PRECHARGE);
  102 +
  103 + /* Load mode */
  104 + writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
  105 + ctl_reg);
  106 + writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
  107 + writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
  108 + writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
  109 + writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
  110 +
  111 + /* Precharge ALL */
  112 + writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
  113 + ctl_reg);
  114 + writel(0xda, start_address + ESDCTL_PRECHARGE);
  115 +
  116 + /* Set mode auto refresh : at least two refresh are required */
  117 + writel(set_mode(ctlval, 1, SMODE_AUTO_REFRESH),
  118 + ctl_reg);
  119 + writel(0xda, start_address);
  120 + writel(0xda, start_address);
  121 +
  122 + writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
  123 + ctl_reg);
  124 + writeb(0xda, start_address + ESDCTL_DDR2_MR);
  125 + writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
  126 +
  127 + /* OCD mode exit */
  128 + writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
  129 +
  130 + /* Set normal mode */
  131 + writel(set_mode(ctlval, 1, SMODE_NORMAL) | refresh,
  132 + ctl_reg);
  133 +
  134 + dram_wait(0x20000);
  135 +
  136 + /* Do not set delay lines, only for MDDR */
  137 +}
arch/arm/include/asm/arch-mx35/sys_proto.h
Diff comments   View file @ d81b27a
... ... @@ -25,6 +25,8 @@
25 25 #define _SYS_PROTO_H_
26 26  
27 27 u32 get_cpu_rev(void);
  28 +void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config,
  29 + u32 row, u32 col, u32 dsize, u32 refresh);
28 30 #define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
29 31  
30 32 #endif
board/woodburn/Makefile
Diff comments   View file @ d81b27a
  1 +#
  2 +# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
  3 +#
  4 +# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
  5 +#
  6 +# This program is free software; you can redistribute it and/or
  7 +# modify it under the terms of the GNU General Public License as
  8 +# published by the Free Software Foundation; either version 2 of
  9 +# the License, or (at your option) any later version.
  10 +#
  11 +# This program is distributed in the hope that it will be useful,
  12 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14 +# GNU General Public License for more details.
  15 +#
  16 +# You should have received a copy of the GNU General Public License
  17 +# along with this program; if not, write to the Free Software
  18 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19 +# MA 02111-1307 USA
  20 +#
  21 +
  22 +include $(TOPDIR)/config.mk
  23 +
  24 +LIB = $(obj)lib$(BOARD).o
  25 +
  26 +COBJS := woodburn.o
  27 +SOBJS := lowlevel_init.o
  28 +
  29 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
  30 +OBJS := $(addprefix $(obj),$(COBJS))
  31 +SOBJS := $(addprefix $(obj),$(SOBJS))
  32 +
  33 +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
  34 + $(call cmd_link_o_target, $(OBJS) $(SOBJS))
  35 +
  36 +#########################################################################
  37 +
  38 +# defines $(obj).depend target
  39 +include $(SRCTREE)/rules.mk
  40 +
  41 +sinclude $(obj).depend
  42 +
  43 +#########################################################################
board/woodburn/imximage.cfg
Diff comments   View file @ d81b27a
  1 +BOOT_FROM sd
  2 +
  3 +# DDR2 init
  4 +DATA 4 0xB8001010 0x00000304
board/woodburn/lowlevel_init.S
Diff comments   View file @ d81b27a
  1 +/*
  2 + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
  3 + *
  4 + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
  5 + *
  6 + * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#include <config.h>
  25 +#include <asm/arch/lowlevel_macro.S>
  26 +
  27 +.globl lowlevel_init
  28 +lowlevel_init:
  29 +
  30 + core_init
  31 +
  32 + init_aips
  33 +
  34 + init_max
  35 +
  36 + init_m3if
  37 +
  38 + mov pc, lr
board/woodburn/woodburn.c
Diff comments   View file @ d81b27a
  1 +/*
  2 + * Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
  3 + *
  4 + * Based on flea3.c and mx35pdk.c
  5 + *
  6 + * See file CREDITS for list of people who contributed to this
  7 + * project.
  8 + *
  9 + * This program is free software; you can redistribute it and/or
  10 + * modify it under the terms of the GNU General Public License as
  11 + * published by the Free Software Foundation; either version 2 of
  12 + * the License, or (at your option) any later version.
  13 + *
  14 + * This program is distributed in the hope that it will be useful,
  15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 + * GNU General Public License for more details.
  18 + *
  19 + * You should have received a copy of the GNU General Public License
  20 + * along with this program; if not, write to the Free Software
  21 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 + * MA 02111-1307 USA
  23 + */
  24 +
  25 +#include <common.h>
  26 +#include <asm/io.h>
  27 +#include <asm/errno.h>
  28 +#include <asm/arch/imx-regs.h>
  29 +#include <asm/arch/crm_regs.h>
  30 +#include <asm/arch/clock.h>
  31 +#include <asm/arch/mx35_pins.h>
  32 +#include <asm/arch/iomux.h>
  33 +#include <i2c.h>
  34 +#include <pmic.h>
  35 +#include <fsl_pmic.h>
  36 +#include <mc13892.h>
  37 +#include <mmc.h>
  38 +#include <fsl_esdhc.h>
  39 +#include <linux/types.h>
  40 +#include <asm/gpio.h>
  41 +#include <asm/arch/sys_proto.h>
  42 +#include <netdev.h>
  43 +#include <spl.h>
  44 +
  45 +#define CCM_CCMR_CONFIG 0x003F4208
  46 +
  47 +#define ESDCTL_DDR2_CONFIG 0x007FFC3F
  48 +
  49 +/* For MMC */
  50 +#define GPIO_MMC_CD 7
  51 +#define GPIO_MMC_WP 8
  52 +
  53 +DECLARE_GLOBAL_DATA_PTR;
  54 +
  55 +int dram_init(void)
  56 +{
  57 + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
  58 + PHYS_SDRAM_1_SIZE);
  59 +
  60 + return 0;
  61 +}
  62 +
  63 +static void board_setup_sdram(void)
  64 +{
  65 + struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
  66 +
  67 + /* Initialize with default values both CSD0/1 */
  68 + writel(0x2000, &esdc->esdctl0);
  69 + writel(0x2000, &esdc->esdctl1);
  70 +
  71 + mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
  72 + 13, 10, 2, 0x8080);
  73 +}
  74 +
  75 +static void setup_iomux_fec(void)
  76 +{
  77 + /* setup pins for FEC */
  78 + mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
  79 + mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
  80 + mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
  81 + mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
  82 + mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
  83 + mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
  84 + mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
  85 + mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
  86 + mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
  87 + mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
  88 + mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
  89 + mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
  90 + mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
  91 + mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
  92 + mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
  93 + mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
  94 + mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
  95 + mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
  96 +}
  97 +
  98 +int woodburn_init(void)
  99 +{
  100 + struct ccm_regs *ccm =
  101 + (struct ccm_regs *)IMX_CCM_BASE;
  102 +
  103 + /* initialize PLL and clock configuration */
  104 + writel(CCM_CCMR_CONFIG, &ccm->ccmr);
  105 +
  106 + /* Set-up RAM */
  107 + board_setup_sdram();
  108 +
  109 + /* enable clocks */
  110 + writel(readl(&ccm->cgr0) |
  111 + MXC_CCM_CGR0_EMI_MASK |
  112 + MXC_CCM_CGR0_EDIO_MASK |
  113 + MXC_CCM_CGR0_EPIT1_MASK,
  114 + &ccm->cgr0);
  115 +
  116 + writel(readl(&ccm->cgr1) |
  117 + MXC_CCM_CGR1_FEC_MASK |
  118 + MXC_CCM_CGR1_GPIO1_MASK |
  119 + MXC_CCM_CGR1_GPIO2_MASK |
  120 + MXC_CCM_CGR1_GPIO3_MASK |
  121 + MXC_CCM_CGR1_I2C1_MASK |
  122 + MXC_CCM_CGR1_I2C2_MASK |
  123 + MXC_CCM_CGR1_I2C3_MASK,
  124 + &ccm->cgr1);
  125 +
  126 + /* Set-up NAND */
  127 + __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
  128 +
  129 + /* Set pinmux for the required peripherals */
  130 + setup_iomux_fec();
  131 +
  132 + /* setup GPIO1_4 FEC_ENABLE signal */
  133 + mxc_request_iomux(MX35_PIN_SCKR, MUX_CONFIG_ALT5);
  134 + gpio_direction_output(4, 1);
  135 + mxc_request_iomux(MX35_PIN_HCKT, MUX_CONFIG_ALT5);
  136 + gpio_direction_output(9, 0);
  137 + gpio_set_value(9, 1);
  138 +
  139 + return 0;
  140 +}
  141 +
  142 +#if defined(CONFIG_SPL_BUILD)
  143 +void board_init_f(ulong dummy)
  144 +{
  145 + /* Set the stack pointer. */
  146 + asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
  147 +
  148 + /* Initialize MUX and SDRAM */
  149 + woodburn_init();
  150 +
  151 + /* Clear the BSS. */
  152 + memset(__bss_start, 0, __bss_end__ - __bss_start);
  153 +
  154 + /* Set global data pointer. */
  155 + gd = &gdata;
  156 +
  157 + preloader_console_init();
  158 + timer_init();
  159 +
  160 + board_init_r(NULL, 0);
  161 +}
  162 +
  163 +void spl_board_init(void)
  164 +{
  165 +}
  166 +
  167 +#endif
  168 +
  169 +
  170 +/* Booting from NOR in external mode */
  171 +int board_early_init_f(void)
  172 +{
  173 + return woodburn_init();
  174 +}
  175 +
  176 +
  177 +int board_init(void)
  178 +{
  179 + struct pmic *p;
  180 + u32 val;
  181 +
  182 + /* address of boot parameters */
  183 + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  184 +
  185 + pmic_init();
  186 + p = get_pmic();
  187 +
  188 + /*
  189 + * Set switchers in Auto in NORMAL mode & STANDBY mode
  190 + * Setup the switcher mode for SW1 & SW2
  191 + */
  192 + pmic_reg_read(p, REG_SW_4, &val);
  193 + val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
  194 + (SWMODE_MASK << SWMODE2_SHIFT)));
  195 + val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
  196 + (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
  197 + /* Set SWILIMB */
  198 + val |= (1 << 22);
  199 + pmic_reg_write(p, REG_SW_4, val);
  200 +
  201 + /* Setup the switcher mode for SW3 & SW4 */
  202 + pmic_reg_read(p, REG_SW_5, &val);
  203 + val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
  204 + (SWMODE_MASK << SWMODE3_SHIFT));
  205 + val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
  206 + (SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
  207 + pmic_reg_write(p, REG_SW_5, val);
  208 +
  209 + /* Set VGEN1 to 3.15V */
  210 + pmic_reg_read(p, REG_SETTING_0, &val);
  211 + val &= ~(VGEN1_MASK);
  212 + val |= VGEN1_3_15;
  213 + pmic_reg_write(p, REG_SETTING_0, val);
  214 +
  215 + pmic_reg_read(p, REG_MODE_0, &val);
  216 + val |= VGEN1EN;
  217 + pmic_reg_write(p, REG_MODE_0, val);
  218 + udelay(2000);
  219 +
  220 + return 0;
  221 +}
  222 +
  223 +#if defined(CONFIG_FSL_ESDHC)
  224 +struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
  225 +
  226 +int board_mmc_init(bd_t *bis)
  227 +{
  228 + /* configure pins for SDHC1 only */
  229 + mxc_request_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_FUNC);
  230 + mxc_request_iomux(MX35_PIN_SD1_CLK, MUX_CONFIG_FUNC);
  231 + mxc_request_iomux(MX35_PIN_SD1_DATA0, MUX_CONFIG_FUNC);
  232 + mxc_request_iomux(MX35_PIN_SD1_DATA1, MUX_CONFIG_FUNC);
  233 + mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC);
  234 + mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC);
  235 +
  236 + /* MMC Card Detect on GPIO1_7 */
  237 + mxc_request_iomux(MX35_PIN_SCKT, MUX_CONFIG_ALT5);
  238 + mxc_iomux_set_input(MUX_IN_GPIO1_IN_7, 0x1);
  239 + gpio_direction_input(GPIO_MMC_CD);
  240 +
  241 + mxc_request_iomux(MX35_PIN_FST, MUX_CONFIG_ALT5);
  242 + mxc_iomux_set_input(MUX_IN_GPIO1_IN_8, 0x1);
  243 + gpio_direction_output(GPIO_MMC_WP, 0);
  244 +
  245 + esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
  246 +
  247 + return fsl_esdhc_initialize(bis, &esdhc_cfg);
  248 +}
  249 +
  250 +int board_mmc_getcd(struct mmc *mmc)
  251 +{
  252 + return !gpio_get_value(GPIO_MMC_CD);
  253 +}
  254 +#endif
  255 +
  256 +u32 get_board_rev(void)
  257 +{
  258 + int rev = 0;
  259 +
  260 + return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
  261 +}
... ... @@ -50,6 +50,8 @@
50 50 imx31_litekit arm arm1136 - logicpd mx31
51 51 flea3 arm arm1136 - CarMediaLab mx35
52 52 mx35pdk arm arm1136 - freescale mx35
  53 +woodburn arm arm1136 - - mx35
  54 +woodburn_sd arm arm1136 woodburn - mx35 woodburn_sd:IMX_CONFIG=board/woodburn/imximage.cfg
53 55 omap2420h4 arm arm1136 - ti omap24xx
54 56 tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x
55 57 rpi_b arm arm1176 rpi_b raspberrypi bcm2835
include/configs/woodburn.h
Diff comments   View file @ d81b27a
  1 +/*
  2 + * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
  3 + *
  4 + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
  5 + *
  6 + * Configuration for the woodburn board.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#ifndef __CONFIG_H
  25 +#define __CONFIG_H
  26 +
  27 +#include <asm/arch/imx-regs.h>
  28 +#include "woodburn_common.h"
  29 +
  30 +/* Set TEXT at the beginning of the NOR flash */
  31 +#define CONFIG_SYS_TEXT_BASE 0xA0000000
  32 +#define CONFIG_BOARD_EARLY_INIT_F
  33 +
  34 +#endif /* __CONFIG_H */
include/configs/woodburn_common.h
Diff comments   View file @ d81b27a
  1 +/*
  2 + * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
  3 + *
  4 + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
  5 + *
  6 + * Configuration for the woodburn board.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#ifndef __WOODBURN_COMMON_CONFIG_H
  25 +#define __WOODBURN_COMMON_CONFIG_H
  26 +
  27 +#include <asm/arch/imx-regs.h>
  28 +
  29 + /* High Level Configuration Options */
  30 +#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
  31 +#define CONFIG_MX35
  32 +#define CONFIG_MX35_HCLK_FREQ 24000000
  33 +
  34 +#define CONFIG_SYS_DCACHE_OFF
  35 +#define CONFIG_SYS_CACHELINE_SIZE 32
  36 +
  37 +#define CONFIG_DISPLAY_CPUINFO
  38 +
  39 +/* Only in case the value is not present in mach-types.h */
  40 +#ifndef MACH_TYPE_FLEA3
  41 +#define MACH_TYPE_FLEA3 3668
  42 +#endif
  43 +
  44 +#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3
  45 +
  46 +/* This is required to setup the ESDC controller */
  47 +
  48 +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
  49 +#define CONFIG_REVISION_TAG
  50 +#define CONFIG_SETUP_MEMORY_TAGS
  51 +#define CONFIG_INITRD_TAG
  52 +
  53 +/*
  54 + * Size of malloc() pool
  55 + */
  56 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
  57 +
  58 +/*
  59 + * Hardware drivers
  60 + */
  61 +#define CONFIG_HARD_I2C
  62 +#define CONFIG_I2C_MXC
  63 +#define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR
  64 +#define CONFIG_SYS_I2C_SPEED 100000
  65 +#define CONFIG_MXC_SPI
  66 +#define CONFIG_MXC_GPIO
  67 +
  68 +/* PMIC Controller */
  69 +#define CONFIG_PMIC
  70 +#define CONFIG_PMIC_I2C
  71 +#define CONFIG_PMIC_FSL_MC13892
  72 +#define CONFIG_PMIC_FSL
  73 +#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
  74 +#define CONFIG_RTC_MC13XXX
  75 +
  76 +
  77 +/* mmc driver */
  78 +#define CONFIG_MMC
  79 +#define CONFIG_GENERIC_MMC
  80 +#define CONFIG_FSL_ESDHC
  81 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
  82 +#define CONFIG_SYS_FSL_ESDHC_NUM 1
  83 +
  84 +/*
  85 + * UART (console)
  86 + */
  87 +#define CONFIG_MXC_UART
  88 +#define CONFIG_MXC_UART_BASE UART1_BASE
  89 +
  90 +/* allow to overwrite serial and ethaddr */
  91 +#define CONFIG_ENV_OVERWRITE
  92 +#define CONFIG_CONS_INDEX 1
  93 +#define CONFIG_BAUDRATE 115200
  94 +
  95 +/*
  96 + * Command definition
  97 + */
  98 +
  99 +#include <config_cmd_default.h>
  100 +
  101 +#define CONFIG_CMD_PING
  102 +#define CONFIG_CMD_DATE
  103 +#define CONFIG_CMD_DHCP
  104 +#define CONFIG_BOOTP_SUBNETMASK
  105 +#define CONFIG_BOOTP_GATEWAY
  106 +#define CONFIG_BOOTP_DNS
  107 +
  108 +#define CONFIG_CMD_NAND
  109 +#define CONFIG_CMD_CACHE
  110 +
  111 +#define CONFIG_CMD_I2C
  112 +#define CONFIG_CMD_SPI
  113 +#define CONFIG_CMD_MII
  114 +#define CONFIG_CMD_NET
  115 +
  116 +#define CONFIG_CMD_MMC
  117 +#define CONFIG_DOS_PARTITION
  118 +#define CONFIG_EFI_PARTITION
  119 +#define CONFIG_CMD_EXT2
  120 +#define CONFIG_CMD_FAT
  121 +
  122 +#define CONFIG_CMD_GPIO
  123 +#define CONFIG_MXC_GPIO
  124 +
  125 +#define CONFIG_NET_RETRY_COUNT 100
  126 +
  127 +#define CONFIG_BOOTDELAY 3
  128 +
  129 +#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
  130 +
  131 +
  132 +/*
  133 + * Ethernet on SOC (FEC)
  134 + */
  135 +#define CONFIG_FEC_MXC
  136 +#define IMX_FEC_BASE FEC_BASE_ADDR
  137 +#define CONFIG_PHYLIB
  138 +#define CONFIG_PHY_MICREL
  139 +#define CONFIG_FEC_MXC_PHYADDR 0x1
  140 +
  141 +#define CONFIG_MII
  142 +#define CONFIG_DISCOVER_PHY
  143 +
  144 +#define CONFIG_ARP_TIMEOUT 200UL
  145 +
  146 +/*
  147 + * Miscellaneous configurable options
  148 + */
  149 +#define CONFIG_SYS_LONGHELP /* undef to save memory */
  150 +#define CONFIG_SYS_PROMPT "woodburn U-Boot > "
  151 +#define CONFIG_CMDLINE_EDITING
  152 +#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
  153 +
  154 +#define CONFIG_AUTO_COMPLETE
  155 +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  156 +/* Print Buffer Size */
  157 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  158 +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  159 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  160 +
  161 +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
  162 +#define CONFIG_SYS_MEMTEST_END 0x10000
  163 +
  164 +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
  165 +
  166 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  167 +
  168 +#define CONFIG_SYS_HZ 1000
  169 +
  170 +
  171 +/*
  172 + * Stack sizes
  173 + *
  174 + * The stack sizes are set up in start.S using the settings below
  175 + */
  176 +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
  177 +
  178 +/*
  179 + * Physical Memory Map
  180 + */
  181 +#define CONFIG_NR_DRAM_BANKS 1
  182 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR
  183 +#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
  184 +
  185 +#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR
  186 +
  187 +#define CONFIG_SYS_GBL_DATA_OFFSET (LOW_LEVEL_SRAM_STACK - \
  188 + IRAM_BASE_ADDR - \
  189 + GENERATED_GBL_DATA_SIZE)
  190 +#define CONFIG_SYS_INIT_SP_ADDR (IRAM_BASE_ADDR + \
  191 + CONFIG_SYS_GBL_DATA_OFFSET)
  192 +
  193 +/*
  194 + * MTD Command for mtdparts
  195 + */
  196 +#define CONFIG_CMD_MTDPARTS
  197 +#define CONFIG_MTD_DEVICE
  198 +#define CONFIG_FLASH_CFI_MTD
  199 +#define CONFIG_MTD_PARTITIONS
  200 +#define MTDIDS_DEFAULT "nand0=mxc_nand,nor0=physmap-flash.0"
  201 +#define MTDPARTS_DEFAULT "mtdparts=mxc_nand:50m(root1)," \
  202 + "32m(rootfb)," \
  203 + "64m(pcache)," \
  204 + "64m(app1)," \
  205 + "10m(app2),-(spool);" \
  206 + "physmap-flash.0:512k(u-boot),64k(env1)," \
  207 + "64k(env2),3776k(kernel1),3776k(kernel2)"
  208 +
  209 +/*
  210 + * FLASH and environment organization
  211 + */
  212 +#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
  213 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  214 +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
  215 +/* Monitor at beginning of flash */
  216 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  217 +#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
  218 +
  219 +#define CONFIG_ENV_SECT_SIZE (128 * 1024)
  220 +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
  221 +
  222 +/* Address and size of Redundant Environment Sector */
  223 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
  224 +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
  225 +
  226 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
  227 + CONFIG_SYS_MONITOR_LEN)
  228 +
  229 +#define CONFIG_ENV_IS_IN_FLASH
  230 +
  231 +/*
  232 + * CFI FLASH driver setup
  233 + */
  234 +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
  235 +#define CONFIG_FLASH_CFI_DRIVER
  236 +
  237 +/* A non-standard buffered write algorithm */
  238 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */
  239 +#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
  240 +
  241 +/*
  242 + * NAND FLASH driver setup
  243 + */
  244 +#define CONFIG_NAND_MXC
  245 +#define CONFIG_NAND_MXC_V1_1
  246 +#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
  247 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
  248 +#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
  249 +#define CONFIG_MXC_NAND_HWECC
  250 +#define CONFIG_SYS_NAND_LARGEPAGE
  251 +
  252 +#if 0
  253 +#define CONFIG_MTD_DEBUG
  254 +#define CONFIG_MTD_DEBUG_VERBOSE 7
  255 +#endif
  256 +#define CONFIG_SYS_NAND_ONFI_DETECTION
  257 +
  258 +/*
  259 + * Default environment and default scripts
  260 + * to update uboot and load kernel
  261 + */
  262 +#define xstr(s) str(s)
  263 +#define str(s) #s
  264 +
  265 +#define CONFIG_HOSTNAME woodburn
  266 +#define CONFIG_EXTRA_ENV_SETTINGS \
  267 + "netdev=eth0\0" \
  268 + "nfsargs=setenv bootargs root=/dev/nfs rw " \
  269 + "nfsroot=${serverip}:${rootpath}\0" \
  270 + "ramargs=setenv bootargs root=/dev/ram rw\0" \
  271 + "addip_sta=setenv bootargs ${bootargs} " \
  272 + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  273 + ":${hostname}:${netdev}:off panic=1\0" \
  274 + "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
  275 + "addip=if test -n ${ipdyn};then run addip_dyn;" \
  276 + "else run addip_sta;fi\0" \
  277 + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
  278 + "addtty=setenv bootargs ${bootargs}" \
  279 + " console=ttymxc0,${baudrate}\0" \
  280 + "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
  281 + "loadaddr=80800000\0" \
  282 + "kernel_addr_r=80800000\0" \
  283 + "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
  284 + "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
  285 + "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
  286 + "flash_self=run ramargs addip addtty addmtd addmisc;" \
  287 + "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  288 + "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
  289 + "bootm ${kernel_addr}\0" \
  290 + "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
  291 + "run nfsargs addip addtty addmtd addmisc;" \
  292 + "bootm ${kernel_addr_r}\0" \
  293 + "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
  294 + "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
  295 + "net_self=if run net_self_load;then " \
  296 + "run ramargs addip addtty addmtd addmisc;" \
  297 + "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
  298 + "else echo Images not loades;fi\0" \
  299 + "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
  300 + "load=tftp ${loadaddr} ${u-boot}\0" \
  301 + "uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
  302 + "update=protect off ${uboot_addr} +80000;" \
  303 + "erase ${uboot_addr} +80000;" \
  304 + "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
  305 + "upd=if run load;then echo Updating u-boot;if run update;" \
  306 + "then echo U-Boot updated;" \
  307 + "else echo Error updating u-boot !;" \
  308 + "echo Board without bootloader !!;" \
  309 + "fi;" \
  310 + "else echo U-Boot not downloaded..exiting;fi\0" \
  311 + "bootcmd=run net_nfs\0"
  312 +
  313 +#endif /* __CONFIG_H */
include/configs/woodburn_sd.h
Diff comments   View file @ d81b27a
  1 +/*
  2 + * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
  3 + *
  4 + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
  5 + *
  6 + * Configuration for the woodburn board.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#ifndef __CONFIG_H
  25 +#define __CONFIG_H
  26 +
  27 +#include <asm/arch/imx-regs.h>
  28 +#include "woodburn_common.h"
  29 +
  30 +/* Set TEXT in RAM */
  31 +#define CONFIG_SYS_TEXT_BASE 0x82000000
  32 +
  33 +#define CONFIG_BOOT_INTERNAL
  34 +
  35 +/*
  36 + * SPL
  37 + */
  38 +#define CONFIG_SPL
  39 +#define CONFIG_SPL_FRAMEWORK
  40 +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm1136/u-boot-spl.lds"
  41 +#define CONFIG_SPL_LIBCOMMON_SUPPORT
  42 +#define CONFIG_SPL_LIBGENERIC_SUPPORT
  43 +#define CONFIG_SPL_LIBDISK_SUPPORT
  44 +#define CONFIG_SPL_SERIAL_SUPPORT
  45 +#define CONFIG_SPL_MMC_SUPPORT
  46 +#define CONFIG_SPL_BOARD_INIT
  47 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x100 /* address 0x60000 */
  48 +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 /* 512 KB */
  49 +#define CONFIG_SPL_GPIO_SUPPORT
  50 +
  51 +#define CONFIG_SPL_TEXT_BASE 0x10002300
  52 +#define CONFIG_SPL_MAX_SIZE (64 * 1024) /* 8 KB for stack */
  53 +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
  54 +
  55 +#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
  56 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
  57 +#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
  58 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  59 +
  60 +#endif /* __CONFIG_H */