arm: socfpga: Add A10 macros

Add i2c, timer and other A10 macros. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

arm: socfpga: Add A10 macros
Add i2c, timer and other A10 macros. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Ley Foon Tan · Marek Vasut
1 parent d1c559af5f
Showing 1 changed file with 7 additions and 1 deletions Side-by-side Diff
arch/arm/mach-socfpga/include/mach/base_addr_a10.h
 /*
- * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ * Copyright (C) 2014-2017 Altera Corporation <www.altera.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
  
  
  
@@ -29,18 +29,24 @@
 #define SOCFPGA_MPUL2_ADDRESS			0xfffff000
 #define SOCFPGA_I2C0_ADDRESS			0xffc02200
 #define SOCFPGA_I2C1_ADDRESS			0xffc02300
+#define SOCFPGA_I2C2_ADDRESS			0xffc02400
+#define SOCFPGA_I2C3_ADDRESS			0xffc02500
+#define SOCFPGA_I2C4_ADDRESS			0xffc02600
  
 #define SOCFPGA_ECC_OCRAM_ADDRESS		0xff8c3000
 #define SOCFPGA_UART0_ADDRESS			0xffc02000
 #define SOCFPGA_OSC1TIMER0_ADDRESS		0xffd00000
+#define SOCFPGA_OSC1TIMER1_ADDRESS		0xffd00100
 #define SOCFPGA_CLKMGR_ADDRESS			0xffd04000
 #define SOCFPGA_RSTMGR_ADDRESS			0xffd05000
  
 #define SOCFPGA_SDR_ADDRESS			0xffcfb000
+#define SOCFPGA_NOC_L4_PRIV_FLT_OFST		0xffd11000
 #define SOCFPGA_SDR_SCHEDULER_ADDRESS		0xffd12400
 #define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS	0xffd13200
 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS	0xffd13300
 #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS		0xffd13400
+#define SOCFPGA_NOC_FW_H2F_SCR_OFST		0xffd13500
  
 #endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */
1	1	/*
2		- * Copyright (C) 2014 Altera Corporation <www.altera.com>
	2	+ * Copyright (C) 2014-2017 Altera Corporation <www.altera.com>
3	3	*
4	4	* SPDX-License-Identifier: GPL-2.0+
5	5	*/
6	6
7	7
8	8
...	...	@@ -29,18 +29,24 @@
29	29	#define SOCFPGA_MPUL2_ADDRESS 0xfffff000
30	30	#define SOCFPGA_I2C0_ADDRESS 0xffc02200
31	31	#define SOCFPGA_I2C1_ADDRESS 0xffc02300
	32	+#define SOCFPGA_I2C2_ADDRESS 0xffc02400
	33	+#define SOCFPGA_I2C3_ADDRESS 0xffc02500
	34	+#define SOCFPGA_I2C4_ADDRESS 0xffc02600
32	35
33	36	#define SOCFPGA_ECC_OCRAM_ADDRESS 0xff8c3000
34	37	#define SOCFPGA_UART0_ADDRESS 0xffc02000
35	38	#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
	39	+#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd00100
36	40	#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
37	41	#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
38	42
39	43	#define SOCFPGA_SDR_ADDRESS 0xffcfb000
	44	+#define SOCFPGA_NOC_L4_PRIV_FLT_OFST 0xffd11000
40	45	#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xffd12400
41	46	#define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200
42	47	#define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS 0xffd13300
43	48	#define SOCFPGA_SDR_FIREWALL_L3_ADDRESS 0xffd13400
	49	+#define SOCFPGA_NOC_FW_H2F_SCR_OFST 0xffd13500
44	50
45	51	#endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */