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Commit d84c55815394bd7e3f6408724ab73bd65d70efbb

Authored by wdenk 2002-01-27 08:56:55 +0800

1 parent a1e329b41b

Exists in master and in 55 other branches

Initial revision

Showing 6 changed files with 725 additions and 0 deletions Side-by-side Diff

board/RPXClassic/Makefile
board/evb64260/intel_flash.h
board/evb64260/zuma_pbb.h
include/jffs2/jffs2_1pass.h
include/mpc74xx.h
tools/gdb/Makefile

board/RPXClassic/Makefile

Diff comments View file @ d84c558

	1	+#
	2	+# (C) Copyright 2000
	3	+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+#
	5	+# See file CREDITS for list of people who contributed to this
	6	+# project.
	7	+#
	8	+# This program is free software; you can redistribute it and/or
	9	+# modify it under the terms of the GNU General Public License as
	10	+# published by the Free Software Foundation; either version 2 of
	11	+# the License, or (at your option) any later version.
	12	+#
	13	+# This program is distributed in the hope that it will be useful,
	14	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+# GNU General Public License for more details.
	17	+#
	18	+# You should have received a copy of the GNU General Public License
	19	+# along with this program; if not, write to the Free Software
	20	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+# MA 02111-1307 USA
	22	+#
	23	+
	24	+include $(TOPDIR)/config.mk
	25	+
	26	+LIB = lib$(BOARD).a
	27	+
	28	+OBJS = $(BOARD).o flash.o
	29	+
	30	+$(LIB): .depend $(OBJS)
	31	+ $(AR) crv $@ $^
	32	+
	33	+#########################################################################
	34	+
	35	+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
	36	+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
	37	+
	38	+sinclude .depend
	39	+
	40	+#########################################################################

board/evb64260/intel_flash.h

Diff comments View file @ d84c558

	1	+/************* DEFINES for Intel StrataFlash FLASH chip ******************/
	2	+
	3	+/*
	4	+ * acceptable chips types are:
	5	+ *
	6	+ * 28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A
	7	+ */
	8	+
	9	+/* register addresses, valid only following an CHIP_CMD_RD_ID command */
	10	+#define CHIP_ADDR_REG_MAN 0x000000 /* manufacturer's id */
	11	+#define CHIP_ADDR_REG_DEV 0x000001 /* device id */
	12	+#define CHIP_ADDR_REG_CFGM 0x000003 /* master lock config */
	13	+#define CHIP_ADDR_REG_CFG(b) (((b)<<16)\|2) /* lock config for block b */
	14	+
	15	+/* Commands */
	16	+#define CHIP_CMD_RST 0xFF /* reset flash */
	17	+#define CHIP_CMD_RD_ID 0x90 /* read the id and lock bits */
	18	+#define CHIP_CMD_RD_QUERY 0x98 /* read device capabilities */
	19	+#define CHIP_CMD_RD_STAT 0x70 /* read the status register */
	20	+#define CHIP_CMD_CLR_STAT 0x50 /* clear the staus register */
	21	+#define CHIP_CMD_WR_BUF 0xE8 /* clear the staus register */
	22	+#define CHIP_CMD_PROG 0x40 /* program word command */
	23	+#define CHIP_CMD_ERASE1 0x20 /* 1st word for block erase */
	24	+#define CHIP_CMD_ERASE2 0xD0 /* 2nd word for block erase */
	25	+#define CHIP_CMD_ERASE_SUSP 0xB0 /* suspend block erase */
	26	+#define CHIP_CMD_LOCK 0x60 /* 1st word for all lock cmds */
	27	+#define CHIP_CMD_SET_LOCK_BLK 0x01 /* 2nd wrd set block lock bit */
	28	+#define CHIP_CMD_SET_LOCK_MSTR 0xF1 /* 2nd wrd set master lck bit */
	29	+#define CHIP_CMD_CLR_LOCK_BLK 0xD0 /* 2nd wrd clear blk lck bit */
	30	+
	31	+/* status register bits */
	32	+#define CHIP_STAT_DPS 0x02 /* Device Protect Status */
	33	+#define CHIP_STAT_VPPS 0x08 /* VPP Status */
	34	+#define CHIP_STAT_PSLBS 0x10 /* Program+Set Lock Bit Stat */
	35	+#define CHIP_STAT_ECLBS 0x20 /* Erase+Clr Lock Bit Stat */
	36	+#define CHIP_STAT_ESS 0x40 /* Erase Suspend Status */
	37	+#define CHIP_STAT_RDY 0x80 /* WSM Mach Status, 1=rdy */
	38	+
	39	+#define CHIP_STAT_ERR (CHIP_STAT_VPPS \| CHIP_STAT_DPS \| \
	40	+ CHIP_STAT_ECLBS \| CHIP_STAT_PSLBS)
	41	+
	42	+/* ID and Lock Configuration */
	43	+#define CHIP_RD_ID_LOCK 0x01 /* Bit 0 of each byte */
	44	+#define CHIP_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */
	45	+#define CHIP_RD_ID_DEV CFG_FLASH_ID
	46	+
	47	+/* dimensions */
	48	+#define CHIP_WIDTH 2 /* chips are in 16 bit mode */
	49	+#define CHIP_WSHIFT 1 /* (log2 of CHIP_WIDTH) */
	50	+#define CHIP_NBLOCKS 128
	51	+#define CHIP_BLKSZ (128 * 1024) /* of 128Kbytes each */
	52	+#define CHIP_SIZE (CHIP_BLKSZ * CHIP_NBLOCKS)
	53	+
	54	+/******************** DEFINES for Hymod Flash ****************************/
	55	+
	56	+/*
	57	+ * The hymod board has 2 x 28F320J5 chips running in
	58	+ * 16 bit mode, for a 32 bit wide bank.
	59	+ */
	60	+
	61	+typedef unsigned short bank_word_t; /* 8/16/32/64bit unsigned int */
	62	+typedef volatile bank_word_t *bank_addr_t;
	63	+typedef unsigned long bank_size_t; /* want this big - >= 32 bit */
	64	+
	65	+#define BANK_CHIP_WIDTH 1 /* each bank is 1 chip wide */
	66	+#define BANK_CHIP_WSHIFT 0 /* (log2 of BANK_CHIP_WIDTH) */
	67	+
	68	+#define BANK_WIDTH (CHIP_WIDTH * BANK_CHIP_WIDTH)
	69	+#define BANK_WSHIFT (CHIP_WSHIFT + BANK_CHIP_WSHIFT)
	70	+#define BANK_NBLOCKS CHIP_NBLOCKS
	71	+#define BANK_BLKSZ (CHIP_BLKSZ * BANK_CHIP_WIDTH)
	72	+#define BANK_SIZE (CHIP_SIZE * BANK_CHIP_WIDTH)
	73	+
	74	+#define MAX_BANKS 1 /* only one bank possible */
	75	+
	76	+/* align bank addresses and sizes to bank word boundaries */
	77	+#define BANK_ADDR_WORD_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
	78	+ & ~(BANK_WIDTH - 1)))
	79	+#define BANK_SIZE_WORD_ALIGN(s) ((bank_size_t)BANK_ADDR_WORD_ALIGN( \
	80	+ (bank_size_t)(s) + (BANK_WIDTH - 1)))
	81	+
	82	+/* align bank addresses and sizes to bank block boundaries */
	83	+#define BANK_ADDR_BLK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
	84	+ & ~(BANK_BLKSZ - 1)))
	85	+#define BANK_SIZE_BLK_ALIGN(s) ((bank_size_t)BANK_ADDR_BLK_ALIGN( \
	86	+ (bank_size_t)(s) + (BANK_BLKSZ - 1)))
	87	+
	88	+/* align bank addresses and sizes to bank boundaries */
	89	+#define BANK_ADDR_BANK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
	90	+ & ~(BANK_SIZE - 1)))
	91	+#define BANK_SIZE_BANK_ALIGN(s) ((bank_size_t)BANK_ADDR_BANK_ALIGN( \
	92	+ (bank_size_t)(s) + (BANK_SIZE - 1)))
	93	+
	94	+/* add an offset to a bank address */
	95	+#define BANK_ADDR_OFFSET(a, o) (bank_addr_t)((bank_size_t)(a) + \
	96	+ (bank_size_t)(o))
	97	+
	98	+/* get base address of bank b, given flash base address a */
	99	+#define BANK_ADDR_BASE(a, b) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
	100	+ (bank_size_t)(b) * BANK_SIZE)
	101	+
	102	+/* adjust a bank address to start of next word, block or bank */
	103	+#define BANK_ADDR_NEXT_WORD(a) BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \
	104	+ BANK_WIDTH)
	105	+#define BANK_ADDR_NEXT_BLK(a) BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \
	106	+ BANK_BLKSZ)
	107	+#define BANK_ADDR_NEXT_BANK(a) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
	108	+ BANK_SIZE)
	109	+
	110	+/* get bank address of chip register r given a bank base address a */
	111	+#define BANK_ADDR_REG(a, r) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
	112	+ ((bank_size_t)(r) << BANK_WSHIFT))
	113	+
	114	+/* make a bank address for each chip register address */
	115	+
	116	+#define BANK_ADDR_REG_MAN(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN)
	117	+#define BANK_ADDR_REG_DEV(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV)
	118	+#define BANK_ADDR_REG_CFGM(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM)
	119	+#define BANK_ADDR_REG_CFG(b,a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b))
	120	+
	121	+/*
	122	+ * replicate a chip cmd/stat/rd value into each byte position within a word
	123	+ * so that multiple chips are accessed in a single word i/o operation
	124	+ *
	125	+ * this must be as wide as the bank_word_t type, and take into account the
	126	+ * chip width and bank layout
	127	+ */
	128	+
	129	+#define BANK_FILL_WORD(o) ((bank_word_t)(o))
	130	+
	131	+/* make a bank word value for each chip cmd/stat/rd value */
	132	+
	133	+/* Commands */
	134	+#define BANK_CMD_RST BANK_FILL_WORD(CHIP_CMD_RST)
	135	+#define BANK_CMD_RD_ID BANK_FILL_WORD(CHIP_CMD_RD_ID)
	136	+#define BANK_CMD_RD_STAT BANK_FILL_WORD(CHIP_CMD_RD_STAT)
	137	+#define BANK_CMD_CLR_STAT BANK_FILL_WORD(CHIP_CMD_CLR_STAT)
	138	+#define BANK_CMD_ERASE1 BANK_FILL_WORD(CHIP_CMD_ERASE1)
	139	+#define BANK_CMD_ERASE2 BANK_FILL_WORD(CHIP_CMD_ERASE2)
	140	+#define BANK_CMD_PROG BANK_FILL_WORD(CHIP_CMD_PROG)
	141	+#define BANK_CMD_LOCK BANK_FILL_WORD(CHIP_CMD_LOCK)
	142	+#define BANK_CMD_SET_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_SET_LOCK_BLK)
	143	+#define BANK_CMD_SET_LOCK_MSTR BANK_FILL_WORD(CHIP_CMD_SET_LOCK_MSTR)
	144	+#define BANK_CMD_CLR_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_CLR_LOCK_BLK)
	145	+
	146	+/* status register bits */
	147	+#define BANK_STAT_DPS BANK_FILL_WORD(CHIP_STAT_DPS)
	148	+#define BANK_STAT_PSS BANK_FILL_WORD(CHIP_STAT_PSS)
	149	+#define BANK_STAT_VPPS BANK_FILL_WORD(CHIP_STAT_VPPS)
	150	+#define BANK_STAT_PSLBS BANK_FILL_WORD(CHIP_STAT_PSLBS)
	151	+#define BANK_STAT_ECLBS BANK_FILL_WORD(CHIP_STAT_ECLBS)
	152	+#define BANK_STAT_ESS BANK_FILL_WORD(CHIP_STAT_ESS)
	153	+#define BANK_STAT_RDY BANK_FILL_WORD(CHIP_STAT_RDY)
	154	+
	155	+#define BANK_STAT_ERR BANK_FILL_WORD(CHIP_STAT_ERR)
	156	+
	157	+/* ID and Lock Configuration */
	158	+#define BANK_RD_ID_LOCK BANK_FILL_WORD(CHIP_RD_ID_LOCK)
	159	+#define BANK_RD_ID_MAN BANK_FILL_WORD(CHIP_RD_ID_MAN)
	160	+#define BANK_RD_ID_DEV BANK_FILL_WORD(CHIP_RD_ID_DEV)

board/evb64260/zuma_pbb.h

Diff comments View file @ d84c558

	1	+#ifndef ZUMA_PBB_H
	2	+#define ZUMA_PBB_H
	3	+
	4	+#define MAX_NUM_BUFFER_PER_RING 32
	5	+
	6	+#ifdef __BIG_ENDIAN
	7	+#define cpu_bits _be_s_bits /* use with le32_to_cpu only */
	8	+#define pci_bits _be_bits /* may contain swapped bytes,
	9	+ but dont need le32_to_cpu */
	10	+#endif
	11	+
	12	+#ifdef __LITTLE_ENDIAN
	13	+#define cpu_bits _le_bits
	14	+#define pci_bits _le_bits
	15	+#endif
	16	+
	17	+#define VENDOR_ID_ZUMA 0x1172
	18	+#define DEVICE_ID_ZUMA_PBB 0x0004
	19	+
	20	+#define RXDBP(chan) (&sip->rx_desc[chan].base) /* ch8 /
	21	+#define RXDP(chan) (&sip->rx_desc[chan].current) /* ch8 + 4 /
	22	+#define TXDBP(chan) (&sip->tx_desc[chan].base) /* ch8 + 64 /
	23	+#define TXDP(chan) (&sip->tx_desc[chan].current) /* ch8 + 68 /
	24	+
	25	+#define PBB_DMA_OWN_BIT 0x80000000
	26	+#define PBB_DMA_LAST_BIT 0x40000000
	27	+
	28	+#define EOF_RX_FLAG 1 /* bit 0 */
	29	+#define EOB_RX_FLAG 2 /* bit 1 */
	30	+#define EOF_TX_FLAG 4 /* bit 2 */
	31	+#define EOB_TX_FLAG 8 /* bit 3 */
	32	+
	33	+#define TX_MODE(m) (((m)&7) << 16)
	34	+
	35	+#define RX_DESC(i) (cs->rx_desc[i])
	36	+#define TX_DESC(i) (cs->tx_desc[i])
	37	+
	38	+#define RX_CONTROL(i) (RX_DESC(i).control.word)
	39	+#define RX_CONTROL_SIZE(i) (RX_DESC(i).control.rx.size)
	40	+#define TX_CONTROL(i) (TX_DESC(i).control.word)
	41	+
	42	+#define RX_DATA_P(i) (&RX_DESC(i).ptr)
	43	+#define TX_DATA_P(i) (&TX_DESC(i).ptr)
	44	+
	45	+typedef volatile unsigned char V8;
	46	+typedef volatile unsigned short V16;
	47	+typedef volatile unsigned int V32;
	48	+
	49	+/* RAM descriptor layout */
	50	+typedef struct _tag_dma_descriptor {
	51	+ V32 ptr;
	52	+ union {
	53	+ struct {
	54	+ V32 owner:1;
	55	+ V32 last:1;
	56	+ V32 reserved0: 10;
	57	+ V32 tx_mode: 4;
	58	+
	59	+ V32 reserved1: 5;
	60	+ V32 size: 11;
	61	+ } tx;
	62	+ struct {
	63	+ V32 owner:1;
	64	+ V32 last:1;
	65	+ V32 reserved0: 14;
	66	+
	67	+ V32 reserved1: 5;
	68	+ V32 size: 11;
	69	+ } rx;
	70	+ V32 word;
	71	+ } control;
	72	+} DMA_DESCRIPTOR;
	73	+
	74	+/*
	75	+ * NOTE: DO NOT USE structure to write non-word values... all registers
	76	+ * MUST be written 4 bytes at a time in SI version 0.
	77	+ * Non-word writes will result in "unaccessed" bytes written as zero.
	78	+ *
	79	+ * Byte reads are allowed.
	80	+ *
	81	+ * V32 pads are because the registers are spaced every 8 bytes (64 bits)
	82	+ *
	83	+ */
	84	+
	85	+/* NOTE!!! 4 dwords */
	86	+typedef struct _tag_dma_descriptor_ring {
	87	+ DMA_DESCRIPTOR *base;
	88	+ V32 pad1; /* skip high dword */
	89	+ volatile DMA_DESCRIPTOR *current;
	90	+ V32 pad3; /* skip high dword */
	91	+} DMA_DESCRIPTOR_RING;
	92	+
	93	+/* 1 dword */
	94	+typedef union _tag_dma_generic {
	95	+ struct { /* byte 3 2 1 0 */
	96	+ V32 chan7:4; /* bits 31-28 */
	97	+ V32 chan6:4; /* bits 27-24 */
	98	+ V32 chan5:4; /* bits 23-20 */
	99	+ V32 chan4:4; /* bits 19-16 */
	100	+ V32 chan3:4; /* bits 15-12 */
	101	+ V32 chan2:4; /* bits 11-8 */
	102	+ V32 chan1:4; /* bits 7-4 */
	103	+ V32 chan0:4; /* bits 3-0 */
	104	+ } _be_s_bits;
	105	+ struct { /* byte 0 1 2 3 */
	106	+ V32 chan1:4; /* bits 7-4 */
	107	+ V32 chan0:4; /* bits 3-0 */
	108	+ V32 chan3:4; /* bits 15-12 */
	109	+ V32 chan2:4; /* bits 11-8 */
	110	+ V32 chan5:4; /* bits 23-20 */
	111	+ V32 chan4:4; /* bits 19-16 */
	112	+ V32 chan7:4; /* bits 31-28 */
	113	+ V32 chan6:4; /* bits 27-24 */
	114	+ } _be_bits;
	115	+ struct { /* byte 0 1 2 3 */
	116	+ V32 chan0:4; /* bits 0-3 */
	117	+ V32 chan1:4; /* bits 4-7 */
	118	+ V32 chan2:4; /* bits 8-11 */
	119	+ V32 chan3:4; /* bits 12-15 */
	120	+ V32 chan4:4; /* bits 16-19 */
	121	+ V32 chan5:4; /* bits 20-23 */
	122	+ V32 chan6:4; /* bits 24-27 */
	123	+ V32 chan7:4; /* bits 28-31 */
	124	+ } _le_bits;
	125	+ V8 byte[4];
	126	+ V32 word;
	127	+} DMA_RXTX_ENABLE, DMA_RX_DELETE,
	128	+ DMA_INT_STATUS, DMA_INT_MASK,
	129	+ DMA_RX_LEVEL_STATUS, DMA_RX_LEVEL_INT_MASK;
	130	+
	131	+/* 1 dword */
	132	+typedef union _tag_dma_rx_timer{
	133	+ struct {
	134	+ V32 res0:8; /* bits 32-24 */
	135	+ V32 res1:7; /* bits 23-17 */
	136	+ V32 enable:1; /* bit 16 */
	137	+ V32 value:16; /* bits 15-0 */
	138	+ } _be_s_bits;
	139	+ struct {
	140	+ /* crosses byte boundary. must use swap. */
	141	+ V32 s_value:16; /* bits 7-0,15-8 */
	142	+ V32 enable:1; /* bit 16 */
	143	+ V32 res1:7; /* bits 23-17 */
	144	+ V32 res0:8; /* bits 32-24 */
	145	+ } _be_bits;
	146	+ struct {
	147	+ V32 value:16; /* bits 0-15 */
	148	+ V32 enable:1; /* bit 16 */
	149	+ V32 res1:7; /* bits 17-23 */
	150	+ V32 res0:8; /* bits 24-32 */
	151	+ } _le_bits;
	152	+ V8 byte[4];
	153	+ V32 word;
	154	+} DMA_RX_TIMER;
	155	+
	156	+/* NOTE!!!: 2 dwords */
	157	+typedef struct _tag_dma_desc_level{
	158	+ union {
	159	+ struct {
	160	+ V32 res1:8; /* bits 31-24 */
	161	+ V32 res0:7; /* bits 23-17 */
	162	+ V32 write:1; /* bit 16 */
	163	+ V32 thresh:8; /* bits 15-8 */
	164	+ V32 level:8; /* bits 7-0 */
	165	+ } _be_s_bits;
	166	+ struct {
	167	+ V32 level:8; /* bits 7-0 */
	168	+ V32 thresh:8; /* bits 15-8 */
	169	+ V32 res0:7; /* bits 30-17 */
	170	+ V32 write:1; /* bit 16 */
	171	+ V32 res1:8; /* bits 31-24 */
	172	+ } _be_bits;
	173	+ struct {
	174	+ V32 level:8; /* bits 0-7 */
	175	+ V32 thresh:8; /* bits 8-15 */
	176	+ V32 write:1; /* bit 16 */
	177	+ V32 res0:7; /* bit 17-30 */
	178	+ V32 res1:8; /* bits 24-31 */
	179	+ } _le_bits;
	180	+ V8 byte[4];
	181	+ V32 word;
	182	+ } desc;
	183	+ V32 pad1;
	184	+} DMA_DESC_LEVEL;
	185	+
	186	+typedef struct _tag_pbb_dma_reg_map {
	187	+ /* 0-15 (0x000-0x078) */
	188	+ DMA_DESCRIPTOR_RING rx_desc[8]; /* 4 dwords each, 128 bytes tot. */
	189	+
	190	+ /* 16-31 (0x080-0x0f8) */
	191	+ DMA_DESCRIPTOR_RING tx_desc[8]; /* 4 dwords each, 128 bytes tot. */
	192	+
	193	+ /* 32/33 (0x100/0x108) */
	194	+ V32 reserved_32;
	195	+ V32 pad_32;
	196	+ V32 reserved_33;
	197	+ V32 pad_33;
	198	+
	199	+ /* 34 (0x110) */
	200	+ DMA_RXTX_ENABLE rxtx_enable;
	201	+ V32 pad_34;
	202	+
	203	+ /* 35 (0x118) */
	204	+ DMA_RX_DELETE rx_delete;
	205	+ V32 pad_35;
	206	+
	207	+ /* 36-38 (0x120-0x130) */
	208	+ DMA_INT_STATUS status;
	209	+ V32 pad_36;
	210	+ DMA_INT_STATUS last_status;
	211	+ V32 pad_37;
	212	+ DMA_INT_MASK int_mask;
	213	+ V32 pad_38;
	214	+
	215	+ /* 39/40 (0x138/0x140) */
	216	+ union {
	217	+ /* NOTE!! 4 dwords */
	218	+ struct {
	219	+ V32 channel_3:8;
	220	+ V32 channel_2:8;
	221	+ V32 channel_1:8;
	222	+ V32 channel_0:8;
	223	+ V32 pad1;
	224	+ V32 channel_7:8;
	225	+ V32 channel_6:8;
	226	+ V32 channel_5:8;
	227	+ V32 channel_4:8;
	228	+ V32 pad3;
	229	+ } _be_s_bits;
	230	+ struct {
	231	+ V32 channel_0:8;
	232	+ V32 channel_1:8;
	233	+ V32 channel_2:8;
	234	+ V32 channel_3:8;
	235	+ V32 pad1;
	236	+ V32 channel_4:8;
	237	+ V32 channel_5:8;
	238	+ V32 channel_6:8;
	239	+ V32 channel_7:8;
	240	+ V32 pad3;
	241	+ } _be_bits, _le_bits;
	242	+ V8 byte[16];
	243	+ V32 word[4];
	244	+ } rx_size;
	245	+
	246	+ /* 41/42 (0x148/0x150) */
	247	+ V32 reserved_41;
	248	+ V32 pad_41;
	249	+ V32 reserved_42;
	250	+ V32 pad_42;
	251	+
	252	+ /* 43/44 (0x158/0x160) */
	253	+ DMA_RX_LEVEL_STATUS rx_level_status;
	254	+ V32 pad_43;
	255	+ DMA_RX_LEVEL_INT_MASK rx_level_int_mask;
	256	+ V32 pad_44;
	257	+
	258	+ /* 45 (0x168) */
	259	+ DMA_RX_TIMER rx_timer;
	260	+ V32 pad_45;
	261	+
	262	+ /* 46 (0x170) */
	263	+ V32 reserved_46;
	264	+ V32 pad_46;
	265	+
	266	+ /* 47 (0x178) */
	267	+ V32 mbox_status;
	268	+ V32 pad_47;
	269	+
	270	+ /* 48/49 (0x180/0x188) */
	271	+ V32 mbox_out;
	272	+ V32 pad_48;
	273	+ V32 mbox_in;
	274	+ V32 pad_49;
	275	+
	276	+ /* 50 (0x190) */
	277	+ V32 config;
	278	+ V32 pad_50;
	279	+
	280	+ /* 51/52 (0x198/0x1a0) */
	281	+ V32 c2a_ctr;
	282	+ V32 pad_51;
	283	+ V32 a2c_ctr;
	284	+ V32 pad_52;
	285	+
	286	+ /* 53 (0x1a8) */
	287	+ union {
	288	+ struct {
	289	+ V32 rev_major:8; /* bits 31-24 */
	290	+ V32 rev_minor:8; /* bits 23-16 */
	291	+ V32 reserved:16; /* bits 15-0 */
	292	+ } _be_s_bits;
	293	+ struct {
	294	+ V32 s_reserved:16; /* bits 7-0, 15-8 */
	295	+ V32 rev_minor:8; /* bits 23-16 */
	296	+ V32 rev_major:8; /* bits 31-24 */
	297	+ } _be_bits;
	298	+ struct {
	299	+ V32 reserved:16; /* bits 0-15 */
	300	+ V32 rev_minor:8; /* bits 16-23 */
	301	+ V32 rev_major:8; /* bits 24-31 */
	302	+ } _le_bits;
	303	+ V8 byte[4];
	304	+ V32 word;
	305	+ } version;
	306	+ V32 pad_53;
	307	+
	308	+ /* 54-59 (0x1b0-0x1d8) */
	309	+ V32 debug_54;
	310	+ V32 pad_54;
	311	+ V32 debug_55;
	312	+ V32 pad_55;
	313	+ V32 debug_56;
	314	+ V32 pad_56;
	315	+ V32 debug_57;
	316	+ V32 pad_57;
	317	+ V32 debug_58;
	318	+ V32 pad_58;
	319	+ V32 debug_59;
	320	+ V32 pad_59;
	321	+
	322	+ /* 60 (0x1e0) */
	323	+ V32 timestamp;
	324	+ V32 pad_60;
	325	+
	326	+ /* 61-63 (0x1e8-0x1f8) */
	327	+ V32 debug_61;
	328	+ V32 pad_61;
	329	+ V32 debug_62;
	330	+ V32 pad_62;
	331	+ V32 debug_63;
	332	+ V32 pad_63;
	333	+
	334	+ /* 64-71 (0x200 - 0x238) */
	335	+ DMA_DESC_LEVEL rx_desc_level[8]; /* 2 dwords each, 32 bytes tot. */
	336	+
	337	+ /* 72-98 (0x240 - 0x2f8) */
	338	+ /* reserved */
	339	+
	340	+ /* 96-127 (0x300 - 0x3f8) */
	341	+ /* mirrors (0x100 - 0x1f8) */
	342	+
	343	+} PBB_DMA_REG_MAP;
	344	+
	345	+
	346	+#endif /* ZUMA_PBB_H */

include/jffs2/jffs2_1pass.h

Diff comments View file @ d84c558

	1	+u32 jffs2_1pass_ls(struct part_info part,const char fname);
	2	+u32 jffs2_1pass_load(char dest, struct part_info part,const char *fname);
	3	+u32 jffs2_1pass_info(struct part_info *part);

include/mpc74xx.h

Diff comments View file @ d84c558

	1	+/*
	2	+ * (C) Copyright 2001
	3	+ * Josh Huber, Mission Critical Linux, Inc. <huber@mclx.com>
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+/*
	25	+ * mpc74xx.h
	26	+ *
	27	+ * MPC74xx specific definitions
	28	+ */
	29	+
	30	+#ifndef __MPC74XX_H__
	31	+#define __MPC74XX_H__
	32	+
	33	+/*----------------------------------------------------------------
	34	+ * Exception offsets (PowerPC standard)
	35	+ */
	36	+#define EXC_OFF_SYS_RESET 0x0100 /* default system reset offset */
	37	+
	38	+/*----------------------------------------------------------------
	39	+ * l2cr values
	40	+ */
	41	+#define l2cr 1017
	42	+
	43	+#define L2CR_L2E 0x80000000 /* bit 0 - enable */
	44	+#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */
	45	+#define L2CR_L2SIZ_2M 0x00000000 /* bits 2-3 - 2MB, MPC7400 only! */
	46	+#define L2CR_L2SIZ_1M 0x30000000 /* ... 1MB */
	47	+#define L2CR_L2SIZ_HM 0x20000000 /* ... 512K */
	48	+#define L2CR_L2SIZ_QM 0x10000000 /* ... 256k */
	49	+#define L2CR_L2CLK_1 0x02000000 /* bits 4-6 clock ratio div 1 */
	50	+#define L2CR_L2CLK_1_5 0x04000000 /* bits 4-6 clock ratio div 1.5 */
	51	+#define L2CR_L2CLK_2 0x08000000 /* bits 4-6 clock ratio div 2 */
	52	+#define L2CR_L2CLK_2_5 0x0a000000 /* bits 4-6 clock ratio div 2.5 */
	53	+#define L2CR_L2CLK_3 0x0c000000 /* bits 4-6 clock ratio div 3 */
	54	+#define L2CR_L2CLK_3_5 0x06000000 /* bits 4-6 clock ratio div 3.5 */
	55	+#define L2CR_L2CLK_4 0x0e000000 /* bits 4-6 clock ratio div 4 */
	56	+#define L2CR_L2RAM_BURST 0x01000000 /* bits 7-8 - burst SRAM */
	57	+#define L2CR_DO 0x00400000 /* bit 9 - enable caching of instr. in L2 */
	58	+#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */
	59	+#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */
	60	+#define L2CR_L2WT 0x00080000 /* bit 12 - l2 write-through */
	61	+#define L2CR_TS 0x00040000 /* bit 13 - test support on */
	62	+#define L2CR_TS_OFF -L2CR_TS /* bit 13 - test support off */
	63	+#define L2CR_L2OH_5 0x00000000 /* bits 14-15 - output hold time = short */
	64	+#define L2CR_L2OH_1 0x00010000 /* bits 14-15 - output hold time = medium */
	65	+#define L2CR_L2OH_INV 0x00020000 /* bits 14-15 - output hold time = long */
	66	+#define L2CR_L2IP 0x00000001 /* global invalidate in progress */
	67	+
	68	+/*----------------------------------------------------------------
	69	+ * BAT settings. Look in config_<BOARD>.h for the actual setup
	70	+ */
	71	+
	72	+#define BATU_BL_128K 0x00000000
	73	+#define BATU_BL_256K 0x00000004
	74	+#define BATU_BL_512K 0x0000000c
	75	+#define BATU_BL_1M 0x0000001c
	76	+#define BATU_BL_2M 0x0000003c
	77	+#define BATU_BL_4M 0x0000007c
	78	+#define BATU_BL_8M 0x000000fc
	79	+#define BATU_BL_16M 0x000001fc
	80	+#define BATU_BL_32M 0x000003fc
	81	+#define BATU_BL_64M 0x000007fc
	82	+#define BATU_BL_128M 0x00000ffc
	83	+#define BATU_BL_256M 0x00001ffc
	84	+
	85	+#define BATU_VS 0x00000002
	86	+#define BATU_VP 0x00000001
	87	+#define BATU_INVALID 0x00000000
	88	+
	89	+#define BATL_WRITETHROUGH 0x00000040 /* W */
	90	+#define BATL_CACHEINHIBIT 0x00000020 /* I */
	91	+#define BATL_COHERENT 0x00000010 /* M */
	92	+#define BATL_GUARDED 0x00000008 /* G */
	93	+
	94	+#define BATL_NO_ACCESS 0x00000000
	95	+#define BATL_RO 0x00000001
	96	+#define BATL_RW 0x00000002
	97	+
	98	+#endif /* __MPC74XX_H__ */

tools/gdb/Makefile

Diff comments View file @ d84c558

	1	+#
	2	+# (C) Copyright 2000
	3	+# Murray Jensen <Murray.Jensen@cmst.csiro.au>
	4	+#
	5	+# See file CREDITS for list of people who contributed to this
	6	+# project.
	7	+#
	8	+# This program is free software; you can redistribute it and/or
	9	+# modify it under the terms of the GNU General Public License as
	10	+# published by the Free Software Foundation; either version 2 of
	11	+# the License, or (at your option) any later version.
	12	+#
	13	+# This program is distributed in the hope that it will be useful,
	14	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+# GNU General Public License for more details.
	17	+#
	18	+# You should have received a copy of the GNU General Public License
	19	+# along with this program; if not, write to the Free Software
	20	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+# MA 02111-1307 USA
	22	+#
	23	+
	24	+include $(TOPDIR)/config.mk
	25	+
	26	+BINS = gdbsend gdbcont
	27	+
	28	+ifneq ($(HOSTOS),HP-UX)
	29	+BINS+= astest
	30	+endif
	31	+
	32	+
	33	+OBJS = gdbsend.o gdbcont.o astest.o error.o remote.o serial.o
	34	+
	35	+#
	36	+# Use native tools and options
	37	+#
	38	+CPPFLAGS = -I$(BFD_ROOT_DIR)/include
	39	+CFLAGS = $(HOST_CFLAGS) -O $(CPPFLAGS)
	40	+CC = $(HOSTCC)
	41	+MAKEDEPEND = makedepend
	42	+
	43	+HOSTOS := $(shell uname -s \| sed -e 's/$[Cc][Yy][Gg][Ww][Ii][Nn]$.*/cygwin/')
	44	+
	45	+ifeq ($(HOSTOS),cygwin)
	46	+
	47	+all:
	48	+.depend:
	49	+
	50	+else # ! CYGWIN
	51	+
	52	+all: $(BINS)
	53	+
	54	+gdbsend: gdbsend.o error.o remote.o serial.o
	55	+ $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
	56	+
	57	+gdbcont: gdbcont.o error.o remote.o serial.o
	58	+ $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
	59	+
	60	+astest: astest.o error.o
	61	+ $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ -L$(BFD_ROOT_DIR)/lib -lbfd -liberty
	62	+
	63	+clean:
	64	+ rm -f $(OBJS)
	65	+
	66	+distclean: clean
	67	+ rm -f $(BINS) core *.bak .depend
	68	+
	69	+#########################################################################
	70	+
	71	+.depend: Makefile $(OBJS:.o=.c)
	72	+ $(CC) -M $(CPPFLAGS) -I../include $(OBJS:.o=.c) > $@
	73	+
	74	+-include .depend
	75	+
	76	+#########################################################################
	77	+
	78	+endif # cygwin