arm: socfpga: Enable build for Arria 10

Update Kconfig and Makefile to enable Arria 10. Clean up Makefile and sorting *.o alphanumerically. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

arm: socfpga: Enable build for Arria 10
Update Kconfig and Makefile to enable Arria 10. Clean up Makefile and sorting *.o alphanumerically. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Ley Foon Tan · Marek Vasut
1 parent 9b21de7811
Showing 2 changed files with 43 additions and 13 deletions Side-by-side Diff
arch/arm/mach-socfpga/Kconfig
arch/arm/mach-socfpga/Makefile
@@ -37,6 +37,9 @@
 	bool
 	select TARGET_SOCFPGA_GEN5
  
+config TARGET_SOCFPGA_ARRIA10
+	bool
+
 config TARGET_SOCFPGA_CYCLONE5
 	bool
 	select TARGET_SOCFPGA_GEN5
@@ -49,6 +52,10 @@
 	prompt "Altera SOCFPGA board select"
 	optional
  
+config TARGET_SOCFPGA_ARRIA10_SOCDK
+	bool "Altera SOCFPGA SoCDK (Arria 10)"
+	select TARGET_SOCFPGA_ARRIA10
+
 config TARGET_SOCFPGA_ARRIA5_SOCDK
 	bool "Altera SOCFPGA SoCDK (Arria V)"
 	select TARGET_SOCFPGA_ARRIA5
@@ -98,6 +105,7 @@
  
 config SYS_BOARD
 	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+	default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
@@ -111,6 +119,7 @@
  
 config SYS_VENDOR
 	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
+	default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
 	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 	default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
 	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
@@ -125,6 +134,7 @@
  
 config SYS_CONFIG_NAME
 	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+	default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
@@ -2,29 +2,49 @@
 # (C) Copyright 2000-2003
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
-# Copyright (C) 2012 Altera Corporation <www.altera.com>
+# Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
  
-obj-y	+= misc.o timer.o reset_manager.o clock_manager.o \
-	   fpga_manager.o board.o
+obj-y	+= board.o
+obj-y	+= clock_manager.o
+obj-y	+= fpga_manager.o
+obj-y	+= misc.o
+obj-y	+= reset_manager.o
+obj-y	+= timer.o
  
-obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clock_manager_arria10.o \
-					pinmux_arria10.o	\
-					misc_arria10.o		\
-					reset_manager_arria10.o
+ifdef CONFIG_TARGET_SOCFPGA_GEN5
+obj-y	+= clock_manager_gen5.o
+obj-y	+= misc_gen5.o
+obj-y	+= reset_manager_gen5.o
+obj-y	+= scan_manager.o
+obj-y	+= system_manager_gen5.o
+obj-y	+= wrap_pll_config.o
+endif
  
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
+obj-y	+= clock_manager_arria10.o
+obj-y	+= misc_arria10.o
+obj-y	+= pinmux_arria10.o
+obj-y	+= reset_manager_arria10.o
+endif
  
+ifdef CONFIG_SPL_BUILD
+obj-y	+= spl.o
+ifdef CONFIG_TARGET_SOCFPGA_GEN5
+obj-y	+= freeze_controller.o
+obj-y	+= wrap_iocsr_config.o
+obj-y	+= wrap_pinmux_config.o
+obj-y	+= wrap_sdram_config.o
+endif
+endif
+
+ifdef CONFIG_TARGET_SOCFPGA_GEN5
 # QTS-generated config file wrappers
-obj-$(CONFIG_TARGET_SOCFPGA_GEN5)	+= scan_manager.o wrap_pll_config.o \
-					   clock_manager_gen5.o reset_manager_gen5.o \
-					   misc_gen5.o system_manager_gen5.o
-obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o	\
-			   wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o	+= -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pinmux_config.o	+= -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pll_config.o	+= -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_sdram_config.o	+= -I$(srctree)/board/$(BOARDDIR)
+endif
...	...	@@ -37,6 +37,9 @@
37	37	bool
38	38	select TARGET_SOCFPGA_GEN5
39	39
	40	+config TARGET_SOCFPGA_ARRIA10
	41	+ bool
	42	+
40	43	config TARGET_SOCFPGA_CYCLONE5
41	44	bool
42	45	select TARGET_SOCFPGA_GEN5
...	...	@@ -49,6 +52,10 @@
49	52	prompt "Altera SOCFPGA board select"
50	53	optional
51	54
	55	+config TARGET_SOCFPGA_ARRIA10_SOCDK
	56	+ bool "Altera SOCFPGA SoCDK (Arria 10)"
	57	+ select TARGET_SOCFPGA_ARRIA10
	58	+
52	59	config TARGET_SOCFPGA_ARRIA5_SOCDK
53	60	bool "Altera SOCFPGA SoCDK (Arria V)"
54	61	select TARGET_SOCFPGA_ARRIA5
...	...	@@ -98,6 +105,7 @@
98	105
99	106	config SYS_BOARD
100	107	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
	108	+ default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
101	109	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
102	110	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
103	111	default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
...	...	@@ -111,6 +119,7 @@
111	119
112	120	config SYS_VENDOR
113	121	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
	122	+ default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
114	123	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
115	124	default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
116	125	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
...	...	@@ -125,6 +134,7 @@
125	134
126	135	config SYS_CONFIG_NAME
127	136	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
	137	+ default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
128	138	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
129	139	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
130	140	default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
...	...	@@ -2,29 +2,49 @@
2	2	# (C) Copyright 2000-2003
3	3	# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	4	#
5		-# Copyright (C) 2012 Altera Corporation <www.altera.com>
	5	+# Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
6	6	#
7	7	# SPDX-License-Identifier: GPL-2.0+
8	8	#
9	9
10		-obj-y += misc.o timer.o reset_manager.o clock_manager.o \
11		- fpga_manager.o board.o
	10	+obj-y += board.o
	11	+obj-y += clock_manager.o
	12	+obj-y += fpga_manager.o
	13	+obj-y += misc.o
	14	+obj-y += reset_manager.o
	15	+obj-y += timer.o
12	16
13		-obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clock_manager_arria10.o \
14		- pinmux_arria10.o \
15		- misc_arria10.o \
16		- reset_manager_arria10.o
	17	+ifdef CONFIG_TARGET_SOCFPGA_GEN5
	18	+obj-y += clock_manager_gen5.o
	19	+obj-y += misc_gen5.o
	20	+obj-y += reset_manager_gen5.o
	21	+obj-y += scan_manager.o
	22	+obj-y += system_manager_gen5.o
	23	+obj-y += wrap_pll_config.o
	24	+endif
17	25
18		-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
	26	+ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
	27	+obj-y += clock_manager_arria10.o
	28	+obj-y += misc_arria10.o
	29	+obj-y += pinmux_arria10.o
	30	+obj-y += reset_manager_arria10.o
	31	+endif
19	32
	33	+ifdef CONFIG_SPL_BUILD
	34	+obj-y += spl.o
	35	+ifdef CONFIG_TARGET_SOCFPGA_GEN5
	36	+obj-y += freeze_controller.o
	37	+obj-y += wrap_iocsr_config.o
	38	+obj-y += wrap_pinmux_config.o
	39	+obj-y += wrap_sdram_config.o
	40	+endif
	41	+endif
	42	+
	43	+ifdef CONFIG_TARGET_SOCFPGA_GEN5
20	44	# QTS-generated config file wrappers
21		-obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \
22		- clock_manager_gen5.o reset_manager_gen5.o \
23		- misc_gen5.o system_manager_gen5.o
24		-obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \
25		- wrap_sdram_config.o
26	45	CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
27	46	CFLAGS_wrap_pinmux_config.o += -I$(srctree)/board/$(BOARDDIR)
28	47	CFLAGS_wrap_pll_config.o += -I$(srctree)/board/$(BOARDDIR)
29	48	CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR)
	49	+endif