Commit d8c099ece2f8d25d153a1f0ed962acfa4da18375
1 parent
6cdf9e3523
Exists in
smarc-imx7_v2017.03_4.9.11_1.0.0_ga
sync device tree with kernel 4.9
Showing 3 changed files with 14 additions and 7 deletions Side-by-side Diff
arch/arm/dts/imx7d-smarcfimx7.dts
| ... | ... | @@ -612,13 +612,12 @@ |
| 612 | 612 | }; |
| 613 | 613 | |
| 614 | 614 | &usdhc3 { |
| 615 | - pinctrl-names = "default", "state_100mhz", "state_200mhz"; | |
| 616 | - pinctrl-0 = <&pinctrl_usdhc3>; | |
| 617 | - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; | |
| 618 | - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; | |
| 615 | + pinctrl-names = "default"; | |
| 616 | + pinctrl-0 = <&pinctrl_usdhc3>; | |
| 619 | 617 | assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; |
| 620 | 618 | assigned-clock-rates = <400000000>; |
| 621 | 619 | bus-width = <8>; |
| 620 | + fsl,tuning-step = <2>; | |
| 622 | 621 | non-removable; |
| 623 | 622 | status = "okay"; |
| 624 | 623 | }; |
| ... | ... | @@ -661,6 +660,7 @@ |
| 661 | 660 | MX7D_PAD_ENET1_COL__GPIO7_IO15 0x80000000 /* ENET1_INT# */ |
| 662 | 661 | MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x80000000 /* ENET2_INT# */ |
| 663 | 662 | MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x80000000 /* WDT_TIME_OUT# */ |
| 663 | + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x5d /* eMMC_Reset# */ | |
| 664 | 664 | >; |
| 665 | 665 | }; |
| 666 | 666 |
arch/arm/dts/imx7s-smarcfimx7.dts
| ... | ... | @@ -549,13 +549,12 @@ |
| 549 | 549 | }; |
| 550 | 550 | |
| 551 | 551 | &usdhc3 { |
| 552 | - pinctrl-names = "default", "state_100mhz", "state_200mhz"; | |
| 552 | + pinctrl-names = "default"; | |
| 553 | 553 | pinctrl-0 = <&pinctrl_usdhc3>; |
| 554 | - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; | |
| 555 | - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; | |
| 556 | 554 | assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; |
| 557 | 555 | assigned-clock-rates = <400000000>; |
| 558 | 556 | bus-width = <8>; |
| 557 | + fsl,tuning-step = <2>; | |
| 559 | 558 | non-removable; |
| 560 | 559 | status = "okay"; |
| 561 | 560 | }; |
| ... | ... | @@ -598,6 +597,7 @@ |
| 598 | 597 | MX7D_PAD_ENET1_COL__GPIO7_IO15 0x80000000 /* ENET1_INT# */ |
| 599 | 598 | MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x80000000 /* ENET2_INT# */ |
| 600 | 599 | MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x80000000 /* WDT_TIME_OUT# */ |
| 600 | + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x5d /* eMMC_Reset# */ | |
| 601 | 601 | >; |
| 602 | 602 | }; |
| 603 | 603 |
board/embedian/smarcfimx7/smarcfimx7.c
| ... | ... | @@ -917,6 +917,13 @@ |
| 917 | 917 | gpio_request(IMX_GPIO_NR(5, 2), "SDIO_PWR_EN"); |
| 918 | 918 | gpio_direction_output(IMX_GPIO_NR(5, 2), 1); |
| 919 | 919 | |
| 920 | +/* eMMC Power Reset */ | |
| 921 | +#define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11) | |
| 922 | + gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr"); | |
| 923 | + gpio_direction_output(USDHC3_PWR_GPIO, 0); | |
| 924 | + udelay(500); | |
| 925 | + gpio_direction_output(USDHC3_PWR_GPIO, 1); | |
| 926 | + | |
| 920 | 927 | /* SMARC BOOT_SEL*/ |
| 921 | 928 | gpio_request(IMX_GPIO_NR(5, 15), "BOOT_SEL_1"); |
| 922 | 929 | gpio_request(IMX_GPIO_NR(5, 16), "BOOT_SEL_2"); |