Eric Lee / smarc-uboot

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Commit d8d5fdb7b2ab9154beee2936082bfb65bf4d9209

Authored by Laurentiu Tudor
Committed by Prabhakar Kushwaha
1 parent 910e8fdaac
Exists in smarc_8mq_lf_v2020.04 and in 11 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

fsl_sec: fix register layout on Layerscape architectures 

On Layerscape architectures the SEC memory map is 1MB and the
register blocks contained in it are 64KB aligned, not 4KB as
the ccsr_sec structure currently assumes. Fix the layout of
the structure for these architectures.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Showing 1 changed file with 8 additions and 0 deletions Side-by-side Diff

... ... @@ -121,10 +121,18 @@
121 121 u32 chanum_ls; /* CHA Number Register, LS */
122 122 u32 secvid_ms; /* SEC Version ID Register, MS */
123 123 u32 secvid_ls; /* SEC Version ID Register, LS */
  124 +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
  125 + u8 res9[0x6f020];
  126 +#else
124 127 u8 res9[0x6020];
  128 +#endif
125 129 u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
126 130 u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
  131 +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
  132 + u8 res10[0x8ffd8];
  133 +#else
127 134 u8 res10[0x8fd8];
  135 +#endif
128 136 } ccsr_sec_t;
129 137  
130 138 #define SEC_CTPR_MS_AXI_LIODN 0x08000000