Eric Lee / smarc-uboot

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Commit d978780b2e676c005460cd561f4f15b5220bdf49

Authored by Wolfgang Denk
2 parents b54d1f26ff bcec8f49d1
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Merge branch 'master' of git://git.denx.de/u-boot-microblaze 

* 'master' of git://git.denx.de/u-boot-microblaze:
  microblaze: Wire up SPI driver
  spi: microblaze: Adds driver for Xilinx SPI controller
  microblaze: intc: Clear interrupt code
  microblaze: Call serial multi initialization
  microblaze: Move __udelay implementation
  microblaze: Remove extern from board.c
  microblaze: Wire up dts configuration
  fdt: Add board specific dts inclusion
  microblaze: Move individual board linker scripts to common script in cpu tree.
  microblaze: Add gpio.h
  microblaze: Add missing undefs for UBI and UBIFS
  microblaze: Expand and correct configuration comments
  microblaze: Enable ubi support
  microblaze: Avoid compile error on systems without cfi flash
  microblaze: Remove wrong define CONFIG_SYS_FLASH_PROTECTION

Conflicts:
	drivers/spi/Makefile

Signed-off-by: Wolfgang Denk <wd@denx.de>

Showing 18 changed files Side-by-side Diff

arch/microblaze/config.mk
Diff comments   View file @ d978780
... ... @@ -29,4 +29,6 @@
29 29 CONFIG_STANDALONE_LOAD_ADDR ?= 0x80F00000
30 30  
31 31 PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__
  32 +
  33 +LDSCRIPT ?= $(SRCTREE)/$(CPUDIR)/u-boot.lds
arch/microblaze/cpu/interrupts.c
Diff comments   View file @ d978780
... ... @@ -26,6 +26,7 @@
26 26  
27 27 #include <common.h>
28 28 #include <command.h>
  29 +#include <malloc.h>
29 30 #include <asm/microblaze_intc.h>
30 31 #include <asm/asm.h>
31 32  
32 33  
33 34  
34 35  
35 36  
... ... @@ -48,20 +49,19 @@
48 49 return (msr & 0x2) != 0;
49 50 }
50 51  
51   -#ifdef CONFIG_SYS_INTC_0
  52 +static struct irq_action *vecs;
  53 +static u32 irq_no;
52 54  
53   -static struct irq_action vecs[CONFIG_SYS_INTC_0_NUM];
54   -
55 55 /* mapping structure to interrupt controller */
56   -microblaze_intc_t *intc = (microblaze_intc_t *) (CONFIG_SYS_INTC_0_ADDR);
  56 +microblaze_intc_t *intc;
57 57  
58 58 /* default handler */
59   -void def_hdlr (void)
  59 +static void def_hdlr(void)
60 60 {
61 61 puts ("def_hdlr\n");
62 62 }
63 63  
64   -void enable_one_interrupt (int irq)
  64 +static void enable_one_interrupt(int irq)
65 65 {
66 66 int mask;
67 67 int offset = 1;
... ... @@ -76,7 +76,7 @@
76 76 #endif
77 77 }
78 78  
79   -void disable_one_interrupt (int irq)
  79 +static void disable_one_interrupt(int irq)
80 80 {
81 81 int mask;
82 82 int offset = 1;
... ... @@ -96,7 +96,7 @@
96 96 {
97 97 struct irq_action *act;
98 98 /* irq out of range */
99   - if ((irq < 0) || (irq > CONFIG_SYS_INTC_0_NUM)) {
  99 + if ((irq < 0) || (irq > irq_no)) {
100 100 puts ("IRQ out of range\n");
101 101 return;
102 102 }
... ... @@ -114,7 +114,7 @@
114 114 }
115 115  
116 116 /* initialization interrupt controller - hardware */
117   -void intc_init (void)
  117 +static void intc_init(void)
118 118 {
119 119 intc->mer = 0;
120 120 intc->ier = 0;
121 121  
122 122  
... ... @@ -127,18 +127,33 @@
127 127 #endif
128 128 }
129 129  
130   -int interrupts_init (void)
  130 +int interrupts_init(void)
131 131 {
132 132 int i;
133   - /* initialize irq list */
134   - for (i = 0; i < CONFIG_SYS_INTC_0_NUM; i++) {
135   - vecs[i].handler = (interrupt_handler_t *) def_hdlr;
136   - vecs[i].arg = (void *)i;
137   - vecs[i].count = 0;
  133 +
  134 +#if defined(CONFIG_SYS_INTC_0_ADDR) && defined(CONFIG_SYS_INTC_0_NUM)
  135 + intc = (microblaze_intc_t *) (CONFIG_SYS_INTC_0_ADDR);
  136 + irq_no = CONFIG_SYS_INTC_0_NUM;
  137 +#endif
  138 + if (irq_no) {
  139 + vecs = calloc(1, sizeof(struct irq_action) * irq_no);
  140 + if (vecs == NULL) {
  141 + puts("Interrupt vector allocation failed\n");
  142 + return -1;
  143 + }
  144 +
  145 + /* initialize irq list */
  146 + for (i = 0; i < irq_no; i++) {
  147 + vecs[i].handler = (interrupt_handler_t *) def_hdlr;
  148 + vecs[i].arg = (void *)i;
  149 + vecs[i].count = 0;
  150 + }
  151 + /* initialize intc controller */
  152 + intc_init();
  153 + enable_interrupts();
  154 + } else {
  155 + puts("Undefined interrupt controller\n");
138 156 }
139   - /* initialize intc controller */
140   - intc_init ();
141   - enable_interrupts ();
142 157 return 0;
143 158 }
144 159  
145 160  
146 161  
147 162  
148 163  
149 164  
150 165  
... ... @@ -172,34 +187,31 @@
172 187 printf ("Interrupt handler on %x line, r14 %x\n", irqs, value);
173 188 #endif
174 189 }
175   -#endif
176 190  
177 191 #if defined(CONFIG_CMD_IRQ)
178   -#ifdef CONFIG_SYS_INTC_0
179   -int do_irqinfo (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
  192 +int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, const char *argv[])
180 193 {
181 194 int i;
182 195 struct irq_action *act = vecs;
183 196  
184   - puts ("\nInterrupt-Information:\n\n"
185   - "Nr Routine Arg Count\n"
186   - "-----------------------------\n");
  197 + if (irq_no) {
  198 + puts("\nInterrupt-Information:\n\n"
  199 + "Nr Routine Arg Count\n"
  200 + "-----------------------------\n");
187 201  
188   - for (i = 0; i < CONFIG_SYS_INTC_0_NUM; i++) {
189   - if (act->handler != (interrupt_handler_t*) def_hdlr) {
190   - printf ("%02d %08x %08x %d\n", i,
191   - (int)act->handler, (int)act->arg, act->count);
  202 + for (i = 0; i < irq_no; i++) {
  203 + if (act->handler != (interrupt_handler_t *) def_hdlr) {
  204 + printf("%02d %08x %08x %d\n", i,
  205 + (int)act->handler, (int)act->arg,
  206 + act->count);
  207 + }
  208 + act++;
192 209 }
193   - act++;
  210 + puts("\n");
  211 + } else {
  212 + puts("Undefined interrupt controller\n");
194 213 }
195   - puts ("\n");
196   - return (0);
  214 + return 0;
197 215 }
198   -#else
199   -int do_irqinfo (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
200   -{
201   - puts ("Undefined interrupt controller\n");
202   -}
203   -#endif
204 216 #endif
arch/microblaze/cpu/start.S
Diff comments   View file @ d978780
... ... @@ -108,7 +108,6 @@
108 108 sh r6, r0, r8
109 109 #endif
110 110  
111   -#ifdef CONFIG_SYS_INTC_0
112 111 /* interrupt_handler */
113 112 swi r2, r0, 0x10 /* interrupt - imm opcode */
114 113 swi r3, r0, 0x14 /* interrupt - brai opcode */
... ... @@ -120,7 +119,6 @@
120 119 sh r7, r0, r8
121 120 rsubi r8, r10, 0x16
122 121 sh r6, r0, r8
123   -#endif
124 122  
125 123 /* hardware exception */
126 124 swi r2, r0, 0x20 /* hardware exception - imm opcode */
arch/microblaze/cpu/timer.c
Diff comments   View file @ d978780
... ... @@ -40,8 +40,26 @@
40 40 }
41 41 #endif
42 42  
43   -#ifdef CONFIG_SYS_INTC_0
44 43 #ifdef CONFIG_SYS_TIMER_0
  44 +void __udelay(unsigned long usec)
  45 +{
  46 + int i;
  47 +
  48 + i = get_timer(0);
  49 + while ((get_timer(0) - i) < (usec / 1000))
  50 + ;
  51 +}
  52 +#else
  53 +void __udelay(unsigned long usec)
  54 +{
  55 + unsigned int i;
  56 +
  57 + for (i = 0; i < (usec * CONFIG_XILINX_CLOCK_FREQ / 10000000); i++)
  58 + ;
  59 +}
  60 +#endif
  61 +
  62 +#ifdef CONFIG_SYS_TIMER_0
45 63 microblaze_timer_t *tmr = (microblaze_timer_t *) (CONFIG_SYS_TIMER_0_ADDR);
46 64  
47 65 void timer_isr (void *arg)
... ... @@ -60,7 +78,6 @@
60 78 install_interrupt_handler (CONFIG_SYS_TIMER_0_IRQ, timer_isr, (void *)tmr);
61 79 return 0;
62 80 }
63   -#endif
64 81 #endif
65 82  
66 83 /*
arch/microblaze/cpu/u-boot.lds
Diff comments   View file @ d978780
  1 +/*
  2 + * (C) Copyright 2004 Atmark Techno, Inc.
  3 + *
  4 + * Yasushi SHOJI <yashi@atmark-techno.com>
  5 + *
  6 + * See file CREDITS for list of people who contributed to this
  7 + * project.
  8 + *
  9 + * This program is free software; you can redistribute it and/or
  10 + * modify it under the terms of the GNU General Public License as
  11 + * published by the Free Software Foundation; either version 2 of
  12 + * the License, or (at your option) any later version.
  13 + *
  14 + * This program is distributed in the hope that it will be useful,
  15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 + * GNU General Public License for more details.
  18 + *
  19 + * You should have received a copy of the GNU General Public License
  20 + * along with this program; if not, write to the Free Software
  21 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 + * MA 02111-1307 USA
  23 + */
  24 +
  25 +OUTPUT_ARCH(microblaze)
  26 +ENTRY(_start)
  27 +
  28 +SECTIONS
  29 +{
  30 + .text ALIGN(0x4):
  31 + {
  32 + __text_start = .;
  33 + arch/microblaze/cpu/start.o (.text)
  34 + *(.text)
  35 + __text_end = .;
  36 + }
  37 +
  38 + .rodata ALIGN(0x4):
  39 + {
  40 + __rodata_start = .;
  41 + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
  42 + __rodata_end = .;
  43 + }
  44 +
  45 + .data ALIGN(0x4):
  46 + {
  47 + __data_start = .;
  48 + *(.data)
  49 + __data_end = .;
  50 + }
  51 +
  52 + .u_boot_cmd ALIGN(0x4):
  53 + {
  54 + . = .;
  55 + __u_boot_cmd_start = .;
  56 + *(.u_boot_cmd)
  57 + __u_boot_cmd_end = .;
  58 + }
  59 +
  60 + .bss ALIGN(0x4):
  61 + {
  62 + __bss_start = .;
  63 + *(.sbss)
  64 + *(.scommon)
  65 + *(.bss)
  66 + *(COMMON)
  67 + . = ALIGN(4);
  68 + __bss_end = .;
  69 + }
  70 + __end = . ;
  71 +}
arch/microblaze/include/asm/gpio.h
Diff comments   View file @ d978780
  1 +#ifndef _ASM_MICROBLAZE_GPIO_H_
  2 +#define _ASM_MICROBLAZE_GPIO_H_
  3 +
  4 +#include <asm/io.h>
  5 +
  6 +static inline int gpio_request(unsigned gpio, const char *label)
  7 +{
  8 + return 0;
  9 +}
  10 +
  11 +static inline int gpio_free(unsigned gpio)
  12 +{
  13 + return 0;
  14 +}
  15 +
  16 +static inline int gpio_direction_input(unsigned gpio)
  17 +{
  18 + return 0;
  19 +}
  20 +
  21 +static inline int gpio_direction_output(unsigned gpio, int value)
  22 +{
  23 + return 0;
  24 +}
  25 +
  26 +static inline int gpio_get_value(unsigned gpio)
  27 +{
  28 + return 0;
  29 +}
  30 +
  31 +static inline int gpio_set_value(unsigned gpio, int value)
  32 +{
  33 + return 0;
  34 +}
  35 +
  36 +static inline int gpio_is_valid(int number)
  37 +{
  38 + return 0;
  39 +}
  40 +#endif
arch/microblaze/include/asm/microblaze_intc.h
Diff comments   View file @ d978780
... ... @@ -41,4 +41,6 @@
41 41  
42 42 void install_interrupt_handler (int irq, interrupt_handler_t * hdlr,
43 43 void *arg);
  44 +
  45 +int interrupts_init(void);
arch/microblaze/lib/Makefile
Diff comments   View file @ d978780
... ... @@ -29,7 +29,6 @@
29 29  
30 30 COBJS-y += board.o
31 31 COBJS-y += bootm.o
32   -COBJS-y += time.o
33 32  
34 33 SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
35 34 OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
arch/microblaze/lib/board.c
Diff comments   View file @ d978780
... ... @@ -30,21 +30,16 @@
30 30 #include <version.h>
31 31 #include <watchdog.h>
32 32 #include <stdio_dev.h>
  33 +#include <serial.h>
33 34 #include <net.h>
34 35 #include <asm/processor.h>
  36 +#include <asm/microblaze_intc.h>
35 37  
36 38 DECLARE_GLOBAL_DATA_PTR;
37 39  
38 40 #ifdef CONFIG_SYS_GPIO_0
39 41 extern int gpio_init (void);
40 42 #endif
41   -#ifdef CONFIG_SYS_INTC_0
42   -extern int interrupts_init (void);
43   -#endif
44   -
45   -#if defined(CONFIG_CMD_NET)
46   -extern int eth_init (bd_t * bis);
47   -#endif
48 43 #ifdef CONFIG_SYS_TIMER_0
49 44 extern int timer_init (void);
50 45 #endif
51 46  
... ... @@ -73,9 +68,7 @@
73 68 #ifdef CONFIG_SYS_GPIO_0
74 69 gpio_init,
75 70 #endif
76   -#ifdef CONFIG_SYS_INTC_0
77 71 interrupts_init,
78   -#endif
79 72 #ifdef CONFIG_SYS_TIMER_0
80 73 timer_init,
81 74 #endif
... ... @@ -116,6 +109,10 @@
116 109 * as our monitory code is run from SDRAM
117 110 */
118 111 mem_malloc_init (CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
  112 +
  113 +#ifdef CONFIG_SERIAL_MULTI
  114 + serial_initialize();
  115 +#endif
119 116  
120 117 for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
121 118 WATCHDOG_RESET ();
arch/microblaze/lib/time.c
Diff comments   View file @ d978780
1   -/*
2   - * (C) Copyright 2007 Michal Simek
3   - * (C) Copyright 2004 Atmark Techno, Inc.
4   - *
5   - * Michal SIMEK <monstr@monstr.eu>
6   - * Yasushi SHOJI <yashi@atmark-techno.com>
7   - *
8   - * See file CREDITS for list of people who contributed to this
9   - * project.
10   - *
11   - * This program is free software; you can redistribute it and/or
12   - * modify it under the terms of the GNU General Public License as
13   - * published by the Free Software Foundation; either version 2 of
14   - * the License, or (at your option) any later version.
15   - *
16   - * This program is distributed in the hope that it will be useful,
17   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
18   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19   - * GNU General Public License for more details.
20   - *
21   - * You should have received a copy of the GNU General Public License
22   - * along with this program; if not, write to the Free Software
23   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24   - * MA 02111-1307 USA
25   - */
26   -
27   -#include <common.h>
28   -
29   -#ifdef CONFIG_SYS_TIMER_0
30   -void __udelay (unsigned long usec)
31   -{
32   - int i;
33   - i = get_timer (0);
34   - while ((get_timer (0) - i) < (usec / 1000)) ;
35   -}
36   -#else
37   -void __udelay (unsigned long usec)
38   -{
39   - unsigned int i;
40   - for (i = 0; i < (usec * CONFIG_XILINX_CLOCK_FREQ / 10000000); i++);
41   -}
42   -#endif
board/xilinx/dts/microblaze.dts
Diff comments   View file @ d978780
  1 +/include/ BOARD_DTS
board/xilinx/microblaze-generic/dts/microblaze.dts
Diff comments   View file @ d978780
  1 +/dts-v1/;
  2 +/ {
  3 + #address-cells = <1>;
  4 + #size-cells = <1>;
  5 + aliases {
  6 + } ;
  7 +} ;
board/xilinx/microblaze-generic/u-boot.lds
View file @ d978780
1   -/*
2   - * (C) Copyright 2004 Atmark Techno, Inc.
3   - *
4   - * Yasushi SHOJI <yashi@atmark-techno.com>
5   - *
6   - * See file CREDITS for list of people who contributed to this
7   - * project.
8   - *
9   - * This program is free software; you can redistribute it and/or
10   - * modify it under the terms of the GNU General Public License as
11   - * published by the Free Software Foundation; either version 2 of
12   - * the License, or (at your option) any later version.
13   - *
14   - * This program is distributed in the hope that it will be useful,
15   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
16   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17   - * GNU General Public License for more details.
18   - *
19   - * You should have received a copy of the GNU General Public License
20   - * along with this program; if not, write to the Free Software
21   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22   - * MA 02111-1307 USA
23   - */
24   -
25   -OUTPUT_ARCH(microblaze)
26   -ENTRY(_start)
27   -
28   -SECTIONS
29   -{
30   - .text ALIGN(0x4):
31   - {
32   - __text_start = .;
33   - arch/microblaze/cpu/start.o (.text)
34   - *(.text)
35   - __text_end = .;
36   - }
37   -
38   - .rodata ALIGN(0x4):
39   - {
40   - __rodata_start = .;
41   - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
42   - __rodata_end = .;
43   - }
44   -
45   - .data ALIGN(0x4):
46   - {
47   - __data_start = .;
48   - *(.data)
49   - __data_end = .;
50   - }
51   -
52   - .u_boot_cmd ALIGN(0x4):
53   - {
54   - . = .;
55   - __u_boot_cmd_start = .;
56   - *(.u_boot_cmd)
57   - __u_boot_cmd_end = .;
58   - }
59   -
60   - .bss ALIGN(0x4):
61   - {
62   - __bss_start = .;
63   - *(.sbss)
64   - *(.scommon)
65   - *(.bss)
66   - *(COMMON)
67   - . = ALIGN(4);
68   - __bss_end = .;
69   - }
70   - __end = . ;
71   -}
drivers/spi/Makefile
Diff comments   View file @ d978780
... ... @@ -44,6 +44,8 @@
44 44 COBJS-$(CONFIG_SH_SPI) += sh_spi.o
45 45 COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
46 46 COBJS-$(CONFIG_TEGRA_SPI) += tegra_spi.o
  47 +COBJS-$(CONFIG_TEGRA2_SPI) += tegra2_spi.o
  48 +COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
47 49  
48 50 COBJS := $(COBJS-y)
49 51 SRCS := $(COBJS:.o=.c)
drivers/spi/xilinx_spi.c
Diff comments   View file @ d978780
  1 +/*
  2 + * Xilinx SPI driver
  3 + *
  4 + * supports 8 bit SPI transfers only, with or w/o FIFO
  5 + *
  6 + * based on bfin_spi.c, by way of altera_spi.c
  7 + * Copyright (c) 2005-2008 Analog Devices Inc.
  8 + * Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw>
  9 + * Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca>
  10 + * Copyright (c) 2012 Stephan Linz <linz@li-pro.net>
  11 + *
  12 + * Licensed under the GPL-2 or later.
  13 + *
  14 + * [0]: http://www.xilinx.com/support/documentation
  15 + *
  16 + * [S]: [0]/ip_documentation/xps_spi.pdf
  17 + * [0]/ip_documentation/axi_spi_ds742.pdf
  18 + */
  19 +#include <config.h>
  20 +#include <common.h>
  21 +#include <malloc.h>
  22 +#include <spi.h>
  23 +
  24 +#include "xilinx_spi.h"
  25 +
  26 +#ifndef CONFIG_SYS_XILINX_SPI_LIST
  27 +#define CONFIG_SYS_XILINX_SPI_LIST { CONFIG_SYS_SPI_BASE }
  28 +#endif
  29 +
  30 +#ifndef CONFIG_XILINX_SPI_IDLE_VAL
  31 +#define CONFIG_XILINX_SPI_IDLE_VAL 0xff
  32 +#endif
  33 +
  34 +#define XILSPI_SPICR_DFLT_ON (SPICR_MANUAL_SS | \
  35 + SPICR_MASTER_MODE | \
  36 + SPICR_SPE)
  37 +
  38 +#define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | \
  39 + SPICR_MANUAL_SS)
  40 +
  41 +#define XILSPI_MAX_XFER_BITS 8
  42 +
  43 +static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST;
  44 +
  45 +__attribute__((weak))
  46 +int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  47 +{
  48 + return bus < ARRAY_SIZE(xilinx_spi_base_list) && cs < 32;
  49 +}
  50 +
  51 +__attribute__((weak))
  52 +void spi_cs_activate(struct spi_slave *slave)
  53 +{
  54 + struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
  55 +
  56 + writel(SPISSR_ACT(slave->cs), &xilspi->regs->spissr);
  57 +}
  58 +
  59 +__attribute__((weak))
  60 +void spi_cs_deactivate(struct spi_slave *slave)
  61 +{
  62 + struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
  63 +
  64 + writel(SPISSR_OFF, &xilspi->regs->spissr);
  65 +}
  66 +
  67 +void spi_init(void)
  68 +{
  69 + /* do nothing */
  70 +}
  71 +
  72 +void spi_set_speed(struct spi_slave *slave, uint hz)
  73 +{
  74 + /* xilinx spi core does not support programmable speed */
  75 +}
  76 +
  77 +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
  78 + unsigned int max_hz, unsigned int mode)
  79 +{
  80 + struct xilinx_spi_slave *xilspi;
  81 + struct xilinx_spi_reg *regs;
  82 +
  83 + if (!spi_cs_is_valid(bus, cs)) {
  84 + printf("XILSPI error: %s: unsupported bus %d / cs %d\n",
  85 + __func__, bus, cs);
  86 + return NULL;
  87 + }
  88 +
  89 + xilspi = malloc(sizeof(*xilspi));
  90 + if (!xilspi) {
  91 + printf("XILSPI error: %s: malloc of SPI structure failed\n",
  92 + __func__);
  93 + return NULL;
  94 + }
  95 + xilspi->slave.bus = bus;
  96 + xilspi->slave.cs = cs;
  97 + xilspi->regs = (struct xilinx_spi_reg *)xilinx_spi_base_list[bus];
  98 + xilspi->freq = max_hz;
  99 + xilspi->mode = mode;
  100 + debug("%s: bus:%i cs:%i base:%p mode:%x max_hz:%d\n", __func__,
  101 + bus, cs, xilspi->regs, xilspi->mode, xilspi->freq);
  102 +
  103 + return &xilspi->slave;
  104 +}
  105 +
  106 +void spi_free_slave(struct spi_slave *slave)
  107 +{
  108 + struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
  109 +
  110 + free(xilspi);
  111 +}
  112 +
  113 +int spi_claim_bus(struct spi_slave *slave)
  114 +{
  115 + struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
  116 + u32 spicr;
  117 +
  118 + debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
  119 + writel(SPISSR_OFF, &xilspi->regs->spissr);
  120 +
  121 + spicr = XILSPI_SPICR_DFLT_ON;
  122 + if (xilspi->mode & SPI_LSB_FIRST)
  123 + spicr |= SPICR_LSB_FIRST;
  124 + if (xilspi->mode & SPI_CPHA)
  125 + spicr |= SPICR_CPHA;
  126 + if (xilspi->mode & SPI_CPOL)
  127 + spicr |= SPICR_CPOL;
  128 + if (xilspi->mode & SPI_LOOP)
  129 + spicr |= SPICR_LOOP;
  130 +
  131 + writel(spicr, &xilspi->regs->spicr);
  132 + return 0;
  133 +}
  134 +
  135 +void spi_release_bus(struct spi_slave *slave)
  136 +{
  137 + struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
  138 +
  139 + debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
  140 + writel(SPISSR_OFF, &xilspi->regs->spissr);
  141 + writel(XILSPI_SPICR_DFLT_OFF, &xilspi->regs->spicr);
  142 +}
  143 +
  144 +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
  145 + void *din, unsigned long flags)
  146 +{
  147 + struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
  148 + /* assume spi core configured to do 8 bit transfers */
  149 + unsigned int bytes = bitlen / XILSPI_MAX_XFER_BITS;
  150 + const unsigned char *txp = dout;
  151 + unsigned char *rxp = din;
  152 + unsigned rxecount = 17; /* max. 16 elements in FIFO, leftover 1 */
  153 +
  154 + debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
  155 + slave->bus, slave->cs, bitlen, bytes, flags);
  156 + if (bitlen == 0)
  157 + goto done;
  158 +
  159 + if (bitlen % XILSPI_MAX_XFER_BITS) {
  160 + printf("XILSPI warning: %s: Not a multiple of %d bits\n",
  161 + __func__, XILSPI_MAX_XFER_BITS);
  162 + flags |= SPI_XFER_END;
  163 + goto done;
  164 + }
  165 +
  166 + /* empty read buffer */
  167 + while (rxecount && !(readl(&xilspi->regs->spisr) & SPISR_RX_EMPTY)) {
  168 + readl(&xilspi->regs->spidrr);
  169 + rxecount--;
  170 + }
  171 +
  172 + if (!rxecount) {
  173 + printf("XILSPI error: %s: Rx buffer not empty\n", __func__);
  174 + return -1;
  175 + }
  176 +
  177 + if (flags & SPI_XFER_BEGIN)
  178 + spi_cs_activate(slave);
  179 +
  180 + while (bytes--) {
  181 + unsigned timeout = /* at least 1usec or greater, leftover 1 */
  182 + xilspi->freq > XILSPI_MAX_XFER_BITS * 1000000 ? 2 :
  183 + (XILSPI_MAX_XFER_BITS * 1000000 / xilspi->freq) + 1;
  184 +
  185 + /* get Tx element from data out buffer and count up */
  186 + unsigned char d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
  187 + debug("%s: tx:%x ", __func__, d);
  188 +
  189 + /* write out and wait for processing (receive data) */
  190 + writel(d & SPIDTR_8BIT_MASK, &xilspi->regs->spidtr);
  191 + while (timeout && readl(&xilspi->regs->spisr)
  192 + & SPISR_RX_EMPTY) {
  193 + timeout--;
  194 + udelay(1);
  195 + }
  196 +
  197 + if (!timeout) {
  198 + printf("XILSPI error: %s: Xfer timeout\n", __func__);
  199 + return -1;
  200 + }
  201 +
  202 + /* read Rx element and push into data in buffer */
  203 + d = readl(&xilspi->regs->spidrr) & SPIDRR_8BIT_MASK;
  204 + if (rxp)
  205 + *rxp++ = d;
  206 + debug("rx:%x\n", d);
  207 + }
  208 +
  209 + done:
  210 + if (flags & SPI_XFER_END)
  211 + spi_cs_deactivate(slave);
  212 +
  213 + return 0;
  214 +}
drivers/spi/xilinx_spi.h
Diff comments   View file @ d978780
  1 +/*
  2 + * Xilinx SPI driver
  3 + *
  4 + * XPS/AXI bus interface
  5 + *
  6 + * based on bfin_spi.c, by way of altera_spi.c
  7 + * Copyright (c) 2005-2008 Analog Devices Inc.
  8 + * Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw>
  9 + * Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca>
  10 + * Copyright (c) 2012 Stephan Linz <linz@li-pro.net>
  11 + *
  12 + * Licensed under the GPL-2 or later.
  13 + *
  14 + * [0]: http://www.xilinx.com/support/documentation
  15 + *
  16 + * [S]: [0]/ip_documentation/xps_spi.pdf
  17 + * [0]/ip_documentation/axi_spi_ds742.pdf
  18 + */
  19 +#ifndef _XILINX_SPI_
  20 +#define _XILINX_SPI_
  21 +
  22 +#include <asm/types.h>
  23 +#include <asm/io.h>
  24 +
  25 +/*
  26 + * Xilinx SPI Register Definition
  27 + *
  28 + * [1]: [0]/ip_documentation/xps_spi.pdf
  29 + * page 8, Register Descriptions
  30 + * [2]: [0]/ip_documentation/axi_spi_ds742.pdf
  31 + * page 7, Register Overview Table
  32 + */
  33 +struct xilinx_spi_reg {
  34 + u32 __space0__[7];
  35 + u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */
  36 + u32 ipisr; /* IP Interrupt Status Register (IPISR) */
  37 + u32 __space1__;
  38 + u32 ipier; /* IP Interrupt Enable Register (IPIER) */
  39 + u32 __space2__[5];
  40 + u32 srr; /* Softare Reset Register (SRR) */
  41 + u32 __space3__[7];
  42 + u32 spicr; /* SPI Control Register (SPICR) */
  43 + u32 spisr; /* SPI Status Register (SPISR) */
  44 + u32 spidtr; /* SPI Data Transmit Register (SPIDTR) */
  45 + u32 spidrr; /* SPI Data Receive Register (SPIDRR) */
  46 + u32 spissr; /* SPI Slave Select Register (SPISSR) */
  47 + u32 spitfor; /* SPI Transmit FIFO Occupancy Register (SPITFOR) */
  48 + u32 spirfor; /* SPI Receive FIFO Occupancy Register (SPIRFOR) */
  49 +};
  50 +
  51 +/* Device Global Interrupt Enable Register (dgier), [1] p15, [2] p15 */
  52 +#define DGIER_GIE (1 << 31)
  53 +
  54 +/* IP Interrupt Status Register (ipisr), [1] p15, [2] p15 */
  55 +#define IPISR_DRR_NOT_EMPTY (1 << 8)
  56 +#define IPISR_SLAVE_SELECT (1 << 7)
  57 +#define IPISR_TXF_HALF_EMPTY (1 << 6)
  58 +#define IPISR_DRR_OVERRUN (1 << 5)
  59 +#define IPISR_DRR_FULL (1 << 4)
  60 +#define IPISR_DTR_UNDERRUN (1 << 3)
  61 +#define IPISR_DTR_EMPTY (1 << 2)
  62 +#define IPISR_SLAVE_MODF (1 << 1)
  63 +#define IPISR_MODF (1 << 0)
  64 +
  65 +/* IP Interrupt Enable Register (ipier), [1] p17, [2] p18 */
  66 +#define IPIER_DRR_NOT_EMPTY (1 << 8)
  67 +#define IPIER_SLAVE_SELECT (1 << 7)
  68 +#define IPIER_TXF_HALF_EMPTY (1 << 6)
  69 +#define IPIER_DRR_OVERRUN (1 << 5)
  70 +#define IPIER_DRR_FULL (1 << 4)
  71 +#define IPIER_DTR_UNDERRUN (1 << 3)
  72 +#define IPIER_DTR_EMPTY (1 << 2)
  73 +#define IPIER_SLAVE_MODF (1 << 1)
  74 +#define IPIER_MODF (1 << 0)
  75 +
  76 +/* Softare Reset Register (srr), [1] p9, [2] p8 */
  77 +#define SRR_RESET_CODE 0x0000000A
  78 +
  79 +/* SPI Control Register (spicr), [1] p9, [2] p8 */
  80 +#define SPICR_LSB_FIRST (1 << 9)
  81 +#define SPICR_MASTER_INHIBIT (1 << 8)
  82 +#define SPICR_MANUAL_SS (1 << 7)
  83 +#define SPICR_RXFIFO_RESEST (1 << 6)
  84 +#define SPICR_TXFIFO_RESEST (1 << 5)
  85 +#define SPICR_CPHA (1 << 4)
  86 +#define SPICR_CPOL (1 << 3)
  87 +#define SPICR_MASTER_MODE (1 << 2)
  88 +#define SPICR_SPE (1 << 1)
  89 +#define SPICR_LOOP (1 << 0)
  90 +
  91 +/* SPI Status Register (spisr), [1] p11, [2] p10 */
  92 +#define SPISR_SLAVE_MODE_SELECT (1 << 5)
  93 +#define SPISR_MODF (1 << 4)
  94 +#define SPISR_TX_FULL (1 << 3)
  95 +#define SPISR_TX_EMPTY (1 << 2)
  96 +#define SPISR_RX_FULL (1 << 1)
  97 +#define SPISR_RX_EMPTY (1 << 0)
  98 +
  99 +/* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */
  100 +#define SPIDTR_8BIT_MASK (0xff << 0)
  101 +#define SPIDTR_16BIT_MASK (0xffff << 0)
  102 +#define SPIDTR_32BIT_MASK (0xffffffff << 0)
  103 +
  104 +/* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */
  105 +#define SPIDRR_8BIT_MASK (0xff << 0)
  106 +#define SPIDRR_16BIT_MASK (0xffff << 0)
  107 +#define SPIDRR_32BIT_MASK (0xffffffff << 0)
  108 +
  109 +/* SPI Slave Select Register (spissr), [1] p13, [2] p13 */
  110 +#define SPISSR_MASK(cs) (1 << (cs))
  111 +#define SPISSR_ACT(cs) ~SPISSR_MASK(cs)
  112 +#define SPISSR_OFF ~0UL
  113 +
  114 +/* SPI Transmit FIFO Occupancy Register (spitfor), [1] p13, [2] p14 */
  115 +#define SPITFOR_OCYVAL_POS 0
  116 +#define SPITFOR_OCYVAL_MASK (0xf << SPITFOR_OCYVAL_POS)
  117 +
  118 +/* SPI Receive FIFO Occupancy Register (spirfor), [1] p14, [2] p14 */
  119 +#define SPIRFOR_OCYVAL_POS 0
  120 +#define SPIRFOR_OCYVAL_MASK (0xf << SPIRFOR_OCYVAL_POS)
  121 +
  122 +struct xilinx_spi_slave {
  123 + struct spi_slave slave;
  124 + struct xilinx_spi_reg *regs;
  125 + unsigned int freq;
  126 + unsigned int mode;
  127 +};
  128 +
  129 +static inline struct xilinx_spi_slave *to_xilinx_spi_slave(
  130 + struct spi_slave *slave)
  131 +{
  132 + return container_of(slave, struct xilinx_spi_slave, slave);
  133 +}
  134 +
  135 +#endif /* _XILINX_SPI_ */
... ... @@ -36,7 +36,8 @@
36 36 Please define CONFIG_ARCH_DEVICE_TREE))
37 37  
38 38 # We preprocess the device tree file provide a useful define
39   -DTS_CPPFLAGS := -DARCH_CPU_DTS=\"$(SRCTREE)/arch/$(ARCH)/dts/$(CONFIG_ARCH_DEVICE_TREE).dtsi\"
  39 +DTS_CPPFLAGS := -DARCH_CPU_DTS=\"$(SRCTREE)/arch/$(ARCH)/dts/$(CONFIG_ARCH_DEVICE_TREE).dtsi\" \
  40 + -DBOARD_DTS=\"$(SRCTREE)/board/$(VENDOR)/$(BOARD)/dts/$(DEVICE_TREE).dts\"
40 41  
41 42 all: $(obj).depend $(LIB)
42 43  
include/configs/microblaze-generic.h
Diff comments   View file @ d978780
... ... @@ -31,6 +31,28 @@
31 31 #define CONFIG_MICROBLAZE 1
32 32 #define MICROBLAZE_V5 1
33 33  
  34 +/* Open Firmware DTS */
  35 +#define CONFIG_OF_CONTROL 1
  36 +#define CONFIG_OF_EMBED 1
  37 +#define CONFIG_DEFAULT_DEVICE_TREE microblaze
  38 +
  39 +/* linear and spi flash memory */
  40 +#ifdef XILINX_FLASH_START
  41 +#define FLASH
  42 +#undef SPIFLASH
  43 +#undef RAMENV /* hold environment in flash */
  44 +#else
  45 +#ifdef XILINX_SPI_FLASH_BASEADDR
  46 +#undef FLASH
  47 +#define SPIFLASH
  48 +#undef RAMENV /* hold environment in flash */
  49 +#else
  50 +#undef FLASH
  51 +#undef SPIFLASH
  52 +#define RAMENV /* hold environment in RAM */
  53 +#endif
  54 +#endif
  55 +
34 56 /* uart */
35 57 #ifdef XILINX_UARTLITE_BASEADDR
36 58 # define CONFIG_XILINX_UARTLITE
... ... @@ -88,7 +110,6 @@
88 110  
89 111 /* interrupt controller */
90 112 #ifdef XILINX_INTC_BASEADDR
91   -# define CONFIG_SYS_INTC_0 1
92 113 # define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR
93 114 # define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
94 115 #endif
95 116  
96 117  
97 118  
98 119  
... ... @@ -113,15 +134,19 @@
113 134  
114 135 /*
115 136 * memory layout - Example
116   - * CONFIG_SYS_TEXT_BASE = 0x1200_0000;
  137 + * CONFIG_SYS_TEXT_BASE = 0x1200_0000; defined in config.mk
117 138 * CONFIG_SYS_SRAM_BASE = 0x1000_0000;
118   - * CONFIG_SYS_SRAM_SIZE = 0x0400_0000;
  139 + * CONFIG_SYS_SRAM_SIZE = 0x0400_0000; 64MB
119 140 *
  141 + * CONFIG_SYS_MONITOR_LEN = 0x40000
  142 + * CONFIG_SYS_MALLOC_LEN = 3 * CONFIG_SYS_MONITOR_LEN = 0xC0000
  143 + *
120 144 * CONFIG_SYS_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
121   - * CONFIG_SYS_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000
122   - * CONFIG_SYS_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000
  145 + * CONFIG_SYS_MONITOR_BASE = 0x13FF_F000 - CONFIG_SYS_MONITOR_LEN = 0x13FB_F000
  146 + * CONFIG_SYS_MALLOC_BASE = 0x13FB_F000 - CONFIG_SYS_MALLOC_LEN = 0x13EF_F000
123 147 *
124 148 * 0x1000_0000 CONFIG_SYS_SDRAM_BASE
  149 + * MEMTEST_AREA 64kB
125 150 * FREE
126 151 * 0x1200_0000 CONFIG_SYS_TEXT_BASE
127 152 * U-BOOT code
... ... @@ -129,9 +154,9 @@
129 154 * FREE
130 155 *
131 156 * STACK
132   - * 0x13F7_F000 CONFIG_SYS_MALLOC_BASE
133   - * MALLOC_AREA 256kB Alloc
134   - * 0x11FB_F000 CONFIG_SYS_MONITOR_BASE
  157 + * 0x13EF_F000 CONFIG_SYS_MALLOC_BASE
  158 + * MALLOC_AREA 768kB Alloc
  159 + * 0x13FB_F000 CONFIG_SYS_MONITOR_BASE
135 160 * MONITOR_CODE 256kB Env
136 161 * 0x13FF_F000 CONFIG_SYS_GBL_DATA_OFFSET
137 162 * GLOBAL_DATA 4kB bd, gd
138 163  
... ... @@ -157,15 +182,30 @@
157 182 - CONFIG_SYS_MONITOR_LEN - GENERATED_BD_INFO_SIZE)
158 183 #define CONFIG_SYS_MONITOR_END \
159 184 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
160   -#define CONFIG_SYS_MALLOC_LEN SIZE
  185 +#define CONFIG_SYS_MALLOC_LEN (SIZE * 3)
161 186 #define CONFIG_SYS_MALLOC_BASE \
162 187 (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
163 188  
164 189 /* stack */
165 190 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_MALLOC_BASE
166 191  
167   -/*#define RAMENV */
168   -#define FLASH
  192 +/*
  193 + * CFI flash memory layout - Example
  194 + * CONFIG_SYS_FLASH_BASE = 0x2200_0000;
  195 + * CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB
  196 + *
  197 + * SECT_SIZE = 0x20000; 128kB is one sector
  198 + * CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store
  199 + *
  200 + * 0x2200_0000 CONFIG_SYS_FLASH_BASE
  201 + * FREE 256kB
  202 + * 0x2204_0000 CONFIG_ENV_ADDR
  203 + * ENV_AREA 128kB
  204 + * 0x2206_0000
  205 + * FREE
  206 + * 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
  207 + *
  208 + */
169 209  
170 210 #ifdef FLASH
171 211 # define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START
172 212  
173 213  
174 214  
... ... @@ -186,22 +226,51 @@
186 226 # define CONFIG_ENV_SIZE 0x1000
187 227 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
188 228  
189   -# else /* !RAMENV */
  229 +# else /* FLASH && !RAMENV */
190 230 # define CONFIG_ENV_IS_IN_FLASH 1
191 231 /* 128K(one sector) for env */
192 232 # define CONFIG_ENV_SECT_SIZE 0x20000
193 233 # define CONFIG_ENV_ADDR \
194 234 (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
195 235 # define CONFIG_ENV_SIZE 0x20000
196   -# endif /* !RAMBOOT */
  236 +# endif /* FLASH && !RAMBOOT */
197 237 #else /* !FLASH */
  238 +
  239 +#ifdef SPIFLASH
  240 +# define CONFIG_SYS_NO_FLASH 1
  241 +# define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR
  242 +# define CONFIG_XILINX_SPI 1
  243 +# define CONFIG_SPI 1
  244 +# define CONFIG_SPI_FLASH 1
  245 +# define CONFIG_SPI_FLASH_STMICRO 1
  246 +# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
  247 +# define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ
  248 +# define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS
  249 +
  250 +# ifdef RAMENV
  251 +# define CONFIG_ENV_IS_NOWHERE 1
  252 +# define CONFIG_ENV_SIZE 0x1000
  253 +# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
  254 +
  255 +# else /* SPIFLASH && !RAMENV */
  256 +# define CONFIG_ENV_IS_IN_SPI_FLASH 1
  257 +# define CONFIG_ENV_SPI_MODE SPI_MODE_3
  258 +# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
  259 +# define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
  260 +/* 128K(two sectors) for env */
  261 +# define CONFIG_ENV_SECT_SIZE 0x10000
  262 +# define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE)
  263 +/* Warning: adjust the offset in respect of other flash content and size */
  264 +# define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
  265 +# endif /* SPIFLASH && !RAMBOOT */
  266 +#else /* !SPIFLASH */
  267 +
198 268 /* ENV in RAM */
199 269 # define CONFIG_SYS_NO_FLASH 1
200 270 # define CONFIG_ENV_IS_NOWHERE 1
201 271 # define CONFIG_ENV_SIZE 0x1000
202 272 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
203   -/* hardware flash protection */
204   -# define CONFIG_SYS_FLASH_PROTECTION
  273 +#endif /* !SPIFLASH */
205 274 #endif /* !FLASH */
206 275  
207 276 /* system ace */
208 277  
209 278  
210 279  
211 280  
212 281  
... ... @@ -269,19 +338,47 @@
269 338 # define CONFIG_CMD_FLASH
270 339 # define CONFIG_CMD_IMLS
271 340 # define CONFIG_CMD_JFFS2
  341 +# define CONFIG_CMD_UBI
  342 +# undef CONFIG_CMD_UBIFS
272 343  
273 344 # if !defined(RAMENV)
274 345 # define CONFIG_CMD_SAVEENV
275 346 # define CONFIG_CMD_SAVES
276 347 # endif
  348 +
277 349 #else
  350 +#if defined(SPIFLASH)
  351 +# define CONFIG_CMD_SF
  352 +
  353 +# if !defined(RAMENV)
  354 +# define CONFIG_CMD_SAVEENV
  355 +# define CONFIG_CMD_SAVES
  356 +# endif
  357 +#else
278 358 # undef CONFIG_CMD_IMLS
279 359 # undef CONFIG_CMD_FLASH
280 360 # undef CONFIG_CMD_JFFS2
  361 +# undef CONFIG_CMD_UBI
  362 +# undef CONFIG_CMD_UBIFS
281 363 #endif
  364 +#endif
282 365  
283 366 #if defined(CONFIG_CMD_JFFS2)
284   -/* JFFS2 partitions */
  367 +# define CONFIG_MTD_PARTITIONS
  368 +#endif
  369 +
  370 +#if defined(CONFIG_CMD_UBIFS)
  371 +# define CONFIG_CMD_UBI
  372 +# define CONFIG_LZO
  373 +#endif
  374 +
  375 +#if defined(CONFIG_CMD_UBI)
  376 +# define CONFIG_MTD_PARTITIONS
  377 +# define CONFIG_RBTREE
  378 +#endif
  379 +
  380 +#if defined(CONFIG_MTD_PARTITIONS)
  381 +/* MTD partitions */
285 382 #define CONFIG_CMD_MTDPARTS /* mtdparts command line support */
286 383 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
287 384 #define CONFIG_FLASH_CFI_MTD