Sound: WM8994: Support I2S0 channel

This patch modifies the WM8994 codec to support I2S0 channel in codec slave mode Signed-off-by: Dani Krishna Mohan <krishna.md@samsung.com>

Sound: WM8994: Support I2S0 channel
This patch modifies the WM8994 codec to support I2S0 channel in codec slave mode Signed-off-by: Dani Krishna Mohan <krishna.md@samsung.com>
Dani Krishna Mohan · Tom Rini
1 parent d7884e047d
Showing 4 changed files with 165 additions and 59 deletions Side-by-side Diff
drivers/sound/sound.c
drivers/sound/wm8994.c
drivers/sound/wm8994_registers.h
include/i2s.h
@@ -36,8 +36,7 @@
 	int error = 0;
 	int base;
  
-	node = fdtdec_next_compatible(blob, 0,
-					COMPAT_SAMSUNG_EXYNOS5_SOUND);
+	node = fdt_path_offset(blob, "i2s");
 	if (node <= 0) {
 		debug("EXYNOS_SOUND: No node for sound in device tree\n");
 		return -1;
@@ -80,6 +79,11 @@
 				node, "samsung,i2s-bit-clk-framesize", -1);
 	error |= i2s->bfs;
 	debug("bfs = %d\n", i2s->bfs);
+
+	i2s->id = fdtdec_get_int(blob, node, "samsung,i2s-id", -1);
+	error |= i2s->id;
+	debug("id = %d\n", i2s->id);
+
 	if (error == -1) {
 		debug("fail to get sound i2s node properties\n");
 		return -1;
@@ -92,6 +96,7 @@
 	i2s->channels = I2S_CHANNELS;
 	i2s->rfs = I2S_RFS;
 	i2s->bfs = I2S_BFS;
+	i2s->id = 0;
 #endif
 	return 0;
 }
@@ -130,10 +135,10 @@
 #endif
 	if (!strcmp(codectype, "wm8994")) {
 		/* Check the codec type and initialise the same */
-		ret = wm8994_init(blob, WM8994_AIF2,
-			pi2s_tx->samplingrate,
-			(pi2s_tx->samplingrate * (pi2s_tx->rfs)),
-			pi2s_tx->bitspersample, pi2s_tx->channels);
+		ret = wm8994_init(blob, pi2s_tx->id + 1,
+				pi2s_tx->samplingrate,
+				(pi2s_tx->samplingrate * (pi2s_tx->rfs)),
+				pi2s_tx->bitspersample, pi2s_tx->channels);
 	} else if (!strcmp(codectype, "max98095")) {
 		ret = max98095_init(blob, pi2s_tx->samplingrate,
 				(pi2s_tx->samplingrate * (pi2s_tx->rfs)),
@@ -432,12 +432,12 @@
 	int ret;
  
 	/* AIF(1/0) register adress offset calculated */
-	if (aif)
+	if (aif-1)
 		offset = 4;
 	else
 		offset = 0;
  
-	switch (wm8994->sysclk[aif]) {
+	switch (wm8994->sysclk[aif-1]) {
 	case WM8994_SYSCLK_MCLK1:
 		reg1 |= SEL_MCLK1;
 		rate = wm8994->mclk[0];
@@ -460,7 +460,7 @@
  
 	default:
 		debug("%s: Invalid input clock selection [%d]\n",
-		      __func__, wm8994->sysclk[aif]);
+		      __func__, wm8994->sysclk[aif-1]);
 		return -1;
 	}
  
  
@@ -470,13 +470,18 @@
 		reg1 |= WM8994_AIF1CLK_DIV;
 	}
  
-	wm8994->aifclk[aif] = rate;
+	wm8994->aifclk[aif-1] = rate;
  
 	ret = wm8994_update_bits(WM8994_AIF1_CLOCKING_1 + offset,
 				WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
 				reg1);
  
-	ret |= wm8994_update_bits(WM8994_CLOCKING_1,
+	if (aif == WM8994_AIF1)
+		ret |= wm8994_update_bits(WM8994_CLOCKING_1,
+			WM8994_AIF1DSPCLK_ENA_MASK | WM8994_SYSDSPCLK_ENA_MASK,
+			WM8994_AIF1DSPCLK_ENA | WM8994_SYSDSPCLK_ENA);
+	else if (aif == WM8994_AIF2)
+		ret |= wm8994_update_bits(WM8994_CLOCKING_1,
 			WM8994_SYSCLK_SRC | WM8994_AIF2DSPCLK_ENA_MASK |
 			WM8994_SYSDSPCLK_ENA_MASK, WM8994_SYSCLK_SRC |
 			WM8994_AIF2DSPCLK_ENA | WM8994_SYSDSPCLK_ENA);
@@ -536,7 +541,7 @@
 					break;
 			if (i == ARRAY_SIZE(opclk_divs)) {
 				debug("%s frequency divisor not found\n",
-					__func__);
+				      __func__);
 				return -1;
 			}
 			ret = wm8994_update_bits(WM8994_CLOCKING_2,
@@ -554,7 +559,7 @@
 		return -1;
 	}
  
-	ret |= configure_aif_clock(wm8994, aif_id - 1);
+	ret |= configure_aif_clock(wm8994, aif_id);
  
 	if (ret < 0) {
 		debug("%s: codec register access error\n", __func__);
  
@@ -608,13 +613,46 @@
 }
  
 /*
+ * Initializes Volume for AIF1 to HP path
+ *
+ * @returns -1 for error  and 0 Success.
+ *
+ */
+static int wm8994_init_volume_aif1_dac1(void)
+{
+	int ret = 0;
+
+	/* Unmute AIF1DAC */
+	ret |= wm8994_i2c_write(WM8994_AIF1_DAC_FILTERS_1, 0x0000);
+
+	ret |= wm8994_update_bits(WM8994_DAC1_LEFT_VOLUME,
+			WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK |
+			WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
+
+	ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_VOLUME,
+			WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK |
+			WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
+	/* Head Phone Volume */
+	ret |= wm8994_i2c_write(WM8994_LEFT_OUTPUT_VOLUME, 0x12D);
+	ret |= wm8994_i2c_write(WM8994_RIGHT_OUTPUT_VOLUME, 0x12D);
+
+	if (ret < 0) {
+		debug("%s: codec register access error\n", __func__);
+		return -1;
+	}
+
+	return 0;
+}
+
+/*
  * Intialise wm8994 codec device
  *
  * @param wm8994	wm8994 information
  *
  * @returns -1 for error  and 0 Success.
  */
-static int wm8994_device_init(struct wm8994_priv *wm8994)
+static int wm8994_device_init(struct wm8994_priv *wm8994,
+			      enum en_audio_interface aif_id)
 {
 	const char *devname;
 	unsigned short reg_data;
  
@@ -661,13 +699,30 @@
 	ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1,
 				WM8994_HPOUT1R_ENA_MASK, WM8994_HPOUT1R_ENA);
  
-	/* Power enable for AIF2 and DAC1 */
-	ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_5,
-		WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK |
-		WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK,
-		WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA | WM8994_DAC1L_ENA |
-		WM8994_DAC1R_ENA);
+	if (aif_id == WM8994_AIF1) {
+		ret |= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_2,
+					WM8994_TSHUT_ENA | WM8994_MIXINL_ENA |
+					WM8994_MIXINR_ENA | WM8994_IN2L_ENA |
+					WM8994_IN2R_ENA);
  
+		ret |= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_4,
+					WM8994_ADCL_ENA | WM8994_ADCR_ENA |
+					WM8994_AIF1ADC1R_ENA |
+					WM8994_AIF1ADC1L_ENA);
+
+		/* Power enable for AIF1 and DAC1 */
+		ret |= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_5,
+					WM8994_AIF1DACL_ENA |
+					WM8994_AIF1DACR_ENA |
+					WM8994_DAC1L_ENA | WM8994_DAC1R_ENA);
+	} else if (aif_id == WM8994_AIF2) {
+		/* Power enable for AIF2 and DAC1 */
+		ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_5,
+			WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK |
+			WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK,
+			WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA |
+			WM8994_DAC1L_ENA | WM8994_DAC1R_ENA);
+	}
 	/* Head Phone Initialisation */
 	ret |= wm8994_update_bits(WM8994_ANALOGUE_HP_1,
 		WM8994_HPOUT1L_DLY_MASK | WM8994_HPOUT1R_DLY_MASK,
  
  
  
  
  
@@ -695,35 +750,49 @@
 	ret |= wm8994_update_bits(WM8994_OUTPUT_MIXER_2,
 			WM8994_DAC1R_TO_HPOUT1R_MASK, WM8994_DAC1R_TO_HPOUT1R);
  
-	/* Routing AIF2 to DAC1 */
-	ret |= wm8994_update_bits(WM8994_DAC1_LEFT_MIXER_ROUTING,
-			WM8994_AIF2DACL_TO_DAC1L_MASK,
-			WM8994_AIF2DACL_TO_DAC1L);
+	if (aif_id == WM8994_AIF1) {
+		/* Routing AIF1 to DAC1 */
+		ret |= wm8994_i2c_write(WM8994_DAC1_LEFT_MIXER_ROUTING,
+				WM8994_AIF1DAC1L_TO_DAC1L);
  
-	ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_MIXER_ROUTING,
-			WM8994_AIF2DACR_TO_DAC1R_MASK,
-			WM8994_AIF2DACR_TO_DAC1R);
+		ret |= wm8994_i2c_write(WM8994_DAC1_RIGHT_MIXER_ROUTING,
+					WM8994_AIF1DAC1R_TO_DAC1R);
  
-	 /* GPIO Settings for AIF2 */
-	 /* B CLK */
-	ret |= wm8994_update_bits(WM8994_GPIO_3, WM8994_GPIO_DIR_MASK |
-				WM8994_GPIO_FUNCTION_MASK ,
-				WM8994_GPIO_DIR_OUTPUT |
-				WM8994_GPIO_FUNCTION_I2S_CLK);
+		/* GPIO Settings for AIF1 */
+		ret |=  wm8994_i2c_write(WM8994_GPIO_1, WM8994_GPIO_DIR_OUTPUT
+					 | WM8994_GPIO_FUNCTION_I2S_CLK
+					 | WM8994_GPIO_INPUT_DEBOUNCE);
  
-	/* LR CLK */
-	ret |= wm8994_update_bits(WM8994_GPIO_4, WM8994_GPIO_DIR_MASK |
-				WM8994_GPIO_FUNCTION_MASK,
-				WM8994_GPIO_DIR_OUTPUT |
-				WM8994_GPIO_FUNCTION_I2S_CLK);
+		ret |= wm8994_init_volume_aif1_dac1();
+	} else if (aif_id == WM8994_AIF2) {
+		/* Routing AIF2 to DAC1 */
+		ret |= wm8994_update_bits(WM8994_DAC1_LEFT_MIXER_ROUTING,
+				WM8994_AIF2DACL_TO_DAC1L_MASK,
+				WM8994_AIF2DACL_TO_DAC1L);
  
-	/* DATA */
-	ret |= wm8994_update_bits(WM8994_GPIO_5, WM8994_GPIO_DIR_MASK |
-				WM8994_GPIO_FUNCTION_MASK,
-				WM8994_GPIO_DIR_OUTPUT |
-				WM8994_GPIO_FUNCTION_I2S_CLK);
+		ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_MIXER_ROUTING,
+				WM8994_AIF2DACR_TO_DAC1R_MASK,
+				WM8994_AIF2DACR_TO_DAC1R);
  
-	ret |= wm8994_init_volume_aif2_dac1();
+		/* GPIO Settings for AIF2 */
+		/* B CLK */
+		ret |= wm8994_update_bits(WM8994_GPIO_3, WM8994_GPIO_DIR_MASK |
+					WM8994_GPIO_FUNCTION_MASK ,
+					WM8994_GPIO_DIR_OUTPUT);
+
+		/* LR CLK */
+		ret |= wm8994_update_bits(WM8994_GPIO_4, WM8994_GPIO_DIR_MASK |
+					WM8994_GPIO_FUNCTION_MASK,
+					WM8994_GPIO_DIR_OUTPUT);
+
+		/* DATA */
+		ret |= wm8994_update_bits(WM8994_GPIO_5, WM8994_GPIO_DIR_MASK |
+					WM8994_GPIO_FUNCTION_MASK,
+					WM8994_GPIO_DIR_OUTPUT);
+
+		ret |= wm8994_init_volume_aif2_dac1();
+	}
+
 	if (ret < 0)
 		goto err;
  
@@ -795,7 +864,7 @@
 	return 0;
 }
  
-/*wm8994 Device Initialisation */
+/* WM8994 Device Initialisation */
 int wm8994_init(const void *blob, enum en_audio_interface aif_id,
 			int sampling_rate, int mclk_freq,
 			int bits_per_sample, unsigned int channels)
  
  
  
@@ -813,15 +882,15 @@
 	g_wm8994_i2c_dev_addr = pcodec_info->i2c_dev_addr;
 	wm8994_i2c_init(pcodec_info->i2c_bus);
  
-	if (pcodec_info->codec_type == CODEC_WM_8994)
+	if (pcodec_info->codec_type == CODEC_WM_8994) {
 		g_wm8994_info.type = WM8994;
-	else {
+	} else {
 		debug("%s: Codec id [%d] not defined\n", __func__,
-				pcodec_info->codec_type);
+		      pcodec_info->codec_type);
 		return -1;
 	}
  
-	ret = wm8994_device_init(&g_wm8994_info);
+	ret = wm8994_device_init(&g_wm8994_info, aif_id);
 	if (ret < 0) {
 		debug("%s: wm8994 codec chip init failed\n", __func__);
 		return ret;
@@ -13,6 +13,7 @@
 #define WM8994_SOFTWARE_RESET                   0x00
 #define WM8994_POWER_MANAGEMENT_1               0x01
 #define WM8994_POWER_MANAGEMENT_2               0x02
+#define WM8994_POWER_MANAGEMENT_4		0x04
 #define WM8994_POWER_MANAGEMENT_5               0x05
 #define WM8994_LEFT_OUTPUT_VOLUME               0x1C
 #define WM8994_RIGHT_OUTPUT_VOLUME              0x1D
@@ -38,6 +39,7 @@
 #define WM8994_AIF2_CONTROL_2                   0x311
 #define WM8994_AIF2_MASTER_SLAVE                0x312
 #define WM8994_AIF2_BCLK                        0x313
+#define WM8994_AIF1_DAC_FILTERS_1		0x420
 #define WM8994_AIF2_DAC_LEFT_VOLUME             0x502
 #define WM8994_AIF2_DAC_RIGHT_VOLUME            0x503
 #define WM8994_AIF2_DAC_FILTERS_1               0x520
@@ -45,6 +47,7 @@
 #define WM8994_DAC1_RIGHT_MIXER_ROUTING         0x602
 #define WM8994_DAC1_LEFT_VOLUME                 0x610
 #define WM8994_DAC1_RIGHT_VOLUME                0x611
+#define WM8994_GPIO_1				0x700
 #define WM8994_GPIO_3                           0x702
 #define WM8994_GPIO_4                           0x703
 #define WM8994_GPIO_5                           0x704
  
@@ -82,7 +85,21 @@
 /* OPCLK_ENA */
 #define WM8994_OPCLK_ENA                        0x0800
  
+#define WM8994_TSHUT_ENA			0x4000
+#define WM8994_MIXINL_ENA			0x0200
+#define WM8994_MIXINR_ENA			0x0100
+#define WM8994_IN2L_ENA				0x0080
+#define WM8994_IN2R_ENA				0x0020
+
 /*
+ * R5 (0x04) - Power Management (4)
+ */
+#define WM8994_ADCL_ENA				0x0001
+#define WM8994_ADCR_ENA				0x0002
+#define WM8994_AIF1ADC1R_ENA			0x0100
+#define WM8994_AIF1ADC1L_ENA			0x0200
+
+/*
  * R5 (0x05) - Power Management (5)
  */
 /* AIF2DACL_ENA */
@@ -91,6 +108,12 @@
 /* AIF2DACR_ENA */
 #define WM8994_AIF2DACR_ENA                     0x1000
 #define WM8994_AIF2DACR_ENA_MASK                0x1000
+/* AIF1DACL_ENA */
+#define WM8994_AIF1DACL_ENA			0x0200
+#define WM8994_AIF1DACL_ENA_MASK		0x0200
+/* AIF1DACR_ENA */
+#define WM8994_AIF1DACR_ENA			0x0100
+#define WM8994_AIF1DACR_ENA_MASK		0x0100
 /* DAC1L_ENA */
 #define WM8994_DAC1L_ENA                        0x0002
 #define WM8994_DAC1L_ENA_MASK                   0x0002
@@ -170,6 +193,9 @@
 /*
  * R520 (0x208) - Clocking (1)
  */
+/* AIF1DSPCLK_ENA */
+#define WM8994_AIF1DSPCLK_ENA			0x0008
+#define WM8994_AIF1DSPCLK_ENA_MASK		0x0008
 /* AIF2DSPCLK_ENA */
 #define WM8994_AIF2DSPCLK_ENA                   0x0004
 #define WM8994_AIF2DSPCLK_ENA_MASK              0x0004
@@ -254,6 +280,8 @@
 /* AIF2DACL_TO_DAC1L */
 #define WM8994_AIF2DACL_TO_DAC1L                0x0004
 #define WM8994_AIF2DACL_TO_DAC1L_MASK           0x0004
+/* AIF1DAC1L_TO_DAC1L */
+#define WM8994_AIF1DAC1L_TO_DAC1L		0x0001
  
 /*
  * R1538 (0x602) - DAC1 Right Mixer Routing
@@ -261,6 +289,8 @@
 /* AIF2DACR_TO_DAC1R */
 #define WM8994_AIF2DACR_TO_DAC1R                0x0004
 #define WM8994_AIF2DACR_TO_DAC1R_MASK           0x0004
+/* AIF1DAC1R_TO_DAC1R */
+#define WM8994_AIF1DAC1R_TO_DAC1R		0x0001
  
 /*
  * R1552 (0x610) - DAC1 Left Volume
  
  
  
@@ -285,12 +315,13 @@
  *  GPIO
  */
 /* OUTPUT PIN */
-#define WM8994_GPIO_DIR_OUTPUT                   0x8000
+#define WM8994_GPIO_DIR_OUTPUT			0x8000
 /* GPIO PIN MASK */
-#define WM8994_GPIO_DIR_MASK                     0xFFE0
+#define WM8994_GPIO_DIR_MASK			0xFFE0
 /* I2S CLK */
-#define WM8994_GPIO_FUNCTION_I2S_CLK             0x0000
+#define WM8994_GPIO_FUNCTION_I2S_CLK		0x0001
+#define WM8994_GPIO_INPUT_DEBOUNCE		0x0100
 /* GPn FN */
-#define WM8994_GPIO_FUNCTION_MASK                0x001F
+#define WM8994_GPIO_FUNCTION_MASK		0x001F
 #endif
@@ -85,6 +85,7 @@
 	unsigned int bitspersample;	/* bits per sample */
 	unsigned int channels;		/* audio channels */
 	unsigned int base_address;	/* I2S Register Base */
+	unsigned int id;		/* I2S controller id */
 };
  
 /*
...	...	@@ -36,8 +36,7 @@
36	36	int error = 0;
37	37	int base;
38	38
39		- node = fdtdec_next_compatible(blob, 0,
40		- COMPAT_SAMSUNG_EXYNOS5_SOUND);
	39	+ node = fdt_path_offset(blob, "i2s");
41	40	if (node <= 0) {
42	41	debug("EXYNOS_SOUND: No node for sound in device tree\n");
43	42	return -1;
...	...	@@ -80,6 +79,11 @@
80	79	node, "samsung,i2s-bit-clk-framesize", -1);
81	80	error \|= i2s->bfs;
82	81	debug("bfs = %d\n", i2s->bfs);
	82	+
	83	+ i2s->id = fdtdec_get_int(blob, node, "samsung,i2s-id", -1);
	84	+ error \|= i2s->id;
	85	+ debug("id = %d\n", i2s->id);
	86	+
83	87	if (error == -1) {
84	88	debug("fail to get sound i2s node properties\n");
85	89	return -1;
...	...	@@ -92,6 +96,7 @@
92	96	i2s->channels = I2S_CHANNELS;
93	97	i2s->rfs = I2S_RFS;
94	98	i2s->bfs = I2S_BFS;
	99	+ i2s->id = 0;
95	100	#endif
96	101	return 0;
97	102	}
...	...	@@ -130,10 +135,10 @@
130	135	#endif
131	136	if (!strcmp(codectype, "wm8994")) {
132	137	/* Check the codec type and initialise the same */
133		- ret = wm8994_init(blob, WM8994_AIF2,
134		- pi2s_tx->samplingrate,
135		- (pi2s_tx->samplingrate * (pi2s_tx->rfs)),
136		- pi2s_tx->bitspersample, pi2s_tx->channels);
	138	+ ret = wm8994_init(blob, pi2s_tx->id + 1,
	139	+ pi2s_tx->samplingrate,
	140	+ (pi2s_tx->samplingrate * (pi2s_tx->rfs)),
	141	+ pi2s_tx->bitspersample, pi2s_tx->channels);
137	142	} else if (!strcmp(codectype, "max98095")) {
138	143	ret = max98095_init(blob, pi2s_tx->samplingrate,
139	144	(pi2s_tx->samplingrate * (pi2s_tx->rfs)),
...	...	@@ -432,12 +432,12 @@
432	432	int ret;
433	433
434	434	/* AIF(1/0) register adress offset calculated */
435		- if (aif)
	435	+ if (aif-1)
436	436	offset = 4;
437	437	else
438	438	offset = 0;
439	439
440		- switch (wm8994->sysclk[aif]) {
	440	+ switch (wm8994->sysclk[aif-1]) {
441	441	case WM8994_SYSCLK_MCLK1:
442	442	reg1 \|= SEL_MCLK1;
443	443	rate = wm8994->mclk[0];
...	...	@@ -460,7 +460,7 @@
460	460
461	461	default:
462	462	debug("%s: Invalid input clock selection [%d]\n",
463		- __func__, wm8994->sysclk[aif]);
	463	+ __func__, wm8994->sysclk[aif-1]);
464	464	return -1;
465	465	}
466	466
467	467
...	...	@@ -470,13 +470,18 @@
470	470	reg1 \|= WM8994_AIF1CLK_DIV;
471	471	}
472	472
473		- wm8994->aifclk[aif] = rate;
	473	+ wm8994->aifclk[aif-1] = rate;
474	474
475	475	ret = wm8994_update_bits(WM8994_AIF1_CLOCKING_1 + offset,
476	476	WM8994_AIF1CLK_SRC_MASK \| WM8994_AIF1CLK_DIV,
477	477	reg1);
478	478
479		- ret \|= wm8994_update_bits(WM8994_CLOCKING_1,
	479	+ if (aif == WM8994_AIF1)
	480	+ ret \|= wm8994_update_bits(WM8994_CLOCKING_1,
	481	+ WM8994_AIF1DSPCLK_ENA_MASK \| WM8994_SYSDSPCLK_ENA_MASK,
	482	+ WM8994_AIF1DSPCLK_ENA \| WM8994_SYSDSPCLK_ENA);
	483	+ else if (aif == WM8994_AIF2)
	484	+ ret \|= wm8994_update_bits(WM8994_CLOCKING_1,
480	485	WM8994_SYSCLK_SRC \| WM8994_AIF2DSPCLK_ENA_MASK \|
481	486	WM8994_SYSDSPCLK_ENA_MASK, WM8994_SYSCLK_SRC \|
482	487	WM8994_AIF2DSPCLK_ENA \| WM8994_SYSDSPCLK_ENA);
...	...	@@ -536,7 +541,7 @@
536	541	break;
537	542	if (i == ARRAY_SIZE(opclk_divs)) {
538	543	debug("%s frequency divisor not found\n",
539		- __func__);
	544	+ __func__);
540	545	return -1;
541	546	}
542	547	ret = wm8994_update_bits(WM8994_CLOCKING_2,
...	...	@@ -554,7 +559,7 @@
554	559	return -1;
555	560	}
556	561
557		- ret \|= configure_aif_clock(wm8994, aif_id - 1);
	562	+ ret \|= configure_aif_clock(wm8994, aif_id);
558	563
559	564	if (ret < 0) {
560	565	debug("%s: codec register access error\n", __func__);
561	566
...	...	@@ -608,13 +613,46 @@
608	613	}
609	614
610	615	/*
	616	+ * Initializes Volume for AIF1 to HP path
	617	+ *
	618	+ * @returns -1 for error and 0 Success.
	619	+ *
	620	+ */
	621	+static int wm8994_init_volume_aif1_dac1(void)
	622	+{
	623	+ int ret = 0;
	624	+
	625	+ /* Unmute AIF1DAC */
	626	+ ret \|= wm8994_i2c_write(WM8994_AIF1_DAC_FILTERS_1, 0x0000);
	627	+
	628	+ ret \|= wm8994_update_bits(WM8994_DAC1_LEFT_VOLUME,
	629	+ WM8994_DAC1_VU_MASK \| WM8994_DAC1L_VOL_MASK \|
	630	+ WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU \| 0xc0);
	631	+
	632	+ ret \|= wm8994_update_bits(WM8994_DAC1_RIGHT_VOLUME,
	633	+ WM8994_DAC1_VU_MASK \| WM8994_DAC1R_VOL_MASK \|
	634	+ WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU \| 0xc0);
	635	+ /* Head Phone Volume */
	636	+ ret \|= wm8994_i2c_write(WM8994_LEFT_OUTPUT_VOLUME, 0x12D);
	637	+ ret \|= wm8994_i2c_write(WM8994_RIGHT_OUTPUT_VOLUME, 0x12D);
	638	+
	639	+ if (ret < 0) {
	640	+ debug("%s: codec register access error\n", __func__);
	641	+ return -1;
	642	+ }
	643	+
	644	+ return 0;
	645	+}
	646	+
	647	+/*
611	648	* Intialise wm8994 codec device
612	649	*
613	650	* @param wm8994 wm8994 information
614	651	*
615	652	* @returns -1 for error and 0 Success.
616	653	*/
617		-static int wm8994_device_init(struct wm8994_priv *wm8994)
	654	+static int wm8994_device_init(struct wm8994_priv *wm8994,
	655	+ enum en_audio_interface aif_id)
618	656	{
619	657	const char *devname;
620	658	unsigned short reg_data;
621	659
...	...	@@ -661,13 +699,30 @@
661	699	ret \|= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1,
662	700	WM8994_HPOUT1R_ENA_MASK, WM8994_HPOUT1R_ENA);
663	701
664		- /* Power enable for AIF2 and DAC1 */
665		- ret \|= wm8994_update_bits(WM8994_POWER_MANAGEMENT_5,
666		- WM8994_AIF2DACL_ENA_MASK \| WM8994_AIF2DACR_ENA_MASK \|
667		- WM8994_DAC1L_ENA_MASK \| WM8994_DAC1R_ENA_MASK,
668		- WM8994_AIF2DACL_ENA \| WM8994_AIF2DACR_ENA \| WM8994_DAC1L_ENA \|
669		- WM8994_DAC1R_ENA);
	702	+ if (aif_id == WM8994_AIF1) {
	703	+ ret \|= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_2,
	704	+ WM8994_TSHUT_ENA \| WM8994_MIXINL_ENA \|
	705	+ WM8994_MIXINR_ENA \| WM8994_IN2L_ENA \|
	706	+ WM8994_IN2R_ENA);
670	707
	708	+ ret \|= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_4,
	709	+ WM8994_ADCL_ENA \| WM8994_ADCR_ENA \|
	710	+ WM8994_AIF1ADC1R_ENA \|
	711	+ WM8994_AIF1ADC1L_ENA);
	712	+
	713	+ /* Power enable for AIF1 and DAC1 */
	714	+ ret \|= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_5,
	715	+ WM8994_AIF1DACL_ENA \|
	716	+ WM8994_AIF1DACR_ENA \|
	717	+ WM8994_DAC1L_ENA \| WM8994_DAC1R_ENA);
	718	+ } else if (aif_id == WM8994_AIF2) {
	719	+ /* Power enable for AIF2 and DAC1 */
	720	+ ret \|= wm8994_update_bits(WM8994_POWER_MANAGEMENT_5,
	721	+ WM8994_AIF2DACL_ENA_MASK \| WM8994_AIF2DACR_ENA_MASK \|
	722	+ WM8994_DAC1L_ENA_MASK \| WM8994_DAC1R_ENA_MASK,
	723	+ WM8994_AIF2DACL_ENA \| WM8994_AIF2DACR_ENA \|
	724	+ WM8994_DAC1L_ENA \| WM8994_DAC1R_ENA);
	725	+ }
671	726	/* Head Phone Initialisation */
672	727	ret \|= wm8994_update_bits(WM8994_ANALOGUE_HP_1,
673	728	WM8994_HPOUT1L_DLY_MASK \| WM8994_HPOUT1R_DLY_MASK,
674	729
675	730
676	731
677	732
678	733
...	...	@@ -695,35 +750,49 @@
695	750	ret \|= wm8994_update_bits(WM8994_OUTPUT_MIXER_2,
696	751	WM8994_DAC1R_TO_HPOUT1R_MASK, WM8994_DAC1R_TO_HPOUT1R);
697	752
698		- /* Routing AIF2 to DAC1 */
699		- ret \|= wm8994_update_bits(WM8994_DAC1_LEFT_MIXER_ROUTING,
700		- WM8994_AIF2DACL_TO_DAC1L_MASK,
701		- WM8994_AIF2DACL_TO_DAC1L);
	753	+ if (aif_id == WM8994_AIF1) {
	754	+ /* Routing AIF1 to DAC1 */
	755	+ ret \|= wm8994_i2c_write(WM8994_DAC1_LEFT_MIXER_ROUTING,
	756	+ WM8994_AIF1DAC1L_TO_DAC1L);
702	757
703		- ret \|= wm8994_update_bits(WM8994_DAC1_RIGHT_MIXER_ROUTING,
704		- WM8994_AIF2DACR_TO_DAC1R_MASK,
705		- WM8994_AIF2DACR_TO_DAC1R);
	758	+ ret \|= wm8994_i2c_write(WM8994_DAC1_RIGHT_MIXER_ROUTING,
	759	+ WM8994_AIF1DAC1R_TO_DAC1R);
706	760
707		- /* GPIO Settings for AIF2 */
708		- /* B CLK */
709		- ret \|= wm8994_update_bits(WM8994_GPIO_3, WM8994_GPIO_DIR_MASK \|
710		- WM8994_GPIO_FUNCTION_MASK ,
711		- WM8994_GPIO_DIR_OUTPUT \|
712		- WM8994_GPIO_FUNCTION_I2S_CLK);
	761	+ /* GPIO Settings for AIF1 */
	762	+ ret \|= wm8994_i2c_write(WM8994_GPIO_1, WM8994_GPIO_DIR_OUTPUT
	763	+ \| WM8994_GPIO_FUNCTION_I2S_CLK
	764	+ \| WM8994_GPIO_INPUT_DEBOUNCE);
713	765
714		- /* LR CLK */
715		- ret \|= wm8994_update_bits(WM8994_GPIO_4, WM8994_GPIO_DIR_MASK \|
716		- WM8994_GPIO_FUNCTION_MASK,
717		- WM8994_GPIO_DIR_OUTPUT \|
718		- WM8994_GPIO_FUNCTION_I2S_CLK);
	766	+ ret \|= wm8994_init_volume_aif1_dac1();
	767	+ } else if (aif_id == WM8994_AIF2) {
	768	+ /* Routing AIF2 to DAC1 */
	769	+ ret \|= wm8994_update_bits(WM8994_DAC1_LEFT_MIXER_ROUTING,
	770	+ WM8994_AIF2DACL_TO_DAC1L_MASK,
	771	+ WM8994_AIF2DACL_TO_DAC1L);
719	772
720		- /* DATA */
721		- ret \|= wm8994_update_bits(WM8994_GPIO_5, WM8994_GPIO_DIR_MASK \|
722		- WM8994_GPIO_FUNCTION_MASK,
723		- WM8994_GPIO_DIR_OUTPUT \|
724		- WM8994_GPIO_FUNCTION_I2S_CLK);
	773	+ ret \|= wm8994_update_bits(WM8994_DAC1_RIGHT_MIXER_ROUTING,
	774	+ WM8994_AIF2DACR_TO_DAC1R_MASK,
	775	+ WM8994_AIF2DACR_TO_DAC1R);
725	776
726		- ret \|= wm8994_init_volume_aif2_dac1();
	777	+ /* GPIO Settings for AIF2 */
	778	+ /* B CLK */
	779	+ ret \|= wm8994_update_bits(WM8994_GPIO_3, WM8994_GPIO_DIR_MASK \|
	780	+ WM8994_GPIO_FUNCTION_MASK ,
	781	+ WM8994_GPIO_DIR_OUTPUT);
	782	+
	783	+ /* LR CLK */
	784	+ ret \|= wm8994_update_bits(WM8994_GPIO_4, WM8994_GPIO_DIR_MASK \|
	785	+ WM8994_GPIO_FUNCTION_MASK,
	786	+ WM8994_GPIO_DIR_OUTPUT);
	787	+
	788	+ /* DATA */
	789	+ ret \|= wm8994_update_bits(WM8994_GPIO_5, WM8994_GPIO_DIR_MASK \|
	790	+ WM8994_GPIO_FUNCTION_MASK,
	791	+ WM8994_GPIO_DIR_OUTPUT);
	792	+
	793	+ ret \|= wm8994_init_volume_aif2_dac1();
	794	+ }
	795	+
727	796	if (ret < 0)
728	797	goto err;
729	798
...	...	@@ -795,7 +864,7 @@
795	864	return 0;
796	865	}
797	866
798		-/wm8994 Device Initialisation /
	867	+/* WM8994 Device Initialisation */
799	868	int wm8994_init(const void *blob, enum en_audio_interface aif_id,
800	869	int sampling_rate, int mclk_freq,
801	870	int bits_per_sample, unsigned int channels)
802	871
803	872
804	873
...	...	@@ -813,15 +882,15 @@
813	882	g_wm8994_i2c_dev_addr = pcodec_info->i2c_dev_addr;
814	883	wm8994_i2c_init(pcodec_info->i2c_bus);
815	884
816		- if (pcodec_info->codec_type == CODEC_WM_8994)
	885	+ if (pcodec_info->codec_type == CODEC_WM_8994) {
817	886	g_wm8994_info.type = WM8994;
818		- else {
	887	+ } else {
819	888	debug("%s: Codec id [%d] not defined\n", __func__,
820		- pcodec_info->codec_type);
	889	+ pcodec_info->codec_type);
821	890	return -1;
822	891	}
823	892
824		- ret = wm8994_device_init(&g_wm8994_info);
	893	+ ret = wm8994_device_init(&g_wm8994_info, aif_id);
825	894	if (ret < 0) {
826	895	debug("%s: wm8994 codec chip init failed\n", __func__);
827	896	return ret;
...	...	@@ -13,6 +13,7 @@
13	13	#define WM8994_SOFTWARE_RESET 0x00
14	14	#define WM8994_POWER_MANAGEMENT_1 0x01
15	15	#define WM8994_POWER_MANAGEMENT_2 0x02
	16	+#define WM8994_POWER_MANAGEMENT_4 0x04
16	17	#define WM8994_POWER_MANAGEMENT_5 0x05
17	18	#define WM8994_LEFT_OUTPUT_VOLUME 0x1C
18	19	#define WM8994_RIGHT_OUTPUT_VOLUME 0x1D
...	...	@@ -38,6 +39,7 @@
38	39	#define WM8994_AIF2_CONTROL_2 0x311
39	40	#define WM8994_AIF2_MASTER_SLAVE 0x312
40	41	#define WM8994_AIF2_BCLK 0x313
	42	+#define WM8994_AIF1_DAC_FILTERS_1 0x420
41	43	#define WM8994_AIF2_DAC_LEFT_VOLUME 0x502
42	44	#define WM8994_AIF2_DAC_RIGHT_VOLUME 0x503
43	45	#define WM8994_AIF2_DAC_FILTERS_1 0x520
...	...	@@ -45,6 +47,7 @@
45	47	#define WM8994_DAC1_RIGHT_MIXER_ROUTING 0x602
46	48	#define WM8994_DAC1_LEFT_VOLUME 0x610
47	49	#define WM8994_DAC1_RIGHT_VOLUME 0x611
	50	+#define WM8994_GPIO_1 0x700
48	51	#define WM8994_GPIO_3 0x702
49	52	#define WM8994_GPIO_4 0x703
50	53	#define WM8994_GPIO_5 0x704
51	54
...	...	@@ -82,7 +85,21 @@
82	85	/* OPCLK_ENA */
83	86	#define WM8994_OPCLK_ENA 0x0800
84	87
	88	+#define WM8994_TSHUT_ENA 0x4000
	89	+#define WM8994_MIXINL_ENA 0x0200
	90	+#define WM8994_MIXINR_ENA 0x0100
	91	+#define WM8994_IN2L_ENA 0x0080
	92	+#define WM8994_IN2R_ENA 0x0020
	93	+
85	94	/*
	95	+ * R5 (0x04) - Power Management (4)
	96	+ */
	97	+#define WM8994_ADCL_ENA 0x0001
	98	+#define WM8994_ADCR_ENA 0x0002
	99	+#define WM8994_AIF1ADC1R_ENA 0x0100
	100	+#define WM8994_AIF1ADC1L_ENA 0x0200
	101	+
	102	+/*
86	103	* R5 (0x05) - Power Management (5)
87	104	*/
88	105	/* AIF2DACL_ENA */
...	...	@@ -91,6 +108,12 @@
91	108	/* AIF2DACR_ENA */
92	109	#define WM8994_AIF2DACR_ENA 0x1000
93	110	#define WM8994_AIF2DACR_ENA_MASK 0x1000
	111	+/* AIF1DACL_ENA */
	112	+#define WM8994_AIF1DACL_ENA 0x0200
	113	+#define WM8994_AIF1DACL_ENA_MASK 0x0200
	114	+/* AIF1DACR_ENA */
	115	+#define WM8994_AIF1DACR_ENA 0x0100
	116	+#define WM8994_AIF1DACR_ENA_MASK 0x0100
94	117	/* DAC1L_ENA */
95	118	#define WM8994_DAC1L_ENA 0x0002
96	119	#define WM8994_DAC1L_ENA_MASK 0x0002
...	...	@@ -170,6 +193,9 @@
170	193	/*
171	194	* R520 (0x208) - Clocking (1)
172	195	*/
	196	+/* AIF1DSPCLK_ENA */
	197	+#define WM8994_AIF1DSPCLK_ENA 0x0008
	198	+#define WM8994_AIF1DSPCLK_ENA_MASK 0x0008
173	199	/* AIF2DSPCLK_ENA */
174	200	#define WM8994_AIF2DSPCLK_ENA 0x0004
175	201	#define WM8994_AIF2DSPCLK_ENA_MASK 0x0004
...	...	@@ -254,6 +280,8 @@
254	280	/* AIF2DACL_TO_DAC1L */
255	281	#define WM8994_AIF2DACL_TO_DAC1L 0x0004
256	282	#define WM8994_AIF2DACL_TO_DAC1L_MASK 0x0004
	283	+/* AIF1DAC1L_TO_DAC1L */
	284	+#define WM8994_AIF1DAC1L_TO_DAC1L 0x0001
257	285
258	286	/*
259	287	* R1538 (0x602) - DAC1 Right Mixer Routing
...	...	@@ -261,6 +289,8 @@
261	289	/* AIF2DACR_TO_DAC1R */
262	290	#define WM8994_AIF2DACR_TO_DAC1R 0x0004
263	291	#define WM8994_AIF2DACR_TO_DAC1R_MASK 0x0004
	292	+/* AIF1DAC1R_TO_DAC1R */
	293	+#define WM8994_AIF1DAC1R_TO_DAC1R 0x0001
264	294
265	295	/*
266	296	* R1552 (0x610) - DAC1 Left Volume
267	297
268	298
269	299
...	...	@@ -285,12 +315,13 @@
285	315	* GPIO
286	316	*/
287	317	/* OUTPUT PIN */
288		-#define WM8994_GPIO_DIR_OUTPUT 0x8000
	318	+#define WM8994_GPIO_DIR_OUTPUT 0x8000
289	319	/* GPIO PIN MASK */
290		-#define WM8994_GPIO_DIR_MASK 0xFFE0
	320	+#define WM8994_GPIO_DIR_MASK 0xFFE0
291	321	/* I2S CLK */
292		-#define WM8994_GPIO_FUNCTION_I2S_CLK 0x0000
	322	+#define WM8994_GPIO_FUNCTION_I2S_CLK 0x0001
	323	+#define WM8994_GPIO_INPUT_DEBOUNCE 0x0100
293	324	/* GPn FN */
294		-#define WM8994_GPIO_FUNCTION_MASK 0x001F
	325	+#define WM8994_GPIO_FUNCTION_MASK 0x001F
295	326	#endif
...	...	@@ -85,6 +85,7 @@
85	85	unsigned int bitspersample; /* bits per sample */
86	86	unsigned int channels; /* audio channels */
87	87	unsigned int base_address; /* I2S Register Base */
	88	+ unsigned int id; /* I2S controller id */
88	89	};
89	90
90	91	/*