Commit d99e0508213d3f5ca0140a43cf224d364d702266
1 parent
65fb55b421
Exists in
smarc_8mq_lf_v2020.04
and in
4 other branches
MLK-20784-2 imx8mm: Load fuse for TMU TCALIV and TASR
On iMX8MM, the default value of TMU registers TCALIV and TASR need be loaded from fuse. HW won't do this, it expect SW loads them before using TMU. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit 9dada8a697b1c103fdb28f528f168da7ecc20849) (cherry picked from commit 082e16654b7c5542ad23f80d126257df50f65054)
Showing 1 changed file with 25 additions and 1 deletions Side-by-side Diff
arch/arm/mach-imx/imx8m/soc.c
| 1 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | 2 | /* |
| 3 | - * Copyright 2017 NXP | |
| 3 | + * Copyright 2017-2019 NXP | |
| 4 | 4 | * |
| 5 | 5 | * Peng Fan <peng.fan@nxp.com> |
| 6 | 6 | */ |
| ... | ... | @@ -552,5 +552,29 @@ |
| 552 | 552 | return -EPERM; |
| 553 | 553 | |
| 554 | 554 | return 0; |
| 555 | +} | |
| 556 | + | |
| 557 | +void nxp_tmu_arch_init(void *reg_base) | |
| 558 | +{ | |
| 559 | + if (is_imx8mm()) { | |
| 560 | + /* Load TCALIV and TASR from fuses */ | |
| 561 | + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; | |
| 562 | + struct fuse_bank *bank = &ocotp->bank[3]; | |
| 563 | + struct fuse_bank3_regs *fuse = | |
| 564 | + (struct fuse_bank3_regs *)bank->fuse_regs; | |
| 565 | + | |
| 566 | + u32 tca_rt, tca_hr, tca_en; | |
| 567 | + u32 buf_vref, buf_slope; | |
| 568 | + | |
| 569 | + tca_rt = fuse->ana0 & 0xFF; | |
| 570 | + tca_hr = (fuse->ana0 & 0xFF00) >> 8; | |
| 571 | + tca_en = (fuse->ana0 & 0x2000000) >> 25; | |
| 572 | + | |
| 573 | + buf_vref = (fuse->ana0 & 0x1F00000) >> 20; | |
| 574 | + buf_slope = (fuse->ana0 & 0xF0000) >> 16; | |
| 575 | + | |
| 576 | + writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28); | |
| 577 | + writel((tca_en << 31) |(tca_hr <<16) | tca_rt, (ulong)reg_base + 0x30); | |
| 578 | + } | |
| 555 | 579 | } |