Eric Lee / smarc-uboot

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Commit d9f2f5008c32c8373d68a4c8e14f50a469965a23

Authored by Stefan Roese
2 parents e190290ba4 be360d9824
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Merge with /git/u-boot.git

Showing 63 changed files Side-by-side Diff

... ... @@ -5,6 +5,32 @@
5 5 * Fix external IRQ configuration on Yellowstone & Yosemite
6 6 Patch by Stefan Roese, 28 Oct 2005
7 7  
  8 +* Add support for multiple PHYs.
  9 + Tested on the following boards:
  10 + cmcpu2 (at91rm9200/ether.c)
  11 + PPChameleon (ppc4xx/4xx_enet.c)
  12 + yukon (mpc8220/fec.c)
  13 + uc100 (mpc8xx/fec.c)
  14 + tqm834x (mpc834x/tsec.c) with EEPRO100
  15 + lite5200 (mpc5xxx/fec.c) with EEPRO100 card (drivers/eepro100.c)
  16 + Main changes include:
  17 + common/miiphyutil.c
  18 + - miiphy_register routine was added to allow multiple PHYs to be registered
  19 + - miiphy_read and miiphy_write are now defined in this file, and
  20 + require additional argument (char *devname)
  21 + - other miiphy_* routines also require additional device name argument
  22 + ../lib_i386/board.c
  23 + ../lib_ppc/board.c
  24 + Calling reset_phy() was moved to be executed *after* eth_initialize().
  25 + This is necessary as now some of the implementations of reset_phy()
  26 + may need to use miiphy_reset() which is not allowed before eth_initialize()
  27 + as eth_initialize registers all required miiphy_* routines.
  28 + Tested on IP860 and PHY initializes properly after this change.
  29 +
  30 +* Correct includes for flat tree builder.
  31 +
  32 +* Fix conflicting types (flash_write()) in trab auto_update.c.
  33 +
8 34 * Add PCI support for the TQM834x board.
9 35  
10 36 * Add missing 4xx board to MAKEALL
board/csb272/csb272.c
Diff comments   View file @ d9f2f50
... ... @@ -164,10 +164,15 @@
164 164 int last_stage_init(void)
165 165 {
166 166 /* initialize the PHY */
167   - miiphy_reset(CONFIG_PHY_ADDR);
168   - miiphy_write(CONFIG_PHY_ADDR, PHY_BMCR,
169   - PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); /* AUTO neg */
170   - miiphy_write(CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08); /* LEDs */
  167 + miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
  168 +
  169 + /* AUTO neg */
  170 + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_BMCR,
  171 + PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
  172 +
  173 + /* LEDs */
  174 + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08);
  175 +
171 176  
172 177 return 0; /* success */
173 178 }
board/csb472/csb472.c
Diff comments   View file @ d9f2f50
... ... @@ -132,10 +132,14 @@
132 132 int last_stage_init(void)
133 133 {
134 134 /* initialize the PHY */
135   - miiphy_reset(CONFIG_PHY_ADDR);
136   - miiphy_write(CONFIG_PHY_ADDR, PHY_BMCR,
137   - PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); /* AUTO neg */
138   - miiphy_write(CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08); /* LEDs */
  135 + miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
  136 +
  137 + /* AUTO neg */
  138 + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_BMCR,
  139 + PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
  140 +
  141 + /* LEDs */
  142 + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08);
139 143  
140 144 return 0; /* success */
141 145 }
board/esd/common/misc.c
Diff comments   View file @ d9f2f50
... ... @@ -33,9 +33,9 @@
33 33 {
34 34 unsigned short reg;
35 35  
36   - miiphy_read(CONFIG_PHY_ADDR, 0x10, &reg);
  36 + miiphy_read("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, &reg);
37 37 reg &= ~0x0040; /* disable sleep mode */
38   - miiphy_write(CONFIG_PHY_ADDR, 0x10, reg);
  38 + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, reg);
39 39 }
40 40 #endif /* CONFIG_LXT971_NO_SLEEP */
board/evb64260/eth.c
Diff comments   View file @ d9f2f50
... ... @@ -85,12 +85,17 @@
85 85 static const char ether_port_phy_addr[3]={4,5,6};
86 86 #endif
87 87  
  88 +/* MII PHY access routines are common for all i/f, use gal_ent0 */
  89 +#define GT6426x_MII_DEVNAME "gal_enet0"
88 90  
  91 +int gt6426x_miiphy_read(char *devname, unsigned char phy,
  92 + unsigned char reg, unsigned short *val);
  93 +
89 94 static inline unsigned short
90 95 miiphy_read_ret(unsigned short phy, unsigned short reg)
91 96 {
92 97 unsigned short val;
93   - miiphy_read(phy,reg,&val);
  98 + gt6426x_miiphy_read(GT6426x_MII_DEVNAME,phy,reg,&val);
94 99 return val;
95 100 }
96 101  
... ... @@ -339,8 +344,8 @@
339 344 MII utilities - write: write to an MII register via SMI
340 345 ***************************************************************************/
341 346 int
342   -miiphy_write(unsigned char phy, unsigned char reg,
343   - unsigned short data)
  347 +gt6426x_miiphy_write(char *devname, unsigned char phy,
  348 + unsigned char reg, unsigned short data)
344 349 {
345 350 unsigned int temp= (reg<<21) | (phy<<16) | data;
346 351  
... ... @@ -354,8 +359,8 @@
354 359 MII utilities - read: read from an MII register via SMI
355 360 ***************************************************************************/
356 361 int
357   -miiphy_read(unsigned char phy, unsigned char reg,
358   - unsigned short *val)
  362 +gt6426x_miiphy_read(char *devname, unsigned char phy,
  363 + unsigned char reg, unsigned short *val)
359 364 {
360 365 unsigned int temp= (reg<<21) | (phy<<16) | 1<<26;
361 366  
... ... @@ -444,7 +449,7 @@
444 449 if ((psr & 0x3) != want) {
445 450 printf("MII: GT thinks %x, PHY thinks %x, restarting autoneg..\n",
446 451 psr & 0x3, want);
447   - miiphy_write(ether_port_phy_addr[p->dev],0,
  452 + miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev],0,
448 453 miiphy_read_ret(ether_port_phy_addr[p->dev],0) | (1<<9));
449 454 udelay(10000); /* the EVB's GT takes a while to notice phy
450 455 went down and up */
... ... @@ -490,7 +495,7 @@
490 495 led 2: 0xc=link/rxact
491 496 led 3: 0x2=rxact (N/C)
492 497 strch: 0,2=30 ms, enable */
493   - miiphy_write(ether_port_phy_addr[p->dev], 20, 0x1c22);
  498 + miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev], 20, 0x1c22);
494 499  
495 500 /* 2.7ns port rise time */
496 501 /*miiphy_write(ether_port_phy_addr[p->dev], 30, 0x0<<10); */
497 502  
... ... @@ -792,7 +797,12 @@
792 797  
793 798  
794 799 eth_register(dev);
  800 +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
  801 + miiphy_register(dev->name,
  802 + gt6426x_miiphy_read, gt6426x_miiphy_write);
  803 +#endif
795 804 }
  805 +
796 806 }
797 807 #endif /* CFG_CMD_NET && CONFIG_NET_MULTI */
board/funkwerk/vovpn-gw/m88e6060.c
Diff comments   View file @ d9f2f50
... ... @@ -160,12 +160,12 @@
160 160  
161 161 /*** reset all phys into powerdown ************************************/
162 162 for (i=0, err=0; i<M88X_PHY_CNT; i++) {
163   - err += miiphy_read( devAddr+phyTab[i],M88X_PHY_CNTL,&val );
  163 + err += bb_miiphy_read(NULL, devAddr+phyTab[i],M88X_PHY_CNTL,&val );
164 164 /* keep SpeedLSB, Duplex */
165 165 val &= 0x2100;
166 166 /* set SWReset, AnegEn, PwrDwn, RestartAneg */
167 167 val |= 0x9a00;
168   - err += miiphy_write( devAddr+phyTab[i],M88X_PHY_CNTL,val );
  168 + err += bb_miiphy_write(NULL, devAddr+phyTab[i],M88X_PHY_CNTL,val );
169 169 }
170 170 if (err) {
171 171 printf( "%s [ERR] reset phys\n",_f );
172 172  
... ... @@ -174,9 +174,9 @@
174 174  
175 175 /*** disable all ports ************************************************/
176 176 for (i=0, err=0; i<M88X_PRT_CNT; i++) {
177   - err += miiphy_read( devAddr+prtTab[i],M88X_PRT_CNTL,&val );
  177 + err += bb_miiphy_read(NULL, devAddr+prtTab[i],M88X_PRT_CNTL,&val );
178 178 val &= 0xfffc;
179   - err += miiphy_write( devAddr+prtTab[i],M88X_PRT_CNTL,val );
  179 + err += bb_miiphy_write(NULL, devAddr+prtTab[i],M88X_PRT_CNTL,val );
180 180 }
181 181 if (err) {
182 182 printf( "%s [ERR] disable ports\n",_f );
183 183  
184 184  
185 185  
186 186  
187 187  
188 188  
... ... @@ -187,33 +187,33 @@
187 187 /* set switch mac addr */
188 188 #define ea eth_get_dev()->enetaddr
189 189 val = (ea[4] << 8) | ea[5];
190   - err = miiphy_write( devAddr+15,M88X_GLB_MAC45,val );
  190 + err = bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC45,val );
191 191 val = (ea[2] << 8) | ea[3];
192   - err += miiphy_write( devAddr+15,M88X_GLB_MAC23,val );
  192 + err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC23,val );
193 193 val = (ea[0] << 8) | ea[1];
194 194 #undef ea
195 195 val &= 0xfeff; /* clear DiffAddr */
196   - err += miiphy_write( devAddr+15,M88X_GLB_MAC01,val );
  196 + err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC01,val );
197 197 if (err) {
198 198 printf( "%s [ERR] switch mac address register\n",_f );
199 199 return( -1 );
200 200 }
201 201  
202 202 /* !DiscardExcessive, MaxFrameSize, CtrMode */
203   - err = miiphy_read( devAddr+15,M88X_GLB_CNTL,&val );
  203 + err = bb_miiphy_read(NULL, devAddr+15,M88X_GLB_CNTL,&val );
204 204 val &= 0xd870;
205 205 val |= 0x0500;
206   - err += miiphy_write( devAddr+15,M88X_GLB_CNTL,val );
  206 + err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_CNTL,val );
207 207 if (err) {
208 208 printf( "%s [ERR] switch global control register\n",_f );
209 209 return( -1 );
210 210 }
211 211  
212 212 /* LernDis off, ATUSize 1024, AgeTime 5min */
213   - err = miiphy_read( devAddr+15,M88X_ATU_CNTL,&val );
  213 + err = bb_miiphy_read(NULL, devAddr+15,M88X_ATU_CNTL,&val );
214 214 val &= 0x000f;
215 215 val |= 0x2130;
216   - err += miiphy_write( devAddr+15,M88X_ATU_CNTL,val );
  216 + err += bb_miiphy_write(NULL, devAddr+15,M88X_ATU_CNTL,val );
217 217 if (err) {
218 218 printf( "%s [ERR] atu control register\n",_f );
219 219 return( -1 );
220 220  
... ... @@ -226,10 +226,10 @@
226 226 }
227 227 while (p->reg != -1) {
228 228 err = 0;
229   - err += miiphy_read( devAddr+prtTab[i],p->reg,&val );
  229 + err += bb_miiphy_read(NULL, devAddr+prtTab[i],p->reg,&val );
230 230 val &= p->msk;
231 231 val |= p->val;
232   - err += miiphy_write( devAddr+prtTab[i],p->reg,val );
  232 + err += bb_miiphy_write(NULL, devAddr+prtTab[i],p->reg,val );
233 233 if (err) {
234 234 printf( "%s [ERR] config port %d register %d\n",_f,i,p->reg );
235 235 /* XXX what todo */
236 236  
... ... @@ -245,10 +245,10 @@
245 245 }
246 246 while (p->reg != -1) {
247 247 err = 0;
248   - err += miiphy_read( devAddr+phyTab[i],p->reg,&val );
  248 + err += bb_miiphy_read(NULL, devAddr+phyTab[i],p->reg,&val );
249 249 val &= p->msk;
250 250 val |= p->val;
251   - err += miiphy_write( devAddr+phyTab[i],p->reg,val );
  251 + err += bb_miiphy_write(NULL, devAddr+phyTab[i],p->reg,val );
252 252 if (err) {
253 253 printf( "%s [ERR] config phy %d register %d\n",_f,i,p->reg );
254 254 /* XXX what todo */
board/funkwerk/vovpn-gw/vovpn-gw.c
Diff comments   View file @ d9f2f50
... ... @@ -198,7 +198,7 @@
198 198 iop->pdat |= 0x00080000;
199 199 for (i=0; i<100; i++) {
200 200 udelay(20000);
201   - if (miiphy_read( CFG_PHY_ADDR,2,&val ) == 0) {
  201 + if (bb_miiphy_read("FCC1 ETHERNET", CFG_PHY_ADDR,2,&val ) == 0) {
202 202 break;
203 203 }
204 204 }
board/mpc8260ads/mpc8260ads.c
Diff comments   View file @ d9f2f50
... ... @@ -238,8 +238,9 @@
238 238 * Do not bypass Rx/Tx (de)scrambler (fix configuration error)
239 239 * Enable autonegotiation.
240 240 */
241   - miiphy_write(CFG_PHY_ADDR, 16, 0x610);
242   - miiphy_write(CFG_PHY_ADDR, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
  241 + bb_miiphy_write(NULL, CFG_PHY_ADDR, 16, 0x610);
  242 + bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR,
  243 + PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
243 244 #else
244 245 /*
245 246 * Ethernet PHY is configured (by means of configuration pins)
... ... @@ -247,9 +248,15 @@
247 248 * to advertise all capabilities, including 100Mb/s, and
248 249 * restart autonegotiation.
249 250 */
250   - miiphy_write(CFG_PHY_ADDR, PHY_ANAR, 0x01E1); /* Advertise all capabilities */
251   - miiphy_write(CFG_PHY_ADDR, PHY_DCR, 0x0000); /* Do not bypass Rx/Tx (de)scrambler */
252   - miiphy_write(CFG_PHY_ADDR, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
  251 +
  252 + /* Advertise all capabilities */
  253 + bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_ANAR, 0x01E1);
  254 +
  255 + /* Do not bypass Rx/Tx (de)scrambler */
  256 + bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_DCR, 0x0000);
  257 +
  258 + bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR,
  259 + PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
253 260 #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
254 261 #endif /* CONFIG_MII */
255 262 }
board/mpc8560ads/mpc8560ads.c
Diff comments   View file @ d9f2f50
... ... @@ -237,9 +237,14 @@
237 237 udelay(1000);
238 238 #endif
239 239 #if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
240   - miiphy_reset(0x0); /* reset PHY */
241   - miiphy_write(0, PHY_MIPSCR, 0xf028); /* change PHY address to 0x02 */
242   - miiphy_write(0x02, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
  240 + /* reset PHY */
  241 + miiphy_reset("FCC1 ETHERNET", 0x0);
  242 +
  243 + /* change PHY address to 0x02 */
  244 + bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
  245 +
  246 + bb_miiphy_write(NULL, 0x02, PHY_BMCR,
  247 + PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
243 248 #endif /* CONFIG_MII */
244 249 }
245 250  
board/mpl/mip405/mip405.c
Diff comments   View file @ d9f2f50
... ... @@ -731,12 +731,12 @@
731 731 char *s;
732 732 mem_test_reloc();
733 733 /* write correct LED configuration */
734   - if (miiphy_write (0x1, 0x14, 0x2402) != 0) {
  734 + if (miiphy_write("ppc_4xx_eth0", 0x1, 0x14, 0x2402) != 0) {
735 735 printf ("Error writing to the PHY\n");
736 736 }
737 737 /* since LED/CFG2 is not connected on the -2,
738 738 * write to correct capability information */
739   - if (miiphy_write (0x1, 0x4, 0x01E1) != 0) {
  739 + if (miiphy_write("ppc_4xx_eth0", 0x1, 0x4, 0x01E1) != 0) {
740 740 printf ("Error writing to the PHY\n");
741 741 }
742 742 print_mip405_rev ();
board/netphone/netphone.c
Diff comments   View file @ d9f2f50
... ... @@ -38,6 +38,11 @@
38 38 #include <watchdog.h>
39 39 #endif
40 40  
  41 +int fec8xx_miiphy_read(char *devname, unsigned char addr,
  42 + unsigned char reg, unsigned short *value);
  43 +int fec8xx_miiphy_write(char *devname, unsigned char addr,
  44 + unsigned char reg, unsigned short value);
  45 +
41 46 /****************************************************************/
42 47  
43 48 /* some sane bit macros */
44 49  
45 50  
... ... @@ -483,12 +488,13 @@
483 488 mii_init();
484 489  
485 490 for (phyno = 0; phyno < 32; ++phyno) {
486   - miiphy_read(phyno, PHY_PHYIDR1, &v);
  491 + fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v);
487 492 if (v == 0xFFFF)
488 493 continue;
489   - miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
  494 + fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD);
490 495 udelay(10000);
491   - miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
  496 + fec8xx_miiphy_write(NULL, phyno, PHY_BMCR,
  497 + PHY_BMCR_RESET | PHY_BMCR_AUTON);
492 498 udelay(10000);
493 499 }
494 500 }
... ... @@ -35,6 +35,11 @@
35 35 #include <watchdog.h>
36 36 #endif
37 37  
  38 +int fec8xx_miiphy_read(char *devname, unsigned char addr,
  39 + unsigned char reg, unsigned short *value);
  40 +int fec8xx_miiphy_write(char *devname, unsigned char addr,
  41 + unsigned char reg, unsigned short value);
  42 +
38 43 /****************************************************************/
39 44  
40 45 /* some sane bit macros */
41 46  
42 47  
... ... @@ -431,12 +436,13 @@
431 436 mii_init();
432 437  
433 438 for (phyno = 0; phyno < 32; ++phyno) {
434   - miiphy_read(phyno, PHY_PHYIDR1, &v);
  439 + fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v);
435 440 if (v == 0xFFFF)
436 441 continue;
437   - miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
  442 + fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD);
438 443 udelay(10000);
439   - miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
  444 + fec8xx_miiphy_write(NULL, phyno, PHY_BMCR,
  445 + PHY_BMCR_RESET | PHY_BMCR_AUTON);
440 446 udelay(10000);
441 447 }
442 448 }
board/netta2/netta2.c
Diff comments   View file @ d9f2f50
... ... @@ -36,6 +36,11 @@
36 36 #include <watchdog.h>
37 37 #endif
38 38  
  39 +int fec8xx_miiphy_read(char *devname, unsigned char addr,
  40 + unsigned char reg, unsigned short *value);
  41 +int fec8xx_miiphy_write(char *devname, unsigned char addr,
  42 + unsigned char reg, unsigned short value);
  43 +
39 44 /****************************************************************/
40 45  
41 46 /* some sane bit macros */
42 47  
43 48  
... ... @@ -481,12 +486,13 @@
481 486 mii_init();
482 487  
483 488 for (phyno = 0; phyno < 32; ++phyno) {
484   - miiphy_read(phyno, PHY_PHYIDR1, &v);
  489 + fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v);
485 490 if (v == 0xFFFF)
486 491 continue;
487   - miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
  492 + fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD);
488 493 udelay(10000);
489   - miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
  494 + fec8xx_miiphy_write(NULL, phyno, PHY_BMCR,
  495 + PHY_BMCR_RESET | PHY_BMCR_AUTON);
490 496 udelay(10000);
491 497 }
492 498 }
board/sbc8560/sbc8560.c
Diff comments   View file @ d9f2f50
... ... @@ -223,9 +223,14 @@
223 223 udelay(1000);
224 224 #endif
225 225 #if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
226   - miiphy_reset(0x0); /* reset PHY */
227   - miiphy_write(0, PHY_MIPSCR, 0xf028); /* change PHY address to 0x02 */
228   - miiphy_write(0x02, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
  226 + /* reset PHY */
  227 + miiphy_reset("FCC1 ETHERNET", 0x0);
  228 +
  229 + /* change PHY address to 0x02 */
  230 + bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
  231 +
  232 + bb_miiphy_write(NULL, 0x02, PHY_BMCR,
  233 + PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
229 234 #endif /* CONFIG_MII */
230 235 }
231 236  
board/stxgp3/stxgp3.c
Diff comments   View file @ d9f2f50
... ... @@ -239,9 +239,14 @@
239 239 udelay(1000);
240 240 #endif
241 241 #if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
242   - miiphy_reset(0x0); /* reset PHY */
243   - miiphy_write(0, PHY_MIPSCR, 0xf028); /* change PHY address to 0x02 */
244   - miiphy_write(0x02, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
  242 + /* reset PHY */
  243 + miiphy_reset("FCC1 ETHERNET", 0x0);
  244 +
  245 + /* change PHY address to 0x02 */
  246 + bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
  247 +
  248 + bb_miiphy_write(NULL, 0x02, PHY_BMCR,
  249 + PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
245 250 #endif /* CONFIG_MII */
246 251 #endif
247 252 }
board/stxxtc/stxxtc.c
Diff comments   View file @ d9f2f50
... ... @@ -481,12 +481,12 @@
481 481 mii_init();
482 482  
483 483 for (phyno = 0; phyno < 32; ++phyno) {
484   - miiphy_read(phyno, PHY_PHYIDR1, &v);
  484 + miiphy_read("FEC ETHERNET", phyno, PHY_PHYIDR1, &v);
485 485 if (v == 0xFFFF)
486 486 continue;
487   - miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
  487 + miiphy_write("FEC ETHERNET", phyno, PHY_BMCR, PHY_BMCR_POWD);
488 488 udelay(10000);
489   - miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
  489 + miiphy_write("FEC ETHERNET", phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
490 490 udelay(10000);
491 491 }
492 492 }
board/trab/auto_update.c
Diff comments   View file @ d9f2f50
... ... @@ -199,7 +199,7 @@
199 199 #endif
200 200 extern int flash_sect_erase(ulong, ulong);
201 201 extern int flash_sect_protect (int, ulong, ulong);
202   -extern int flash_write (uchar *, ulong, ulong);
  202 +extern int flash_write (char *, ulong, ulong);
203 203 /* change char* to void* to shutup the compiler */
204 204 extern int i2c_write_multiple (uchar, uint, int, void *, int);
205 205 extern int i2c_read_multiple (uchar, uint, int, void *, int);
... ... @@ -30,6 +30,8 @@
30 30 #include <i2c.h>
31 31 #include <miiphy.h>
32 32  
  33 +int fec8xx_miiphy_write(char *devname, unsigned char addr,
  34 + unsigned char reg, unsigned short value);
33 35  
34 36 /*********************************************************************/
35 37 /* UPMA Pre Initilization Table by WV (Miron MT48LC16M16A2-7E B) */
... ... @@ -258,8 +260,11 @@
258 260 */
259 261 mii_init();
260 262  
261   - miiphy_write(0, PHY_BMCR, 0x2100); /* disable auto-negotiation, 100mbit, full-duplex */
262   - miiphy_write(0, PHY_FCSCR, 0x4122); /* set LED's to Link, Transmit, Receive */
  263 + /* disable auto-negotiation, 100mbit, full-duplex */
  264 + fec8xx_miiphy_write(NULL, 0, PHY_BMCR, 0x2100);
  265 +
  266 + /* set LED's to Link, Transmit, Receive */
  267 + fec8xx_miiphy_write(NULL, 0, PHY_FCSCR, 0x4122);
263 268  
264 269 return 0;
265 270 }
... ... @@ -41,19 +41,21 @@
41 41 uint last_reg;
42 42  
43 43 /*
44   - * MII read/write
  44 + * MII device/info/read/write
45 45 *
46 46 * Syntax:
47   - * mii read {addr} {reg}
48   - * mii write {addr} {reg} {data}
  47 + * mii device {devname}
  48 + * mii info {addr}
  49 + * mii read {addr} {reg}
  50 + * mii write {addr} {reg} {data}
49 51 */
50   -
51 52 int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
52 53 {
53 54 char op;
54 55 unsigned char addr, reg;
55 56 unsigned short data;
56 57 int rcode = 0;
  58 + char *devname;
57 59  
58 60 #if defined(CONFIG_8xx) || defined(CONFIG_MCF52x2)
59 61 mii_init ();
60 62  
... ... @@ -78,8 +80,11 @@
78 80 data = simple_strtoul (argv[4], NULL, 16);
79 81 }
80 82  
  83 + /* use current device */
  84 + devname = miiphy_get_current_dev();
  85 +
81 86 /*
82   - * check info/read/write.
  87 + * check device/read/write/list.
83 88 */
84 89 if (op == 'i') {
85 90 unsigned char j, start, end;
86 91  
87 92  
88 93  
89 94  
90 95  
91 96  
92 97  
93 98  
... ... @@ -91,34 +96,43 @@
91 96 * Look for any and all PHYs. Valid addresses are 0..31.
92 97 */
93 98 if (argc >= 3) {
94   - start = addrlo; end = addrhi + 1;
  99 + start = addr; end = addr + 1;
95 100 } else {
96   - start = 0; end = 32;
  101 + start = 0; end = 31;
97 102 }
98 103  
99 104 for (j = start; j < end; j++) {
100   - if (miiphy_info (j, &oui, &model, &rev) == 0) {
  105 + if (miiphy_info (devname, j, &oui, &model, &rev) == 0) {
101 106 printf ("PHY 0x%02X: "
102 107 "OUI = 0x%04X, "
103 108 "Model = 0x%02X, "
104 109 "Rev = 0x%02X, "
105 110 "%3dbaseT, %s\n",
106 111 j, oui, model, rev,
107   - miiphy_speed (j),
108   - miiphy_duplex (j) == FULL ? "FDX" : "HDX");
  112 + miiphy_speed (devname, j),
  113 + (miiphy_duplex (devname, j) == FULL)
  114 + ? "FDX" : "HDX");
  115 + } else {
  116 + puts ("Error reading info from the PHY\n");
109 117 }
110 118 }
111 119 } else if (op == 'r') {
112   - if (miiphy_read (addr, reg, &data) != 0) {
  120 + if (miiphy_read (devname, addr, reg, &data) != 0) {
113 121 puts ("Error reading from the PHY\n");
114 122 rcode = 1;
  123 + } else {
  124 + printf ("%04X\n", data & 0x0000FFFF);
115 125 }
116   - printf ("%04X\n", data & 0x0000FFFF);
117 126 } else if (op == 'w') {
118   - if (miiphy_write (addr, reg, data) != 0) {
  127 + if (miiphy_write (devname, addr, reg, data) != 0) {
119 128 puts ("Error writing to the PHY\n");
120 129 rcode = 1;
121 130 }
  131 + } else if (op == 'd') {
  132 + if (argc == 2)
  133 + miiphy_listdev ();
  134 + else
  135 + miiphy_set_current_dev (argv[2]);
122 136 } else {
123 137 printf ("Usage:\n%s\n", cmdtp->usage);
124 138 return 1;
... ... @@ -140,9 +154,11 @@
140 154 U_BOOT_CMD(
141 155 mii, 5, 1, do_mii,
142 156 "mii - MII utility commands\n",
143   - "info <addr> - display MII PHY info\n"
144   - "mii read <addr> <reg> - read MII PHY <addr> register <reg>\n"
145   - "mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n"
  157 + "device - list available devices\n"
  158 + "mii device <devname> - set current device\n"
  159 + "mii info <addr> - display MII PHY info\n"
  160 + "mii read <addr> <reg> - read MII PHY <addr> register <reg>\n"
  161 + "mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n"
146 162 );
147 163  
148 164 #else /* ! CONFIG_TERSE_MII ================================================= */
... ... @@ -386,7 +402,7 @@
386 402 return 0;
387 403 }
388 404  
389   -uint last_op;
  405 +char last_op[2];
390 406 uint last_data;
391 407 uint last_addr_lo;
392 408 uint last_addr_hi;
393 409  
... ... @@ -412,11 +428,12 @@
412 428 /* ---------------------------------------------------------------- */
413 429 int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
414 430 {
415   - char op;
  431 + char op[2];
416 432 unsigned char addrlo, addrhi, reglo, reghi;
417 433 unsigned char addr, reg;
418 434 unsigned short data;
419 435 int rcode = 0;
  436 + char *devname;
420 437  
421 438 #ifdef CONFIG_8xx
422 439 mii_init ();
... ... @@ -426,7 +443,8 @@
426 443 * We use the last specified parameters, unless new ones are
427 444 * entered.
428 445 */
429   - op = last_op;
  446 + op[0] = last_op[0];
  447 + op[1] = last_op[1];
430 448 addrlo = last_addr_lo;
431 449 addrhi = last_addr_hi;
432 450 reglo = last_reg_lo;
... ... @@ -434,7 +452,12 @@
434 452 data = last_data;
435 453  
436 454 if ((flag & CMD_FLAG_REPEAT) == 0) {
437   - op = argv[1][0];
  455 + op[0] = argv[1][0];
  456 + if (strlen(argv[1]) > 1)
  457 + op[1] = argv[1][1];
  458 + else
  459 + op[1] = '\0';
  460 +
438 461 if (argc >= 3)
439 462 extract_range(argv[2], &addrlo, &addrhi);
440 463 if (argc >= 4)
441 464  
... ... @@ -443,10 +466,13 @@
443 466 data = simple_strtoul (argv[4], NULL, 16);
444 467 }
445 468  
  469 + /* use current device */
  470 + devname = miiphy_get_current_dev();
  471 +
446 472 /*
447 473 * check info/read/write.
448 474 */
449   - if (op == 'i') {
  475 + if (op[0] == 'i') {
450 476 unsigned char j, start, end;
451 477 unsigned int oui;
452 478 unsigned char model;
453 479  
454 480  
455 481  
... ... @@ -462,22 +488,25 @@
462 488 }
463 489  
464 490 for (j = start; j <= end; j++) {
465   - if (miiphy_info (j, &oui, &model, &rev) == 0) {
  491 + if (miiphy_info (devname, j, &oui, &model, &rev) == 0) {
466 492 printf("PHY 0x%02X: "
467 493 "OUI = 0x%04X, "
468 494 "Model = 0x%02X, "
469 495 "Rev = 0x%02X, "
470 496 "%3dbaseT, %s\n",
471 497 j, oui, model, rev,
472   - miiphy_speed (j),
473   - miiphy_duplex (j) == FULL ? "FDX" : "HDX");
  498 + miiphy_speed (devname, j),
  499 + (miiphy_duplex (devname, j) == FULL)
  500 + ? "FDX" : "HDX");
  501 + } else {
  502 + puts ("Error reading info from the PHY\n");
474 503 }
475 504 }
476   - } else if (op == 'r') {
  505 + } else if (op[0] == 'r') {
477 506 for (addr = addrlo; addr <= addrhi; addr++) {
478 507 for (reg = reglo; reg <= reghi; reg++) {
479 508 data = 0xffff;
480   - if (miiphy_read (addr, reg, &data) != 0) {
  509 + if (miiphy_read (devname, addr, reg, &data) != 0) {
481 510 printf(
482 511 "Error reading from the PHY addr=%02x reg=%02x\n",
483 512 addr, reg);
484 513  
485 514  
... ... @@ -492,17 +521,17 @@
492 521 if ((addrlo != addrhi) && (reglo != reghi))
493 522 printf("\n");
494 523 }
495   - } else if (op == 'w') {
  524 + } else if (op[0] == 'w') {
496 525 for (addr = addrlo; addr <= addrhi; addr++) {
497 526 for (reg = reglo; reg <= reghi; reg++) {
498   - if (miiphy_write (addr, reg, data) != 0) {
  527 + if (miiphy_write (devname, addr, reg, data) != 0) {
499 528 printf("Error writing to the PHY addr=%02x reg=%02x\n",
500 529 addr, reg);
501 530 rcode = 1;
502 531 }
503 532 }
504 533 }
505   - } else if (op == 'd') {
  534 + } else if (strncmp(op, "du", 2) == 0) {
506 535 ushort regs[6];
507 536 int ok = 1;
508 537 if ((reglo > 5) || (reghi > 5)) {
... ... @@ -512,8 +541,8 @@
512 541 return 1;
513 542 }
514 543 for (addr = addrlo; addr <= addrhi; addr++) {
515   - for (reg = 0; reg < 6; reg++) {
516   - if (miiphy_read(addr, reg, &regs[reg]) != 0) {
  544 + for (reg = reglo; reg < reghi + 1; reg++) {
  545 + if (miiphy_read(devname, addr, reg, &regs[reg]) != 0) {
517 546 ok = 0;
518 547 printf(
519 548 "Error reading from the PHY addr=%02x reg=%02x\n",
... ... @@ -525,6 +554,11 @@
525 554 MII_dump_0_to_5(regs, reglo, reghi);
526 555 printf("\n");
527 556 }
  557 + } else if (strncmp(op, "de", 2) == 0) {
  558 + if (argc == 2)
  559 + miiphy_listdev ();
  560 + else
  561 + miiphy_set_current_dev (argv[2]);
528 562 } else {
529 563 printf("Usage:\n%s\n", cmdtp->usage);
530 564 return 1;
... ... @@ -533,7 +567,8 @@
533 567 /*
534 568 * Save the parameters for repeats.
535 569 */
536   - last_op = op;
  570 + last_op[0] = op[0];
  571 + last_op[1] = op[1];
537 572 last_addr_lo = addrlo;
538 573 last_addr_hi = addrhi;
539 574 last_reg_lo = reglo;
... ... @@ -548,10 +583,12 @@
548 583 U_BOOT_CMD(
549 584 mii, 5, 1, do_mii,
550 585 "mii - MII utility commands\n",
551   - "info <addr> - display MII PHY info\n"
552   - "mii read <addr> <reg> - read MII PHY <addr> register <reg>\n"
553   - "mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n"
554   - "mii dump <addr> <reg> - pretty-print <addr> <reg> (0-5 only)\n"
  586 + "device - list available devices\n"
  587 + "mii device <devname> - set current device\n"
  588 + "mii info <addr> - display MII PHY info\n"
  589 + "mii read <addr> <reg> - read MII PHY <addr> register <reg>\n"
  590 + "mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n"
  591 + "mii dump <addr> <reg> - pretty-print <addr> <reg> (0-5 only)\n"
555 592 "Addr and/or reg may be ranges, e.g. 2-7.\n"
556 593 );
557 594  
... ... @@ -6,12 +6,12 @@
6 6 #include <malloc.h>
7 7 #include <environment.h>
8 8  
  9 +#ifdef CONFIG_OF_FLAT_TREE
  10 +
9 11 #include <asm/errno.h>
10 12 #include <stddef.h>
11 13  
12 14 #include <ft_build.h>
13   -
14   -#ifdef CONFIG_OF_FLAT_TREE
15 15  
16 16 /* align addr on a size boundary - adjust address up if needed -- Cort */
17 17 #define _ALIGN(addr,size) (((addr)+(size)-1)&(~((size)-1)))
... ... @@ -121,7 +121,8 @@
121 121 * Returns:
122 122 * 0 on success
123 123 */
124   -int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
  124 +int bb_miiphy_read (char *devname, unsigned char addr,
  125 + unsigned char reg, unsigned short *value)
125 126 {
126 127 short rdreg; /* register working value */
127 128 int j; /* counter */
... ... @@ -188,7 +189,8 @@
188 189 * Returns:
189 190 * 0 on success
190 191 */
191   -int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
  192 +int bb_miiphy_write (char *devname, unsigned char addr,
  193 + unsigned char reg, unsigned short value)
192 194 {
193 195 int j; /* counter */
194 196 #ifndef CONFIG_EP8248
... ... @@ -30,9 +30,218 @@
30 30 #include <miiphy.h>
31 31  
32 32 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
  33 +#include <asm/types.h>
  34 +#include <linux/list.h>
  35 +#include <malloc.h>
  36 +#include <net.h>
33 37  
  38 +/* local debug macro */
  39 +#define MII_DEBUG
  40 +#undef MII_DEBUG
  41 +
  42 +#undef debug
  43 +#ifdef MII_DEBUG
  44 +#define debug(fmt,args...) printf (fmt ,##args)
  45 +#else
  46 +#define debug(fmt,args...)
  47 +#endif /* MII_DEBUG */
  48 +
  49 +struct mii_dev {
  50 + struct list_head link;
  51 + char *name;
  52 + int (* read)(char *devname, unsigned char addr,
  53 + unsigned char reg, unsigned short *value);
  54 + int (* write)(char *devname, unsigned char addr,
  55 + unsigned char reg, unsigned short value);
  56 +};
  57 +
  58 +static struct list_head mii_devs;
  59 +static struct mii_dev *current_mii;
  60 +
34 61 /*****************************************************************************
35 62 *
  63 + * Register read and write MII access routines for the device <name>.
  64 + */
  65 +void miiphy_register(char *name,
  66 + int (* read)(char *devname, unsigned char addr,
  67 + unsigned char reg, unsigned short *value),
  68 + int (* write)(char *devname, unsigned char addr,
  69 + unsigned char reg, unsigned short value))
  70 +{
  71 + struct list_head *entry;
  72 + struct mii_dev *new_dev;
  73 + struct mii_dev *miidev;
  74 + static int head_initialized = 0;
  75 + unsigned int name_len;
  76 +
  77 + if (head_initialized == 0) {
  78 + INIT_LIST_HEAD(&mii_devs);
  79 + current_mii = NULL;
  80 + head_initialized = 1;
  81 + }
  82 +
  83 + /* check if we have unique name */
  84 + list_for_each(entry, &mii_devs) {
  85 + miidev = list_entry(entry, struct mii_dev, link);
  86 + if (strcmp(miidev->name, name) == 0) {
  87 + printf("miiphy_register: non unique device name '%s'\n",
  88 + name);
  89 + return;
  90 + }
  91 + }
  92 +
  93 + /* allocate memory */
  94 + name_len = strlen(name);
  95 + new_dev = (struct mii_dev *)malloc(sizeof(struct mii_dev) + name_len + 1);
  96 +
  97 + if(new_dev == NULL) {
  98 + printf("miiphy_register: cannot allocate memory for '%s'\n",
  99 + name);
  100 + return;
  101 + }
  102 + memset(new_dev, 0, sizeof(struct mii_dev) + name_len);
  103 +
  104 + /* initalize mii_dev struct fields */
  105 + INIT_LIST_HEAD(&new_dev->link);
  106 + new_dev->read = read;
  107 + new_dev->write = write;
  108 + new_dev->name = (char *)(new_dev + 1);
  109 + strncpy(new_dev->name, name, name_len);
  110 + new_dev->name[name_len] = '\0';
  111 +
  112 + debug("miiphy_register: added '%s', read=0x%08lx, write=0x%08lx\n",
  113 + new_dev->name, new_dev->read, new_dev->write);
  114 +
  115 + /* add it to the list */
  116 + list_add_tail(&new_dev->link, &mii_devs);
  117 +
  118 + if (!current_mii)
  119 + current_mii = new_dev;
  120 +}
  121 +
  122 +int miiphy_set_current_dev(char *devname)
  123 +{
  124 + struct list_head *entry;
  125 + struct mii_dev *dev;
  126 +
  127 + list_for_each(entry, &mii_devs) {
  128 + dev = list_entry(entry, struct mii_dev, link);
  129 +
  130 + if (strcmp(devname, dev->name) == 0) {
  131 + current_mii = dev;
  132 + return 0;
  133 + }
  134 + }
  135 +
  136 + printf("No such device: %s\n", devname);
  137 + return 1;
  138 +}
  139 +
  140 +char *miiphy_get_current_dev()
  141 +{
  142 + if (current_mii)
  143 + return current_mii->name;
  144 +
  145 + return NULL;
  146 +}
  147 +
  148 +/*****************************************************************************
  149 + *
  150 + * Read to variable <value> from the PHY attached to device <devname>,
  151 + * use PHY address <addr> and register <reg>.
  152 + *
  153 + * Returns:
  154 + * 0 on success
  155 + */
  156 +int miiphy_read(char *devname, unsigned char addr, unsigned char reg,
  157 + unsigned short *value)
  158 +{
  159 + struct list_head *entry;
  160 + struct mii_dev *dev;
  161 + int found_dev = 0;
  162 + int read_ret = 0;
  163 +
  164 + if (!devname) {
  165 + printf("NULL device name!\n");
  166 + return 1;
  167 + }
  168 +
  169 + list_for_each(entry, &mii_devs) {
  170 + dev = list_entry(entry, struct mii_dev, link);
  171 +
  172 + if (strcmp(devname, dev->name) == 0) {
  173 + found_dev = 1;
  174 + read_ret = dev->read(devname, addr, reg, value);
  175 + break;
  176 + }
  177 + }
  178 +
  179 + if (found_dev == 0)
  180 + printf("No such device: %s\n", devname);
  181 +
  182 + return ((found_dev) ? read_ret : 1);
  183 +}
  184 +
  185 +/*****************************************************************************
  186 + *
  187 + * Write <value> to the PHY attached to device <devname>,
  188 + * use PHY address <addr> and register <reg>.
  189 + *
  190 + * Returns:
  191 + * 0 on success
  192 + */
  193 +int miiphy_write(char *devname, unsigned char addr, unsigned char reg,
  194 + unsigned short value)
  195 +{
  196 + struct list_head *entry;
  197 + struct mii_dev *dev;
  198 + int found_dev = 0;
  199 + int write_ret = 0;
  200 +
  201 + if (!devname) {
  202 + printf("NULL device name!\n");
  203 + return 1;
  204 + }
  205 +
  206 + list_for_each(entry, &mii_devs) {
  207 + dev = list_entry(entry, struct mii_dev, link);
  208 +
  209 + if (strcmp(devname, dev->name) == 0) {
  210 + found_dev = 1;
  211 + write_ret = dev->write(devname, addr, reg, value);
  212 + break;
  213 + }
  214 + }
  215 +
  216 + if (found_dev == 0)
  217 + printf("No such device: %s\n", devname);
  218 +
  219 + return ((found_dev) ? write_ret : 1);
  220 +}
  221 +
  222 +/*****************************************************************************
  223 + *
  224 + * Print out list of registered MII capable devices.
  225 + */
  226 +void miiphy_listdev(void)
  227 +{
  228 + struct list_head *entry;
  229 + struct mii_dev *dev;
  230 +
  231 + puts("MII devices: ");
  232 + list_for_each(entry, &mii_devs) {
  233 + dev = list_entry(entry, struct mii_dev, link);
  234 + printf("'%s' ", dev->name);
  235 + }
  236 + puts("\n");
  237 +
  238 + if (current_mii)
  239 + printf("Current device: '%s'\n", current_mii->name);
  240 +}
  241 +
  242 +
  243 +/*****************************************************************************
  244 + *
36 245 * Read the OUI, manufacture's model number, and revision number.
37 246 *
38 247 * OUI: 22 bits (unsigned int)
39 248  
... ... @@ -42,14 +251,15 @@
42 251 * Returns:
43 252 * 0 on success
44 253 */
45   -int miiphy_info (unsigned char addr,
  254 +int miiphy_info (char *devname,
  255 + unsigned char addr,
46 256 unsigned int *oui,
47 257 unsigned char *model, unsigned char *rev)
48 258 {
49 259 unsigned int reg = 0;
50 260 unsigned short tmp;
51 261  
52   - if (miiphy_read (addr, PHY_PHYIDR2, &tmp) != 0) {
  262 + if (miiphy_read (devname, addr, PHY_PHYIDR2, &tmp) != 0) {
53 263 #ifdef DEBUG
54 264 puts ("PHY ID register 2 read failed\n");
55 265 #endif
... ... @@ -65,7 +275,7 @@
65 275 return (-1);
66 276 }
67 277  
68   - if (miiphy_read (addr, PHY_PHYIDR1, &tmp) != 0) {
  278 + if (miiphy_read (devname, addr, PHY_PHYIDR1, &tmp) != 0) {
69 279 #ifdef DEBUG
70 280 puts ("PHY ID register 1 read failed\n");
71 281 #endif
72 282  
73 283  
... ... @@ -88,18 +298,18 @@
88 298 * Returns:
89 299 * 0 on success
90 300 */
91   -int miiphy_reset (unsigned char addr)
  301 +int miiphy_reset (char *devname, unsigned char addr)
92 302 {
93 303 unsigned short reg;
94 304 int loop_cnt;
95 305  
96   - if (miiphy_read (addr, PHY_BMCR, &reg) != 0) {
  306 + if (miiphy_read (devname, addr, PHY_BMCR, &reg) != 0) {
97 307 #ifdef DEBUG
98 308 printf ("PHY status read failed\n");
99 309 #endif
100 310 return (-1);
101 311 }
102   - if (miiphy_write (addr, PHY_BMCR, reg | 0x8000) != 0) {
  312 + if (miiphy_write (devname, addr, PHY_BMCR, reg | 0x8000) != 0) {
103 313 #ifdef DEBUG
104 314 puts ("PHY reset failed\n");
105 315 #endif
... ... @@ -116,7 +326,7 @@
116 326 loop_cnt = 0;
117 327 reg = 0x8000;
118 328 while (((reg & 0x8000) != 0) && (loop_cnt++ < 1000000)) {
119   - if (miiphy_read (addr, PHY_BMCR, &reg) != 0) {
  329 + if (miiphy_read (devname, addr, PHY_BMCR, &reg) != 0) {
120 330 # ifdef DEBUG
121 331 puts ("PHY status read failed\n");
122 332 # endif
123 333  
... ... @@ -137,12 +347,12 @@
137 347 *
138 348 * Determine the ethernet speed (10/100).
139 349 */
140   -int miiphy_speed (unsigned char addr)
  350 +int miiphy_speed (char *devname, unsigned char addr)
141 351 {
142 352 unsigned short reg;
143 353  
144 354 #if defined(CONFIG_PHY_GIGE)
145   - if (miiphy_read (addr, PHY_1000BTSR, &reg)) {
  355 + if (miiphy_read (devname, addr, PHY_1000BTSR, &reg)) {
146 356 printf ("PHY 1000BT Status read failed\n");
147 357 } else {
148 358 if (reg != 0xFFFF) {
149 359  
... ... @@ -154,14 +364,14 @@
154 364 #endif /* CONFIG_PHY_GIGE */
155 365  
156 366 /* Check Basic Management Control Register first. */
157   - if (miiphy_read (addr, PHY_BMCR, &reg)) {
  367 + if (miiphy_read (devname, addr, PHY_BMCR, &reg)) {
158 368 puts ("PHY speed read failed, assuming 10bT\n");
159 369 return (_10BASET);
160 370 }
161 371 /* Check if auto-negotiation is on. */
162 372 if ((reg & PHY_BMCR_AUTON) != 0) {
163 373 /* Get auto-negotiation results. */
164   - if (miiphy_read (addr, PHY_ANLPAR, &reg)) {
  374 + if (miiphy_read (devname, addr, PHY_ANLPAR, &reg)) {
165 375 puts ("PHY AN speed read failed, assuming 10bT\n");
166 376 return (_10BASET);
167 377 }
168 378  
... ... @@ -185,12 +395,12 @@
185 395 *
186 396 * Determine full/half duplex.
187 397 */
188   -int miiphy_duplex (unsigned char addr)
  398 +int miiphy_duplex (char *devname, unsigned char addr)
189 399 {
190 400 unsigned short reg;
191 401  
192 402 #if defined(CONFIG_PHY_GIGE)
193   - if (miiphy_read (addr, PHY_1000BTSR, &reg)) {
  403 + if (miiphy_read (devname, addr, PHY_1000BTSR, &reg)) {
194 404 printf ("PHY 1000BT Status read failed\n");
195 405 } else {
196 406 if ( (reg != 0xFFFF) &&
197 407  
... ... @@ -205,14 +415,14 @@
205 415 #endif /* CONFIG_PHY_GIGE */
206 416  
207 417 /* Check Basic Management Control Register first. */
208   - if (miiphy_read (addr, PHY_BMCR, &reg)) {
  418 + if (miiphy_read (devname, addr, PHY_BMCR, &reg)) {
209 419 puts ("PHY duplex read failed, assuming half duplex\n");
210 420 return (HALF);
211 421 }
212 422 /* Check if auto-negotiation is on. */
213 423 if ((reg & PHY_BMCR_AUTON) != 0) {
214 424 /* Get auto-negotiation results. */
215   - if (miiphy_read (addr, PHY_ANLPAR, &reg)) {
  425 + if (miiphy_read (devname, addr, PHY_ANLPAR, &reg)) {
216 426 puts ("PHY AN duplex read failed, assuming half duplex\n");
217 427 return (HALF);
218 428 }
219 429  
... ... @@ -237,13 +447,13 @@
237 447 *
238 448 * Determine link status
239 449 */
240   -int miiphy_link (unsigned char addr)
  450 +int miiphy_link (char *devname, unsigned char addr)
241 451 {
242 452 unsigned short reg;
243 453  
244 454 /* dummy read; needed to latch some phys */
245   - (void)miiphy_read(addr, PHY_BMSR, &reg);
246   - if (miiphy_read (addr, PHY_BMSR, &reg)) {
  455 + (void)miiphy_read(devname, addr, PHY_BMSR, &reg);
  456 + if (miiphy_read (devname, addr, PHY_BMSR, &reg)) {
247 457 puts ("PHY_BMSR read failed, assuming no link\n");
248 458 return (0);
249 459 }
cpu/arm920t/at91rm9200/ether.c
Diff comments   View file @ d9f2f50
... ... @@ -23,6 +23,7 @@
23 23  
24 24 #include <at91rm9200_net.h>
25 25 #include <net.h>
  26 +#include <miiphy.h>
26 27  
27 28 /* ----- Ethernet Buffer definitions ----- */
28 29  
... ... @@ -150,7 +151,6 @@
150 151 return TRUE;
151 152 }
152 153  
153   -
154 154 int eth_init (bd_t * bd)
155 155 {
156 156 int ret;
... ... @@ -265,8 +265,9 @@
265 265 {
266 266 };
267 267  
268   -#if (CONFIG_COMMANDS & CFG_CMD_MII)
269   -int miiphy_read(unsigned char addr, unsigned char reg, unsigned short * value)
  268 +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
  269 +int at91rm9200_miiphy_read(char *devname, unsigned char addr,
  270 + unsigned char reg, unsigned short * value)
270 271 {
271 272 at91rm9200_EmacEnableMDIO (p_mac);
272 273 at91rm9200_EmacReadPhy (p_mac, reg, value);
273 274  
... ... @@ -274,14 +275,24 @@
274 275 return 0;
275 276 }
276 277  
277   -int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
  278 +int at91rm9200_miiphy_write(char *devname, unsigned char addr,
  279 + unsigned char reg, unsigned short value)
278 280 {
279 281 at91rm9200_EmacEnableMDIO (p_mac);
280 282 at91rm9200_EmacWritePhy (p_mac, reg, &value);
281 283 at91rm9200_EmacDisableMDIO (p_mac);
282 284 return 0;
283 285 }
284   -#endif /* CONFIG_COMMANDS & CFG_CMD_MII */
  286 +
  287 +#endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) */
  288 +
  289 +int at91rm9200_miiphy_initialize(bd_t *bis)
  290 +{
  291 +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
  292 + miiphy_register("at91rm9200phy", at91rm9200_miiphy_read, at91rm9200_miiphy_write);
  293 +#endif
  294 + return 0;
  295 +}
285 296  
286 297 #endif /* CONFIG_COMMANDS & CFG_CMD_NET */
287 298  
... ... @@ -519,7 +519,8 @@
519 519 * Otherwise they hang in mii_send() !!! Sorry!
520 520 *****************************************************************************/
521 521  
522   -int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
  522 +int mcf52x2_miiphy_read (char *devname, unsigned char addr,
  523 + unsigned char reg, unsigned short *value)
523 524 {
524 525 short rdreg; /* register working value */
525 526  
... ... @@ -537,7 +538,8 @@
537 538 return 0;
538 539 }
539 540  
540   -int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
  541 +int mcf52x2_miiphy_write (char *devname, unsigned char addr,
  542 + unsigned char reg, unsigned short value)
541 543 {
542 544 short rdreg; /* register working value */
543 545  
544 546  
... ... @@ -554,6 +556,15 @@
554 556 return 0;
555 557 }
556 558 #endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII) */
557   -
558 559 #endif /* CFG_CMD_NET, FEC_ENET */
  560 +
  561 +int mcf52x2_miiphy_initialize(bd_t *bis)
  562 +{
  563 +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
  564 +#if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)
  565 + miiphy_register("mcf52x2phy", mcf52x2_miiphy_read, mcf52x2_miiphy_write);
  566 +#endif
  567 +#endif
  568 + return 0;
  569 +}
cpu/mips/au1x00_eth.c
Diff comments   View file @ d9f2f50
... ... @@ -63,6 +63,10 @@
63 63 #include <asm/io.h>
64 64 #include <asm/au1x00.h>
65 65  
  66 +#if (CONFIG_COMMANDS & CFG_CMD_MII)
  67 +#include <miiphy.h>
  68 +#endif
  69 +
66 70 /* Ethernet Transmit and Receive Buffers */
67 71 #define DBUF_LENGTH 1520
68 72 #define PKT_MAXBUF_SIZE 1518
69 73  
... ... @@ -233,11 +237,17 @@
233 237  
234 238 eth_register(dev);
235 239  
  240 +#if (CONFIG_COMMANDS & CFG_CMD_MII)
  241 + miiphy_register(dev->name,
  242 + au1x00_miiphy_read, au1x00_miiphy_write);
  243 +#endif
  244 +
236 245 return 1;
237 246 }
238 247  
239 248 #if (CONFIG_COMMANDS & CFG_CMD_MII)
240   -int miiphy_read(unsigned char addr, unsigned char reg, unsigned short * value)
  249 +int au1x00_miiphy_read(char *devname, unsigned char addr,
  250 + unsigned char reg, unsigned short * value)
241 251 {
242 252 volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
243 253 volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
... ... @@ -269,7 +279,8 @@
269 279 return 0;
270 280 }
271 281  
272   -int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
  282 +int au1x00_miiphy_write(char *devname, unsigned char addr,
  283 + unsigned char reg, unsigned short value)
273 284 {
274 285 volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
275 286 volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
... ... @@ -19,9 +19,13 @@
19 19 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
20 20 defined(CONFIG_MPC5xxx_FEC)
21 21  
  22 +#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
  23 +#error "CONFIG_MII has to be defined!"
  24 +#endif
  25 +
22 26 #if (DEBUG & 0x60)
23   -static void tfifo_print(mpc5xxx_fec_priv *fec);
24   -static void rfifo_print(mpc5xxx_fec_priv *fec);
  27 +static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec);
  28 +static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec);
25 29 #endif /* DEBUG */
26 30  
27 31 #if (DEBUG & 0x40)
28 32  
... ... @@ -35,9 +39,12 @@
35 39 uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
36 40 } NBUF;
37 41  
  42 +int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal);
  43 +int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
  44 +
38 45 /********************************************************************/
39 46 #if (DEBUG & 0x2)
40   -static void mpc5xxx_fec_phydump (void)
  47 +static void mpc5xxx_fec_phydump (char *devname)
41 48 {
42 49 uint16 phyStatus, i;
43 50 uint8 phyAddr = CONFIG_PHY_ADDR;
... ... @@ -55,7 +62,7 @@
55 62  
56 63 for (i = 0; i < 32; i++) {
57 64 if (reg_mask[i]) {
58   - miiphy_read(phyAddr, i, &phyStatus);
  65 + miiphy_read(devname, phyAddr, i, &phyStatus);
59 66 printf("Mii reg %d: 0x%04x\n", i, phyStatus);
60 67 }
61 68 }
... ... @@ -457,7 +464,7 @@
457 464 /*
458 465 * Reset PHY, then delay 300ns
459 466 */
460   - miiphy_write(phyAddr, 0x0, 0x8000);
  467 + miiphy_write(dev->name, phyAddr, 0x0, 0x8000);
461 468 udelay(1000);
462 469  
463 470 if (fec->xcv_type == MII10) {
464 471  
465 472  
... ... @@ -467,11 +474,11 @@
467 474 #if (DEBUG & 0x2)
468 475 printf("Forcing 10 Mbps ethernet link... ");
469 476 #endif
470   - miiphy_read(phyAddr, 0x1, &phyStatus);
  477 + miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
471 478 /*
472   - miiphy_write(fec, phyAddr, 0x0, 0x0100);
  479 + miiphy_write(dev->name, fec, phyAddr, 0x0, 0x0100);
473 480 */
474   - miiphy_write(phyAddr, 0x0, 0x0180);
  481 + miiphy_write(dev->name, phyAddr, 0x0, 0x0180);
475 482  
476 483 timeout = 20;
477 484 do { /* wait for link status to go down */
... ... @@ -482,7 +489,7 @@
482 489 #endif
483 490 break;
484 491 }
485   - miiphy_read(phyAddr, 0x1, &phyStatus);
  492 + miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
486 493 #if (DEBUG & 0x2)
487 494 printf("=");
488 495 #endif
... ... @@ -495,7 +502,7 @@
495 502 printf("failed. Link is down.\n");
496 503 break;
497 504 }
498   - miiphy_read(phyAddr, 0x1, &phyStatus);
  505 + miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
499 506 #if (DEBUG & 0x2)
500 507 printf("+");
501 508 #endif
502 509  
... ... @@ -508,12 +515,12 @@
508 515 /*
509 516 * Set the auto-negotiation advertisement register bits
510 517 */
511   - miiphy_write(phyAddr, 0x4, 0x01e1);
  518 + miiphy_write(dev->name, phyAddr, 0x4, 0x01e1);
512 519  
513 520 /*
514 521 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
515 522 */
516   - miiphy_write(phyAddr, 0x0, 0x1200);
  523 + miiphy_write(dev->name, phyAddr, 0x0, 0x1200);
517 524  
518 525 /*
519 526 * Wait for AN completion
... ... @@ -529,7 +536,7 @@
529 536 return -1;
530 537 }
531 538  
532   - if (miiphy_read(phyAddr, 0x1, &phyStatus) != 0) {
  539 + if (miiphy_read(dev->name, phyAddr, 0x1, &phyStatus) != 0) {
533 540 #if (DEBUG & 0x2)
534 541 printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
535 542 #endif
... ... @@ -546,7 +553,7 @@
546 553  
547 554 #if (DEBUG & 0x2)
548 555 if (fec->xcv_type != SEVENWIRE)
549   - mpc5xxx_fec_phydump ();
  556 + mpc5xxx_fec_phydump (dev->name);
550 557 #endif
551 558  
552 559  
... ... @@ -631,7 +638,7 @@
631 638 #if (DEBUG & 0x60)
632 639 /********************************************************************/
633 640  
634   -static void tfifo_print(mpc5xxx_fec_priv *fec)
  641 +static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec)
635 642 {
636 643 uint16 phyAddr = CONFIG_PHY_ADDR;
637 644 uint16 phyStatus;
... ... @@ -639,7 +646,7 @@
639 646 if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
640 647 || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
641 648  
642   - miiphy_read(phyAddr, 0x1, &phyStatus);
  649 + miiphy_read(devname, phyAddr, 0x1, &phyStatus);
643 650 printf("\nphyStatus: 0x%04x\n", phyStatus);
644 651 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
645 652 printf("ievent: 0x%08x\n", fec->eth->ievent);
... ... @@ -655,7 +662,7 @@
655 662 }
656 663 }
657 664  
658   -static void rfifo_print(mpc5xxx_fec_priv *fec)
  665 +static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec)
659 666 {
660 667 uint16 phyAddr = CONFIG_PHY_ADDR;
661 668 uint16 phyStatus;
... ... @@ -663,7 +670,7 @@
663 670 if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
664 671 || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
665 672  
666   - miiphy_read(phyAddr, 0x1, &phyStatus);
  673 + miiphy_read(devname, phyAddr, 0x1, &phyStatus);
667 674 printf("\nphyStatus: 0x%04x\n", phyStatus);
668 675 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
669 676 printf("ievent: 0x%08x\n", fec->eth->ievent);
... ... @@ -694,7 +701,7 @@
694 701  
695 702 #if (DEBUG & 0x20)
696 703 printf("tbd status: 0x%04x\n", fec->tbdBase[0].status);
697   - tfifo_print(fec);
  704 + tfifo_print(dev->name, fec);
698 705 #endif
699 706  
700 707 /*
... ... @@ -737,7 +744,7 @@
737 744 */
738 745 if (fec->xcv_type != SEVENWIRE) {
739 746 uint16 phyStatus;
740   - miiphy_read(0, 0x1, &phyStatus);
  747 + miiphy_read(dev->name, 0, 0x1, &phyStatus);
741 748 }
742 749  
743 750 /*
744 751  
... ... @@ -745,11 +752,11 @@
745 752 */
746 753  
747 754 #if (DEBUG & 0x20)
748   - tfifo_print(fec);
  755 + tfifo_print(dev->name, fec);
749 756 #endif
750 757 SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
751 758 #if (DEBUG & 0x20)
752   - tfifo_print(fec);
  759 + tfifo_print(dev->name, fec);
753 760 #endif
754 761 #if (DEBUG & 0x8)
755 762 printf( "+" );
... ... @@ -896,6 +903,11 @@
896 903 sprintf(dev->name, "FEC ETHERNET");
897 904 eth_register(dev);
898 905  
  906 +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
  907 + miiphy_register (dev->name,
  908 + fec5xxx_miiphy_read, fec5xxx_miiphy_write);
  909 +#endif
  910 +
899 911 /*
900 912 * Try to set the mac address now. The fec mac address is
901 913 * a garbage after reset. When not using fec for booting
902 914  
... ... @@ -912,12 +924,13 @@
912 924 }
913 925  
914 926 mpc5xxx_fec_init_phy(dev, bis);
  927 +
915 928 return 1;
916 929 }
917 930  
918 931 /* MII-interface related functions */
919 932 /********************************************************************/
920   -int miiphy_read(uint8 phyAddr, uint8 regAddr, uint16 * retVal)
  933 +int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal)
921 934 {
922 935 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
923 936 uint32 reg; /* convenient holder for the PHY register */
... ... @@ -959,7 +972,7 @@
959 972 }
960 973  
961 974 /********************************************************************/
962   -int miiphy_write(uint8 phyAddr, uint8 regAddr, uint16 data)
  975 +int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data)
963 976 {
964 977 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
965 978 uint32 reg; /* convenient holder for the PHY register */
... ... @@ -18,11 +18,13 @@
18 18 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
19 19 defined(CONFIG_MPC8220_FEC)
20 20  
21   -/*#if (CONFIG_COMMANDS & CFG_CMD_NET)*/
  21 +#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
  22 +#error "CONFIG_MII has to be defined!"
  23 +#endif
22 24  
23 25 #ifdef DEBUG
24   -static void tfifo_print (mpc8220_fec_priv * fec);
25   -static void rfifo_print (mpc8220_fec_priv * fec);
  26 +static void tfifo_print (char *devname, mpc8220_fec_priv * fec);
  27 +static void rfifo_print (char *devname, mpc8220_fec_priv * fec);
26 28 #endif /* DEBUG */
27 29  
28 30 #ifdef DEBUG
29 31  
... ... @@ -36,9 +38,12 @@
36 38 u8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
37 39 } NBUF;
38 40  
  41 +int fec8220_miiphy_read (char *devname, u8 phyAddr, u8 regAddr, u16 * retVal);
  42 +int fec8220_miiphy_write (char *devname, u8 phyAddr, u8 regAddr, u16 data);
  43 +
39 44 /********************************************************************/
40 45 #ifdef DEBUG
41   -static void mpc8220_fec_phydump (void)
  46 +static void mpc8220_fec_phydump (char *devname)
42 47 {
43 48 u16 phyStatus, i;
44 49 u8 phyAddr = CONFIG_PHY_ADDR;
... ... @@ -56,7 +61,7 @@
56 61  
57 62 for (i = 0; i < 32; i++) {
58 63 if (reg_mask[i]) {
59   - miiphy_read (phyAddr, i, &phyStatus);
  64 + miiphy_read (devname, phyAddr, i, &phyStatus);
60 65 printf ("Mii reg %d: 0x%04x\n", i, phyStatus);
61 66 }
62 67 }
... ... @@ -400,7 +405,7 @@
400 405 /*
401 406 * Reset PHY, then delay 300ns
402 407 */
403   - miiphy_write (phyAddr, 0x0, 0x8000);
  408 + miiphy_write (dev->name, phyAddr, 0x0, 0x8000);
404 409 udelay (1000);
405 410  
406 411 if (fec->xcv_type == MII10) {
407 412  
... ... @@ -410,11 +415,11 @@
410 415 #ifdef DEBUG
411 416 printf ("Forcing 10 Mbps ethernet link... ");
412 417 #endif
413   - miiphy_read (phyAddr, 0x1, &phyStatus);
  418 + miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
414 419 /*
415 420 miiphy_write(fec, phyAddr, 0x0, 0x0100);
416 421 */
417   - miiphy_write (phyAddr, 0x0, 0x0180);
  422 + miiphy_write (dev->name, phyAddr, 0x0, 0x0180);
418 423  
419 424 timeout = 20;
420 425 do { /* wait for link status to go down */
... ... @@ -425,7 +430,7 @@
425 430 #endif
426 431 break;
427 432 }
428   - miiphy_read (phyAddr, 0x1, &phyStatus);
  433 + miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
429 434 #ifdef DEBUG
430 435 printf ("=");
431 436 #endif
... ... @@ -438,7 +443,7 @@
438 443 printf ("failed. Link is down.\n");
439 444 break;
440 445 }
441   - miiphy_read (phyAddr, 0x1, &phyStatus);
  446 + miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
442 447 #ifdef DEBUG
443 448 printf ("+");
444 449 #endif
445 450  
... ... @@ -451,12 +456,12 @@
451 456 /*
452 457 * Set the auto-negotiation advertisement register bits
453 458 */
454   - miiphy_write (phyAddr, 0x4, 0x01e1);
  459 + miiphy_write (dev->name, phyAddr, 0x4, 0x01e1);
455 460  
456 461 /*
457 462 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
458 463 */
459   - miiphy_write (phyAddr, 0x0, 0x1200);
  464 + miiphy_write (dev->name, phyAddr, 0x0, 0x1200);
460 465  
461 466 /*
462 467 * Wait for AN completion
... ... @@ -472,7 +477,7 @@
472 477 return -1;
473 478 }
474 479  
475   - if (miiphy_read (phyAddr, 0x1, &phyStatus) !=
  480 + if (miiphy_read (dev->name, phyAddr, 0x1, &phyStatus) !=
476 481 0) {
477 482 #ifdef DEBUG
478 483 printf ("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
... ... @@ -495,7 +500,7 @@
495 500  
496 501 #ifdef DEBUG
497 502 if (fec->xcv_type != SEVENWIRE)
498   - mpc8220_fec_phydump ();
  503 + mpc8220_fec_phydump (dev->name);
499 504 #endif
500 505  
501 506 /*
... ... @@ -518,7 +523,7 @@
518 523  
519 524 #ifdef DEBUG
520 525 if (fec->xcv_type != SEVENWIRE)
521   - mpc8220_fec_phydump ();
  526 + mpc8220_fec_phydump (dev->name);
522 527 #endif
523 528  
524 529 /*
... ... @@ -573,7 +578,7 @@
573 578 #ifdef DEBUG
574 579 /********************************************************************/
575 580  
576   -static void tfifo_print (mpc8220_fec_priv * fec)
  581 +static void tfifo_print (char *devname, mpc8220_fec_priv * fec)
577 582 {
578 583 u16 phyAddr = CONFIG_PHY_ADDR;
579 584 u16 phyStatus;
... ... @@ -581,7 +586,7 @@
581 586 if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
582 587 || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
583 588  
584   - miiphy_read (phyAddr, 0x1, &phyStatus);
  589 + miiphy_read (devname, phyAddr, 0x1, &phyStatus);
585 590 printf ("\nphyStatus: 0x%04x\n", phyStatus);
586 591 printf ("ecntrl: 0x%08x\n", fec->eth->ecntrl);
587 592 printf ("ievent: 0x%08x\n", fec->eth->ievent);
... ... @@ -597,7 +602,7 @@
597 602 }
598 603 }
599 604  
600   -static void rfifo_print (mpc8220_fec_priv * fec)
  605 +static void rfifo_print (char *devname, mpc8220_fec_priv * fec)
601 606 {
602 607 u16 phyAddr = CONFIG_PHY_ADDR;
603 608 u16 phyStatus;
... ... @@ -605,7 +610,7 @@
605 610 if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
606 611 || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
607 612  
608   - miiphy_read (phyAddr, 0x1, &phyStatus);
  613 + miiphy_read (devname, phyAddr, 0x1, &phyStatus);
609 614 printf ("\nphyStatus: 0x%04x\n", phyStatus);
610 615 printf ("ecntrl: 0x%08x\n", fec->eth->ecntrl);
611 616 printf ("ievent: 0x%08x\n", fec->eth->ievent);
... ... @@ -636,7 +641,7 @@
636 641  
637 642 #ifdef DEBUG
638 643 printf ("tbd status: 0x%04x\n", fec->tbdBase[0].status);
639   - tfifo_print (fec);
  644 + tfifo_print (dev->name, fec);
640 645 #endif
641 646  
642 647 /*
... ... @@ -680,7 +685,7 @@
680 685 if (fec->xcv_type != SEVENWIRE) {
681 686 u16 phyStatus;
682 687  
683   - miiphy_read (0, 0x1, &phyStatus);
  688 + miiphy_read (dev->name, 0, 0x1, &phyStatus);
684 689 }
685 690  
686 691 /*
687 692  
... ... @@ -688,13 +693,13 @@
688 693 */
689 694  
690 695 #ifdef DEBUG
691   - tfifo_print (fec);
  696 + tfifo_print (dev->name, fec);
692 697 #endif
693 698  
694 699 DMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
695 700  
696 701 #ifdef DEBUG
697   - tfifo_print (fec);
  702 + tfifo_print (dev->name, fec);
698 703 #endif
699 704  
700 705 #ifdef DEBUG
... ... @@ -842,6 +847,11 @@
842 847 sprintf (dev->name, "FEC ETHERNET");
843 848 eth_register (dev);
844 849  
  850 +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
  851 + miiphy_register (dev->name,
  852 + fec8220_miiphy_read, fec8220_miiphy_write);
  853 +#endif
  854 +
845 855 /*
846 856 * Try to set the mac address now. The fec mac address is
847 857 * a garbage after reset. When not using fec for booting
... ... @@ -875,7 +885,7 @@
875 885  
876 886 /* MII-interface related functions */
877 887 /********************************************************************/
878   -int miiphy_read (u8 phyAddr, u8 regAddr, u16 * retVal)
  888 +int fec8220_miiphy_read (char *devname, u8 phyAddr, u8 regAddr, u16 * retVal)
879 889 {
880 890 ethernet_regs *eth = (ethernet_regs *) MMAP_FEC1;
881 891 u32 reg; /* convenient holder for the PHY register */
... ... @@ -919,7 +929,7 @@
919 929 }
920 930  
921 931 /********************************************************************/
922   -int miiphy_write (u8 phyAddr, u8 regAddr, u16 data)
  932 +int fec8220_miiphy_write (char *devname, u8 phyAddr, u8 regAddr, u16 data)
923 933 {
924 934 ethernet_regs *eth = (ethernet_regs *) MMAP_FEC1;
925 935 u32 reg; /* convenient holder for the PHY register */
cpu/mpc8260/ether_fcc.c
Diff comments   View file @ d9f2f50
... ... @@ -47,6 +47,10 @@
47 47 #include <config.h>
48 48 #include <net.h>
49 49  
  50 +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
  51 +#include <miiphy.h>
  52 +#endif
  53 +
50 54 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \
51 55 defined(CONFIG_NET_MULTI)
52 56  
... ... @@ -386,6 +390,12 @@
386 390 dev->recv = fec_recv;
387 391  
388 392 eth_register(dev);
  393 +
  394 +#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) \
  395 + && defined(CONFIG_BITBANGMII)
  396 + miiphy_register(dev->name,
  397 + bb_miiphy_read, bb_miiphy_write);
  398 +#endif
389 399 }
390 400  
391 401 return 1;
cpu/mpc85xx/ether_fcc.c
Diff comments   View file @ d9f2f50
... ... @@ -48,6 +48,10 @@
48 48 #include <config.h>
49 49 #include <net.h>
50 50  
  51 +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
  52 +#include <miiphy.h>
  53 +#endif
  54 +
51 55 #if defined(CONFIG_CPM2)
52 56  
53 57 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \
... ... @@ -451,6 +455,12 @@
451 455 dev->recv = fec_recv;
452 456  
453 457 eth_register(dev);
  458 +
  459 +#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) \
  460 + && defined(CONFIG_BITBANGMII)
  461 + miiphy_register(dev->name,
  462 + bb_miiphy_read, bb_miiphy_write);
  463 +#endif
454 464 }
455 465  
456 466 return 1;
... ... @@ -46,8 +46,13 @@
46 46  
47 47 #if defined(WANT_MII)
48 48 #include <miiphy.h>
  49 +
  50 +#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
  51 +#error "CONFIG_MII has to be defined!"
49 52 #endif
50 53  
  54 +#endif
  55 +
51 56 #if defined(CONFIG_RMII) && !defined(WANT_MII)
52 57 #error RMII support is unusable without a working PHY.
53 58 #endif
... ... @@ -56,6 +61,11 @@
56 61 static int mii_discover_phy(struct eth_device *dev);
57 62 #endif
58 63  
  64 +int fec8xx_miiphy_read(char *devname, unsigned char addr,
  65 + unsigned char reg, unsigned short *value);
  66 +int fec8xx_miiphy_write(char *devname, unsigned char addr,
  67 + unsigned char reg, unsigned short value);
  68 +
59 69 static struct ether_fcc_info_s
60 70 {
61 71 int ether_index;
... ... @@ -169,6 +179,11 @@
169 179 dev->recv = fec_recv;
170 180  
171 181 eth_register(dev);
  182 +
  183 +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
  184 + miiphy_register(dev->name,
  185 + fec8xx_miiphy_read, fec8xx_miiphy_write);
  186 +#endif
172 187 }
173 188 return 1;
174 189 }
... ... @@ -712,7 +727,7 @@
712 727 /*
713 728 * adapt the RMII speed to the speed of the phy
714 729 */
715   - if (miiphy_speed (efis->actual_phy_addr) == _100BASET) {
  730 + if (miiphy_speed (dev->name, efis->actual_phy_addr) == _100BASET) {
716 731 fec_100Mbps (dev);
717 732 } else {
718 733 fec_10Mbps (dev);
... ... @@ -723,7 +738,7 @@
723 738 /*
724 739 * adapt to the half/full speed settings
725 740 */
726   - if (miiphy_duplex (efis->actual_phy_addr) == FULL) {
  741 + if (miiphy_duplex (dev->name, efis->actual_phy_addr) == FULL) {
727 742 fec_full_duplex (dev);
728 743 } else {
729 744 fec_half_duplex (dev);
... ... @@ -969,7 +984,8 @@
969 984 * Otherwise they hang in mii_send() !!! Sorry!
970 985 *****************************************************************************/
971 986  
972   -int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value)
  987 +int fec8xx_miiphy_read(char *devname, unsigned char addr,
  988 + unsigned char reg, unsigned short *value)
973 989 {
974 990 short rdreg; /* register working value */
975 991  
... ... @@ -985,7 +1001,8 @@
985 1001 return 0;
986 1002 }
987 1003  
988   -int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
  1004 +int fec8xx_miiphy_write(char *devname, unsigned char addr,
  1005 + unsigned char reg, unsigned short value)
989 1006 {
990 1007 short rdreg; /* register working value */
991 1008 #ifdef MII_DEBUG
cpu/ppc4xx/4xx_enet.c
Diff comments   View file @ d9f2f50
... ... @@ -167,6 +167,11 @@
167 167 unsigned long mal_errr);
168 168 static void emac_err (struct eth_device *dev, unsigned long isr);
169 169  
  170 +extern int phy_setup_aneg (char *devname, unsigned char addr);
  171 +extern int emac4xx_miiphy_read (char *devname, unsigned char addr,
  172 + unsigned char reg, unsigned short *value);
  173 +extern int emac4xx_miiphy_write (char *devname, unsigned char addr,
  174 + unsigned char reg, unsigned short value);
170 175  
171 176 /*-----------------------------------------------------------------------------+
172 177 | ppc_4xx_eth_halt
... ... @@ -206,9 +211,6 @@
206 211 return;
207 212 }
208 213  
209   -extern int phy_setup_aneg (unsigned char addr);
210   -extern int miiphy_reset (unsigned char addr);
211   -
212 214 #if defined (CONFIG_440GX)
213 215 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
214 216 {
... ... @@ -462,7 +464,7 @@
462 464 * otherwise, just check the speeds & feeds
463 465 */
464 466 if (hw_p->first_init == 0) {
465   - miiphy_reset (reg);
  467 + miiphy_reset (dev->name, reg);
466 468  
467 469 #if defined(CONFIG_440GX)
468 470 #if defined(CONFIG_CIS8201_PHY)
469 471  
... ... @@ -472,9 +474,9 @@
472 474 */
473 475 if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) {
474 476 #if defined(CONFIG_CIS8201_SHORT_ETCH)
475   - miiphy_write (reg, 23, 0x1300);
  477 + miiphy_write (dev->name, reg, 23, 0x1300);
476 478 #else
477   - miiphy_write (reg, 23, 0x1000);
  479 + miiphy_write (dev->name, reg, 23, 0x1000);
478 480 #endif
479 481 /*
480 482 * Vitesse VSC8201/Cicada CIS8201 errata:
481 483  
482 484  
... ... @@ -482,26 +484,26 @@
482 484 * This work around (provided by Vitesse) changes
483 485 * the default timer convergence from 8ms to 12ms
484 486 */
485   - miiphy_write (reg, 0x1f, 0x2a30);
486   - miiphy_write (reg, 0x08, 0x0200);
487   - miiphy_write (reg, 0x1f, 0x52b5);
488   - miiphy_write (reg, 0x02, 0x0004);
489   - miiphy_write (reg, 0x01, 0x0671);
490   - miiphy_write (reg, 0x00, 0x8fae);
491   - miiphy_write (reg, 0x1f, 0x2a30);
492   - miiphy_write (reg, 0x08, 0x0000);
493   - miiphy_write (reg, 0x1f, 0x0000);
  487 + miiphy_write (dev->name, reg, 0x1f, 0x2a30);
  488 + miiphy_write (dev->name, reg, 0x08, 0x0200);
  489 + miiphy_write (dev->name, reg, 0x1f, 0x52b5);
  490 + miiphy_write (dev->name, reg, 0x02, 0x0004);
  491 + miiphy_write (dev->name, reg, 0x01, 0x0671);
  492 + miiphy_write (dev->name, reg, 0x00, 0x8fae);
  493 + miiphy_write (dev->name, reg, 0x1f, 0x2a30);
  494 + miiphy_write (dev->name, reg, 0x08, 0x0000);
  495 + miiphy_write (dev->name, reg, 0x1f, 0x0000);
494 496 /* end Vitesse/Cicada errata */
495 497 }
496 498 #endif
497 499 #endif
498 500 /* Start/Restart autonegotiation */
499   - phy_setup_aneg (reg);
  501 + phy_setup_aneg (dev->name, reg);
500 502 udelay (1000);
501 503 }
502 504 #endif /* defined(CONFIG_PHY_RESET) */
503 505  
504   - miiphy_read (reg, PHY_BMSR, &reg_short);
  506 + miiphy_read (dev->name, reg, PHY_BMSR, &reg_short);
505 507  
506 508 /*
507 509 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
... ... @@ -523,7 +525,7 @@
523 525 putc ('.');
524 526 }
525 527 udelay (1000); /* 1 ms */
526   - miiphy_read (reg, PHY_BMSR, &reg_short);
  528 + miiphy_read (dev->name, reg, PHY_BMSR, &reg_short);
527 529  
528 530 }
529 531 puts (" done\n");
... ... @@ -531,8 +533,8 @@
531 533 }
532 534 #endif /* #ifndef CONFIG_CS8952_PHY */
533 535  
534   - speed = miiphy_speed (reg);
535   - duplex = miiphy_duplex (reg);
  536 + speed = miiphy_speed (dev->name, reg);
  537 + duplex = miiphy_duplex (dev->name, reg);
536 538  
537 539 if (hw_p->print_speed) {
538 540 hw_p->print_speed = 0;
... ... @@ -1485,6 +1487,10 @@
1485 1487 #else
1486 1488 emac0_dev = dev;
1487 1489 #endif
  1490 +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
  1491 + miiphy_register (dev->name,
  1492 + emac4xx_miiphy_read, emac4xx_miiphy_write);
  1493 +#endif
1488 1494  
1489 1495 } /* end for each supported device */
1490 1496 return (1);
... ... @@ -1519,6 +1525,16 @@
1519 1525 int eth_rx(void)
1520 1526 {
1521 1527 return (ppc_4xx_eth_rx(emac0_dev));
  1528 +}
  1529 +
  1530 +int emac4xx_miiphy_initialize (bd_t * bis)
  1531 +{
  1532 +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
  1533 + miiphy_register ("ppc_4xx_eth0",
  1534 + emac4xx_miiphy_read, emac4xx_miiphy_write);
  1535 +#endif
  1536 +
  1537 + return 0;
1522 1538 }
1523 1539 #endif /* !defined(CONFIG_NET_MULTI) */
1524 1540  
... ... @@ -55,14 +55,14 @@
55 55 /* Dump out to the screen PHY regs */
56 56 /***********************************************************/
57 57  
58   -void miiphy_dump (unsigned char addr)
  58 +void miiphy_dump (char *devname, unsigned char addr)
59 59 {
60 60 unsigned long i;
61 61 unsigned short data;
62 62  
63 63  
64 64 for (i = 0; i < 0x1A; i++) {
65   - if (miiphy_read (addr, i, &data)) {
  65 + if (miiphy_read (devname, addr, i, &data)) {
66 66 printf ("read error for reg %lx\n", i);
67 67 return;
68 68 }
69 69  
70 70  
71 71  
72 72  
... ... @@ -79,21 +79,21 @@
79 79 /***********************************************************/
80 80 /* (Re)start autonegotiation */
81 81 /***********************************************************/
82   -int phy_setup_aneg (unsigned char addr)
  82 +int phy_setup_aneg (char *devname, unsigned char addr)
83 83 {
84 84 unsigned short ctl, adv;
85 85  
86 86 /* Setup standard advertise */
87   - miiphy_read (addr, PHY_ANAR, &adv);
  87 + miiphy_read (devname, addr, PHY_ANAR, &adv);
88 88 adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 |
89 89 PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
90 90 PHY_ANLPAR_10);
91   - miiphy_write (addr, PHY_ANAR, adv);
  91 + miiphy_write (devname, addr, PHY_ANAR, adv);
92 92  
93 93 /* Start/Restart aneg */
94   - miiphy_read (addr, PHY_BMCR, &ctl);
  94 + miiphy_read (devname, addr, PHY_BMCR, &ctl);
95 95 ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
96   - miiphy_write (addr, PHY_BMCR, ctl);
  96 + miiphy_write (devname, addr, PHY_BMCR, ctl);
97 97  
98 98 return 0;
99 99 }
... ... @@ -142,7 +142,8 @@
142 142 }
143 143  
144 144  
145   -int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
  145 +int emac4xx_miiphy_read (char *devname, unsigned char addr,
  146 + unsigned char reg, unsigned short *value)
146 147 {
147 148 unsigned long sta_reg; /* STA scratch area */
148 149 unsigned long i;
... ... @@ -207,7 +208,8 @@
207 208 /* write a phy reg and return the value with a rc */
208 209 /***********************************************************/
209 210  
210   -int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
  211 +int emac4xx_miiphy_write (char *devname, unsigned char addr,
  212 + unsigned char reg, unsigned short value)
211 213 {
212 214 unsigned long sta_reg; /* STA scratch area */
213 215 unsigned long i;
... ... @@ -26,6 +26,7 @@
26 26 #include <net.h>
27 27 #include <asm/io.h>
28 28 #include <pci.h>
  29 +#include <miiphy.h>
29 30  
30 31 #undef DEBUG
31 32  
32 33  
33 34  
34 35  
35 36  
36 37  
37 38  
38 39  
39 40  
40 41  
41 42  
42 43  
43 44  
44 45  
... ... @@ -271,49 +272,124 @@
271 272 *(volatile u32 *) ((addr + dev->iobase)) = cpu_to_le32 (command);
272 273 }
273 274  
274   -#if defined (CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
  275 +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
275 276 static inline int INL (struct eth_device *dev, u_long addr)
276 277 {
277 278 return le32_to_cpu (*(volatile u32 *) (addr + dev->iobase));
278 279 }
279 280  
280   -int miiphy_read (unsigned char addr,
281   - unsigned char reg,
282   - unsigned short *value)
  281 +static int get_phyreg (struct eth_device *dev, unsigned char addr,
  282 + unsigned char reg, unsigned short *value)
283 283 {
284   - int cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
  284 + int cmd;
  285 + int timeout = 50;
285 286  
286   - struct eth_device *dev = eth_get_dev ();
287   -
  287 + /* read requested data */
  288 + cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
288 289 OUTL (dev, cmd, SCBCtrlMDI);
289 290  
290 291 do {
  292 + udelay(1000);
291 293 cmd = INL (dev, SCBCtrlMDI);
292   - } while (!(cmd & (1 << 28)));
  294 + } while (!(cmd & (1 << 28)) && (--timeout));
293 295  
  296 + if (timeout == 0)
  297 + return -1;
  298 +
294 299 *value = (unsigned short) (cmd & 0xffff);
295 300  
296 301 return 0;
297 302 }
298 303  
299   -int miiphy_write (unsigned char addr,
300   - unsigned char reg,
301   - unsigned short value)
  304 +static int set_phyreg (struct eth_device *dev, unsigned char addr,
  305 + unsigned char reg, unsigned short value)
302 306 {
303   - int cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
  307 + int cmd;
  308 + int timeout = 50;
304 309  
305   - struct eth_device *dev = eth_get_dev ();
306   -
  310 + /* write requested data */
  311 + cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
307 312 OUTL (dev, cmd | value, SCBCtrlMDI);
308 313  
309   - while (!(INL (dev, SCBCtrlMDI) & (1 << 28)));
  314 + while (!(INL (dev, SCBCtrlMDI) & (1 << 28)) && (--timeout))
  315 + udelay(1000);
310 316  
  317 + if (timeout == 0)
  318 + return -1;
  319 +
311 320 return 0;
312 321 }
313   -#endif /* (CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) */
314 322  
315   - /* Wait for the chip get the command.
316   - */
  323 +/* Check if given phyaddr is valid, i.e. there is a PHY connected.
  324 + * Do this by checking model value field from ID2 register.
  325 + */
  326 +static struct eth_device* verify_phyaddr (char *devname, unsigned char addr)
  327 +{
  328 + struct eth_device *dev;
  329 + unsigned short value;
  330 + unsigned char model;
  331 +
  332 + dev = eth_get_dev_by_name(devname);
  333 + if (dev == NULL) {
  334 + printf("%s: no such device\n", devname);
  335 + return NULL;
  336 + }
  337 +
  338 + /* read id2 register */
  339 + if (get_phyreg(dev, addr, PHY_PHYIDR2, &value) != 0) {
  340 + printf("%s: mii read timeout!\n", devname);
  341 + return NULL;
  342 + }
  343 +
  344 + /* get model */
  345 + model = (unsigned char)((value >> 4) & 0x003f);
  346 +
  347 + if (model == 0) {
  348 + printf("%s: no PHY at address %d\n", devname, addr);
  349 + return NULL;
  350 + }
  351 +
  352 + return dev;
  353 +}
  354 +
  355 +static int eepro100_miiphy_read (char *devname, unsigned char addr,
  356 + unsigned char reg, unsigned short *value)
  357 +{
  358 + struct eth_device *dev;
  359 +
  360 + dev = verify_phyaddr(devname, addr);
  361 + if (dev == NULL)
  362 + return -1;
  363 +
  364 + if (get_phyreg(dev, addr, reg, value) != 0) {
  365 + printf("%s: mii read timeout!\n", devname);
  366 + return -1;
  367 + }
  368 +
  369 + return 0;
  370 +}
  371 +
  372 +static int eepro100_miiphy_write (char *devname, unsigned char addr,
  373 + unsigned char reg, unsigned short value)
  374 +{
  375 + struct eth_device *dev;
  376 +
  377 + dev = verify_phyaddr(devname, addr);
  378 + if (dev == NULL)
  379 + return -1;
  380 +
  381 + if (set_phyreg(dev, addr, reg, value) != 0) {
  382 + printf("%s: mii write timeout!\n", devname);
  383 + return -1;
  384 + }
  385 +
  386 + return 0;
  387 +}
  388 +
  389 +#endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) */
  390 +
  391 +/* Wait for the chip get the command.
  392 +*/
317 393 static int wait_for_eepro100 (struct eth_device *dev)
318 394 {
319 395 int i;
... ... @@ -385,6 +461,12 @@
385 461 dev->recv = eepro100_recv;
386 462  
387 463 eth_register (dev);
  464 +
  465 +#if defined (CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
  466 + /* register mii command access routines */
  467 + miiphy_register(dev->name,
  468 + eepro100_miiphy_read, eepro100_miiphy_write);
  469 +#endif
388 470  
389 471 card_number++;
390 472  
drivers/ns7520_eth.c
Diff comments   View file @ d9f2f50
... ... @@ -767,8 +767,8 @@
767 767 /**
768 768 * Read a 16-bit value from an MII register.
769 769 */
770   -extern int miiphy_read(unsigned char const addr, unsigned char const reg,
771   - unsigned short *const value)
  770 +extern int ns7520_miiphy_read(char *devname, unsigned char const addr,
  771 + unsigned char const reg, unsigned short *const value)
772 772 {
773 773 int ret = MII_STATUS_FAILURE;
774 774  
... ... @@ -813,8 +813,8 @@
813 813 /**
814 814 * Write a 16-bit value to an MII register.
815 815 */
816   -extern int miiphy_write(unsigned char const addr, unsigned char const reg,
817   - unsigned short const value)
  816 +extern int ns7520_miiphy_write(char *devname, unsigned char const addr,
  817 + unsigned char const reg, unsigned short const value)
818 818 {
819 819 int ret = MII_STATUS_FAILURE;
820 820  
... ... @@ -847,4 +847,14 @@
847 847 }
848 848 #endif /* defined(CONFIG_MII) */
849 849 #endif /* CONFIG_DRIVER_NS7520_ETHERNET */
  850 +
  851 +int ns7520_miiphy_initialize(bd_t *bis)
  852 +{
  853 +#if defined(CONFIG_DRIVER_NS7520_ETHERNET)
  854 +#if defined(CONFIG_MII)
  855 + miiphy_register("ns7520phy", ns7520_miiphy_read, ns7520_miiphy_write);
  856 +#endif
  857 +#endif
  858 + return 0;
  859 +}
... ... @@ -21,8 +21,9 @@
21 21  
22 22 #if defined(CONFIG_TSEC_ENET)
23 23 #include "tsec.h"
  24 +#include "miiphy.h"
24 25  
25   -#define TX_BUF_CNT 2
  26 +#define TX_BUF_CNT 2
26 27  
27 28 static uint rxIdx; /* index of the current RX buffer */
28 29 static uint txIdx; /* index of the current TX buffer */
... ... @@ -120,6 +121,10 @@
120 121 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
121 122 static void adjust_link(struct eth_device *dev);
122 123 static void relocate_cmds(void);
  124 +static int tsec_miiphy_write(char *devname, unsigned char addr,
  125 + unsigned char reg, unsigned short value);
  126 +static int tsec_miiphy_read(char *devname, unsigned char addr,
  127 + unsigned char reg, unsigned short *value);
123 128  
124 129 /* Initialize device structure. Returns success if PHY
125 130 * initialization succeeded (i.e. if it recognizes the PHY)
... ... @@ -169,6 +174,11 @@
169 174 priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
170 175 priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
171 176  
  177 +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \
  178 + && !defined(BITBANGMII)
  179 + miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
  180 +#endif
  181 +
172 182 /* Try to initialize PHY here, and return */
173 183 return init_phy(dev);
174 184 }
... ... @@ -1058,7 +1068,8 @@
1058 1068 }
1059 1069  
1060 1070  
1061   -#ifndef CONFIG_BITBANGMII
  1071 +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \
  1072 + && !defined(BITBANGMII)
1062 1073  
1063 1074 struct tsec_private * get_priv_for_phy(unsigned char phyaddr)
1064 1075 {
... ... @@ -1078,7 +1089,8 @@
1078 1089 * Returns:
1079 1090 * 0 on success
1080 1091 */
1081   -int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value)
  1092 +static int tsec_miiphy_read(char *devname, unsigned char addr,
  1093 + unsigned char reg, unsigned short *value)
1082 1094 {
1083 1095 unsigned short ret;
1084 1096 struct tsec_private *priv = get_priv_for_phy(addr);
... ... @@ -1100,7 +1112,8 @@
1100 1112 * Returns:
1101 1113 * 0 on success
1102 1114 */
1103   -int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
  1115 +static int tsec_miiphy_write(char *devname, unsigned char addr,
  1116 + unsigned char reg, unsigned short value)
1104 1117 {
1105 1118 struct tsec_private *priv = get_priv_for_phy(addr);
1106 1119  
... ... @@ -1114,7 +1127,8 @@
1114 1127 return 0;
1115 1128 }
1116 1129  
1117   -#endif /* CONFIG_BITBANGMII */
  1130 +#endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
  1131 + && !defined(BITBANGMII) */
1118 1132  
1119 1133 #endif /* CONFIG_TSEC_ENET */
include/configs/Alaska8220.h
Diff comments   View file @ d9f2f50
... ... @@ -90,6 +90,7 @@
90 90 CFG_CMD_SNTP )
91 91  
92 92 #define CONFIG_NET_MULTI
  93 +#define CONFIG_MII
93 94  
94 95 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
95 96 #include <cmd_confdefs.h>
include/configs/IAD210.h
Diff comments   View file @ d9f2f50
... ... @@ -88,6 +88,7 @@
88 88  
89 89 # undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
90 90 # define CONFIG_FEC_ENET 1 /* use FEC ethernet */
  91 +# define CONFIG_MII 1
91 92 # define CFG_DISCOVER_PHY 1
92 93 # define CONFIG_FEC_UTOPIA 1
93 94 # define CONFIG_ETHADDR 08:00:06:26:A2:6D
include/configs/ICU862.h
Diff comments   View file @ d9f2f50
... ... @@ -85,6 +85,7 @@
85 85  
86 86 #undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
87 87 #define CONFIG_FEC_ENET 1 /* use FEC ethernet */
  88 +#define CONFIG_MII 1
88 89 #if 1
89 90 #define CFG_DISCOVER_PHY 1
90 91 #else
include/configs/IceCube.h
Diff comments   View file @ d9f2f50
... ... @@ -71,6 +71,7 @@
71 71 #define CFG_XLB_PIPELINING 1
72 72  
73 73 #define CONFIG_NET_MULTI 1
  74 +#define CONFIG_MII 1
74 75 #define CONFIG_EEPRO100 1
75 76 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
76 77 #define CONFIG_NS8382X 1
... ... @@ -79,6 +80,7 @@
79 80  
80 81 #else /* MPC5100 */
81 82  
  83 +#define CONFIG_MII 1
82 84 #define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
83 85  
84 86 #endif
include/configs/KUP4K.h
Diff comments   View file @ d9f2f50
... ... @@ -141,6 +141,7 @@
141 141 #define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
142 142  
143 143 #define CFG_DISCOVER_PHY
  144 +#define CONFIG_MII
144 145  
145 146 #if 0
146 147 #define CONFIG_ETHADDR 00:0B:64:00:00:00 /* our OUI from IEEE */
include/configs/KUP4X.h
Diff comments   View file @ d9f2f50
... ... @@ -150,6 +150,7 @@
150 150 #define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
151 151  
152 152 #define CFG_DISCOVER_PHY
  153 +#define CONFIG_MII
153 154  
154 155 #if 0
155 156 #define CONFIG_ETHADDR 00:0B:64:80:00:00 /* our OUI from IEEE */
include/configs/MPC8560ADS.h
Diff comments   View file @ d9f2f50
... ... @@ -43,7 +43,9 @@
43 43  
44 44 #define CONFIG_PCI
45 45 #define CONFIG_TSEC_ENET /* tsec ethernet support */
  46 +#undef CONFIG_TSEC_ENET /* tsec ethernet support */
46 47 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
  48 +#define CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
47 49 #define CONFIG_ENV_OVERWRITE
48 50 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
49 51 #define CONFIG_DDR_DLL /* possible DLL fix needed */
include/configs/PM520.h
Diff comments   View file @ d9f2f50
... ... @@ -72,6 +72,7 @@
72 72 #define CONFIG_PCI_IO_SIZE 0x01000000
73 73  
74 74 #define CONFIG_NET_MULTI 1
  75 +#define CONFIG_MII 1
75 76 #define CONFIG_EEPRO100 1
76 77 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
77 78 #undef CONFIG_NS8382X
include/configs/PM854.h
Diff comments   View file @ d9f2f50
... ... @@ -235,7 +235,7 @@
235 235 #define CONFIG_NET_MULTI
236 236 #define CONFIG_PCI_PNP /* do pci plug-and-play */
237 237  
238   -/* #define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled */
  238 +#define CONFIG_EEPRO100
239 239 #define CONFIG_E1000
240 240 #undef CONFIG_TULIP
241 241  
include/configs/QS860T.h
Diff comments   View file @ d9f2f50
... ... @@ -56,6 +56,7 @@
56 56 #define CONFIG_QS860T 1 /* ...on a QS860T module */
57 57  
58 58 #define CONFIG_FEC_ENET 1 /* FEC 10/100BaseT ethernet */
  59 +#define CONFIG_MII
59 60 #define FEC_INTERRUPT SIU_LEVEL1
60 61 #undef CONFIG_SCC1_ENET /* SCC1 10BaseT ethernet */
61 62 #define CFG_DISCOVER_PHY
include/configs/SXNI855T.h
Diff comments   View file @ d9f2f50
... ... @@ -142,6 +142,7 @@
142 142 # define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
143 143  
144 144 #define CONFIG_FEC_ENET 1 /* use FEC ethernet */
  145 +#define CONFIG_MII 1
145 146  
146 147 #define CFG_DISCOVER_PHY
147 148  
include/configs/TQM5200.h
Diff comments   View file @ d9f2f50
... ... @@ -83,7 +83,7 @@
83 83 #define CONFIG_PCI_IO_SIZE 0x01000000
84 84  
85 85 #define CONFIG_NET_MULTI 1
86   -/* #define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled */
  86 +#define CONFIG_EEPRO100
87 87 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
88 88 #define CONFIG_NS8382X 1
89 89 #endif /* CONFIG_STK52XX */
include/configs/TQM834x.h
Diff comments   View file @ d9f2f50
... ... @@ -280,6 +280,7 @@
280 280  
281 281  
282 282 #undef CONFIG_EEPRO100
  283 +#define CONFIG_EEPRO100
283 284 #undef CONFIG_TULIP
284 285  
285 286 #if !defined(CONFIG_PCI_PNP)
include/configs/TQM8560.h
Diff comments   View file @ d9f2f50
... ... @@ -283,7 +283,7 @@
283 283 #define CONFIG_NET_MULTI
284 284 #define CONFIG_PCI_PNP /* do pci plug-and-play */
285 285  
286   -/* #define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled */
  286 +#define CONFIG_EEPRO100
287 287 #undef CONFIG_TULIP
288 288  
289 289 #if !defined(CONFIG_PCI_PNP)
include/configs/Total5200.h
Diff comments   View file @ d9f2f50
... ... @@ -100,6 +100,7 @@
100 100 #define CONFIG_PCI_IO_SIZE 0x01000000
101 101  
102 102 #define CONFIG_NET_MULTI 1
  103 +#define CONFIG_MII 1
103 104 #define CONFIG_EEPRO100 1
104 105 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
105 106 #define CONFIG_NS8382X 1
... ... @@ -108,6 +109,7 @@
108 109  
109 110 #else /* MGT5100 */
110 111  
  112 +#define CONFIG_MII 1
111 113 #define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
112 114  
113 115 #endif
include/configs/Yukon8220.h
Diff comments   View file @ d9f2f50
... ... @@ -90,6 +90,7 @@
90 90 CFG_CMD_SNTP )
91 91  
92 92 #define CONFIG_NET_MULTI
  93 +#define CONFIG_MII
93 94  
94 95 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
95 96 #include <cmd_confdefs.h>
include/configs/at91rm9200dk.h
Diff comments   View file @ d9f2f50
... ... @@ -98,7 +98,7 @@
98 98 /* #define CONFIG_ENV_OVERWRITE 1 */
99 99  
100 100 #define CONFIG_COMMANDS \
101   - ((CONFIG_CMD_DFL | \
  101 + ((CONFIG_CMD_DFL | CFG_CMD_MII |\
102 102 CFG_CMD_DHCP ) & \
103 103 ~(CFG_CMD_BDI | \
104 104 CFG_CMD_IMI | \
include/configs/cpci5200.h
Diff comments   View file @ d9f2f50
... ... @@ -83,6 +83,8 @@
83 83 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
84 84 #define CONFIG_PCI_IO_SIZE 0x01000000
85 85 #endif
  86 +
  87 +#define CONFIG_MII
86 88 #if 0 /* test-only !!! */
87 89 #define CONFIG_NET_MULTI 1
88 90 #define CONFIG_EEPRO100 1
include/configs/o2dnt.h
Diff comments   View file @ d9f2f50
... ... @@ -69,7 +69,7 @@
69 69 #define CFG_XLB_PIPELINING 1
70 70  
71 71 #define CONFIG_NET_MULTI 1
72   -/* #define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled */
  72 +#define CONFIG_EEPRO100
73 73 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
74 74 #define CONFIG_NS8382X 1
75 75  
include/configs/pf5200.h
Diff comments   View file @ d9f2f50
... ... @@ -83,6 +83,7 @@
83 83 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
84 84 #define CONFIG_PCI_IO_SIZE 0x01000000
85 85  
  86 +#define CONFIG_MII 1
86 87 #if 0 /* test-only !!! */
87 88 #define CONFIG_NET_MULTI 1
88 89 #define CONFIG_EEPRO100 1
... ... @@ -38,18 +38,38 @@
38 38 #ifndef _miiphy_h_
39 39 #define _miiphy_h_
40 40  
  41 +#include <net.h>
41 42  
42   -int miiphy_read(unsigned char addr, unsigned char reg, unsigned short * value);
43   -int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value);
44   -int miiphy_info(unsigned char addr, unsigned int *oui, unsigned char *model,
45   - unsigned char *rev);
46   -int miiphy_reset(unsigned char addr);
47   -int miiphy_speed(unsigned char addr);
48   -int miiphy_duplex(unsigned char addr);
  43 +int miiphy_read(char *devname, unsigned char addr, unsigned char reg,
  44 + unsigned short *value);
  45 +int miiphy_write(char *devname, unsigned char addr, unsigned char reg,
  46 + unsigned short value);
  47 +int miiphy_info(char *devname, unsigned char addr, unsigned int *oui,
  48 + unsigned char *model, unsigned char *rev);
  49 +int miiphy_reset(char *devname, unsigned char addr);
  50 +int miiphy_speed(char *devname, unsigned char addr);
  51 +int miiphy_duplex(char *devname, unsigned char addr);
49 52 #ifdef CFG_FAULT_ECHO_LINK_DOWN
50   -int miiphy_link(unsigned char addr);
  53 +int miiphy_link(char *devname, unsigned char addr);
51 54 #endif
52 55  
  56 +void miiphy_register(char *devname,
  57 + int (* read)(char *devname, unsigned char addr,
  58 + unsigned char reg, unsigned short *value),
  59 + int (* write)(char *devname, unsigned char addr,
  60 + unsigned char reg, unsigned short value));
  61 +
  62 +int miiphy_set_current_dev(char *devname);
  63 +char *miiphy_get_current_dev(void);
  64 +
  65 +void miiphy_listdev(void);
  66 +
  67 +#define BB_MII_DEVNAME "bbmii"
  68 +
  69 +int bb_miiphy_read (char *devname, unsigned char addr,
  70 + unsigned char reg, unsigned short *value);
  71 +int bb_miiphy_write (char *devname, unsigned char addr,
  72 + unsigned char reg, unsigned short value);
53 73  
54 74 /* phy seed setup */
55 75 #define AUTO 99
... ... @@ -114,6 +114,7 @@
114 114 extern void eth_set_current(void); /* set nterface to ethcur var. */
115 115 #endif
116 116 extern struct eth_device *eth_get_dev(void); /* get the current device MAC */
  117 +extern struct eth_device *eth_get_dev_by_name(char *devname); /* get device */
117 118 extern int eth_get_dev_index (void); /* get the device index */
118 119 extern void eth_set_enetaddr(int num, char* a); /* Set new MAC address */
119 120  
... ... @@ -345,8 +345,10 @@
345 345 #ifdef BOARD_LATE_INIT
346 346 board_late_init ();
347 347 #endif
348   -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
  348 +#if (CONFIG_COMMANDS & CFG_CMD_NET)
  349 +#if defined(CONFIG_NET_MULTI)
349 350 puts ("Net: ");
  351 +#endif
350 352 eth_initialize(gd->bd);
351 353 #endif
352 354 /* main_loop() can return to retry autoboot, if so just run it again. */
... ... @@ -317,15 +317,6 @@
317 317 misc_init_r();
318 318 #endif
319 319  
320   -
321   -#if (CONFIG_COMMANDS & CFG_CMD_NET) && (0)
322   - WATCHDOG_RESET();
323   -# ifdef DEBUG
324   - puts ("Reset Ethernet PHY\n");
325   -# endif
326   - reset_phy();
327   -#endif
328   -
329 320 #if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) && !(CONFIG_COMMANDS & CFG_CMD_IDE)
330 321 WATCHDOG_RESET();
331 322 puts ("PCMCIA:");
332 323  
333 324  
... ... @@ -387,10 +378,20 @@
387 378 doc_init();
388 379 #endif
389 380  
390   -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
  381 +#if (CONFIG_COMMANDS & CFG_CMD_NET)
  382 +#if defined(CONFIG_NET_MULTI)
391 383 WATCHDOG_RESET();
392 384 puts("Net: ");
  385 +#endif
393 386 eth_initialize(gd->bd);
  387 +#endif
  388 +
  389 +#if (CONFIG_COMMANDS & CFG_CMD_NET) && (0)
  390 + WATCHDOG_RESET();
  391 +# ifdef DEBUG
  392 + puts ("Reset Ethernet PHY\n");
  393 +# endif
  394 + reset_phy();
394 395 #endif
395 396  
396 397 #ifdef CONFIG_LAST_STAGE_INIT
... ... @@ -414,8 +414,10 @@
414 414 misc_init_r ();
415 415 #endif
416 416  
417   -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
  417 +#if (CONFIG_COMMANDS & CFG_CMD_NET)
  418 +#if defined(CONFIG_NET_MULTI)
418 419 puts ("Net: ");
  420 +#endif
419 421 eth_initialize(gd->bd);
420 422 #endif
421 423  
... ... @@ -899,27 +899,6 @@
899 899 hermes_start_lxt980 ((int) bd->bi_ethspeed);
900 900 #endif
901 901  
902   -#if (CONFIG_COMMANDS & CFG_CMD_NET) && ( \
903   - defined(CONFIG_CCM) || \
904   - defined(CONFIG_ELPT860) || \
905   - defined(CONFIG_EP8260) || \
906   - defined(CONFIG_IP860) || \
907   - defined(CONFIG_IVML24) || \
908   - defined(CONFIG_IVMS8) || \
909   - defined(CONFIG_MPC8260ADS) || \
910   - defined(CONFIG_MPC8266ADS) || \
911   - defined(CONFIG_MPC8560ADS) || \
912   - defined(CONFIG_PCU_E) || \
913   - defined(CONFIG_RPXSUPER) || \
914   - defined(CONFIG_STXGP3) || \
915   - defined(CONFIG_SPD823TS) || \
916   - defined(CONFIG_RESET_PHY_R) )
917   -
918   - WATCHDOG_RESET ();
919   - debug ("Reset Ethernet PHY\n");
920   - reset_phy ();
921   -#endif
922   -
923 902 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
924 903 WATCHDOG_RESET ();
925 904 puts ("KGDB: ");
926 905  
927 906  
... ... @@ -978,10 +957,33 @@
978 957 nand_init(); /* go init the NAND */
979 958 #endif
980 959  
981   -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
  960 +#if (CONFIG_COMMANDS & CFG_CMD_NET)
  961 +#if defined(CONFIG_NET_MULTI)
982 962 WATCHDOG_RESET ();
983 963 puts ("Net: ");
  964 +#endif
984 965 eth_initialize (bd);
  966 +#endif
  967 +
  968 +#if (CONFIG_COMMANDS & CFG_CMD_NET) && ( \
  969 + defined(CONFIG_CCM) || \
  970 + defined(CONFIG_ELPT860) || \
  971 + defined(CONFIG_EP8260) || \
  972 + defined(CONFIG_IP860) || \
  973 + defined(CONFIG_IVML24) || \
  974 + defined(CONFIG_IVMS8) || \
  975 + defined(CONFIG_MPC8260ADS) || \
  976 + defined(CONFIG_MPC8266ADS) || \
  977 + defined(CONFIG_MPC8560ADS) || \
  978 + defined(CONFIG_PCU_E) || \
  979 + defined(CONFIG_RPXSUPER) || \
  980 + defined(CONFIG_STXGP3) || \
  981 + defined(CONFIG_SPD823TS) || \
  982 + defined(CONFIG_RESET_PHY_R) )
  983 +
  984 + WATCHDOG_RESET ();
  985 + debug ("Reset Ethernet PHY\n");
  986 + reset_phy ();
985 987 #endif
986 988  
987 989 #ifdef CONFIG_POST
... ... @@ -60,6 +60,26 @@
60 60 return eth_current;
61 61 }
62 62  
  63 +struct eth_device *eth_get_dev_by_name(char *devname)
  64 +{
  65 + struct eth_device *dev, *target_dev;
  66 +
  67 + if (!eth_devices)
  68 + return NULL;
  69 +
  70 + dev = eth_devices;
  71 + target_dev = NULL;
  72 + do {
  73 + if (strcmp(devname, dev->name) == 0) {
  74 + target_dev = dev;
  75 + break;
  76 + }
  77 + dev = dev->next;
  78 + } while (dev != eth_devices);
  79 +
  80 + return target_dev;
  81 +}
  82 +
63 83 int eth_get_dev_index (void)
64 84 {
65 85 struct eth_device *dev;
... ... @@ -412,6 +432,30 @@
412 432 char *eth_get_name (void)
413 433 {
414 434 return (eth_current ? eth_current->name : "unknown");
  435 +}
  436 +#elif (CONFIG_COMMANDS & CFG_CMD_NET) && !defined(CONFIG_NET_MULTI)
  437 +
  438 +extern int at91rm9200_miiphy_initialize(bd_t *bis);
  439 +extern int emac4xx_miiphy_initialize(bd_t *bis);
  440 +extern int mcf52x2_miiphy_initialize(bd_t *bis);
  441 +extern int ns7520_miiphy_initialize(bd_t *bis);
  442 +
  443 +int eth_initialize(bd_t *bis)
  444 +{
  445 +#if defined(CONFIG_AT91RM9200)
  446 + at91rm9200_miiphy_initialize(bis);
  447 +#endif
  448 +#if defined(CONFIG_4xx) && !defined(CONFIG_IOP480) \
  449 + && !defined(CONFIG_AP1000) && !defined(CONFIG_405)
  450 + emac4xx_miiphy_initialize(bis);
  451 +#endif
  452 +#if defined(CONFIG_MCF52x2)
  453 + mcf52x2_miiphy_initialize(bis);
  454 +#endif
  455 +#if defined(CONFIG_NETARM)
  456 + ns7520_miiphy_initialize(bis);
  457 +#endif
  458 + return 0;
415 459 }
416 460 #endif
... ... @@ -461,7 +461,7 @@
461 461 /*
462 462 * Echo the inverted link state to the fault LED.
463 463 */
464   - if(miiphy_link(CFG_FAULT_MII_ADDR)) {
  464 + if(miiphy_link(eth_get_dev()->name, CFG_FAULT_MII_ADDR)) {
465 465 status_led_set (STATUS_LED_RED, STATUS_LED_OFF);
466 466 } else {
467 467 status_led_set (STATUS_LED_RED, STATUS_LED_ON);
... ... @@ -512,7 +512,7 @@
512 512 /*
513 513 * Echo the inverted link state to the fault LED.
514 514 */
515   - if(miiphy_link(CFG_FAULT_MII_ADDR)) {
  515 + if(miiphy_link(eth_get_dev()->name, CFG_FAULT_MII_ADDR)) {
516 516 status_led_set (STATUS_LED_RED, STATUS_LED_OFF);
517 517 } else {
518 518 status_led_set (STATUS_LED_RED, STATUS_LED_ON);