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Commit da188a0388191185d3e1b7a535180ca10cf062ae

Authored by Chris Zankel
Committed by Tom Rini
1 parent c978b52410

xtensa: add core information for the dc232b processor 

DC232B is an xtensa processor with full MMUv2 capable of running Linux.
Core information files are autogenerated from the processor description
and are not meant to be edited.

Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

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arch/xtensa/include/asm/arch-dc232b/core.h
Diff comments   View file @ da188a0
  1 +/*
  2 + * Xtensa processor core configuration information.
  3 + * This file is autogenerated, please do not edit.
  4 + *
  5 + * Copyright (C) 1999-2007 Tensilica Inc.
  6 + *
  7 + * SPDX-License-Identifier: GPL-2.0+
  8 + */
  9 +
  10 +#ifndef _XTENSA_CORE_CONFIGURATION_H
  11 +#define _XTENSA_CORE_CONFIGURATION_H
  12 +
  13 +
  14 +/****************************************************************************
  15 + Parameters Useful for Any Code, USER or PRIVILEGED
  16 + ****************************************************************************/
  17 +
  18 +/*
  19 + * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
  20 + * configured, and a value of 0 otherwise. These macros are always defined.
  21 + */
  22 +
  23 +
  24 +/*----------------------------------------------------------------------
  25 + ISA
  26 + ----------------------------------------------------------------------*/
  27 +
  28 +#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
  29 +#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
  30 +#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
  31 +#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
  32 +#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */
  33 +#define XCHAL_HAVE_DEBUG 1 /* debug option */
  34 +#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
  35 +#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
  36 +#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
  37 +#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
  38 +#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
  39 +#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
  40 +#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
  41 +#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
  42 +#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */
  43 +#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
  44 +#define XCHAL_HAVE_L32R 1 /* L32R instruction */
  45 +#define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
  46 +#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
  47 +#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
  48 +#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
  49 +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
  50 +#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
  51 +#define XCHAL_HAVE_ABS 1 /* ABS instruction */
  52 +/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
  53 +/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
  54 +#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
  55 +#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
  56 +#define XCHAL_HAVE_SPECULATION 0 /* speculation */
  57 +#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
  58 +#define XCHAL_NUM_CONTEXTS 1 /* */
  59 +#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
  60 +#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
  61 +#define XCHAL_HAVE_PRID 1 /* processor ID register */
  62 +#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
  63 +#define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */
  64 +#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
  65 +#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */
  66 +#define XCHAL_HAVE_MAC16 1 /* MAC16 package */
  67 +#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
  68 +#define XCHAL_HAVE_FP 0 /* floating point pkg */
  69 +#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
  70 +#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
  71 +#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
  72 +
  73 +
  74 +/*----------------------------------------------------------------------
  75 + MISC
  76 + ----------------------------------------------------------------------*/
  77 +
  78 +#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */
  79 +#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
  80 +#define XCHAL_DATA_WIDTH 4 /* data width in bytes */
  81 +/* In T1050, applies to selected core load and store instructions (see ISA): */
  82 +#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
  83 +#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
  84 +
  85 +#define XCHAL_SW_VERSION 701001 /* sw version of this header */
  86 +
  87 +#define XCHAL_CORE_ID "dc232b" /* alphanum core name
  88 + (CoreID) set in the Xtensa
  89 + Processor Generator */
  90 +
  91 +#define XCHAL_CORE_DESCRIPTION "Diamond 232L Standard Core Rev.B (LE)"
  92 +#define XCHAL_BUILD_UNIQUE_ID 0x0000BEEF /* 22-bit sw build ID */
  93 +
  94 +/*
  95 + * These definitions describe the hardware targeted by this software.
  96 + */
  97 +#define XCHAL_HW_CONFIGID0 0xC56307FE /* ConfigID hi 32 bits*/
  98 +#define XCHAL_HW_CONFIGID1 0x0D40BEEF /* ConfigID lo 32 bits*/
  99 +#define XCHAL_HW_VERSION_NAME "LX2.1.1" /* full version name */
  100 +#define XCHAL_HW_VERSION_MAJOR 2210 /* major ver# of targeted hw */
  101 +#define XCHAL_HW_VERSION_MINOR 1 /* minor ver# of targeted hw */
  102 +#define XCHAL_HW_VERSION 221001 /* major*100+minor */
  103 +#define XCHAL_HW_REL_LX2 1
  104 +#define XCHAL_HW_REL_LX2_1 1
  105 +#define XCHAL_HW_REL_LX2_1_1 1
  106 +#define XCHAL_HW_CONFIGID_RELIABLE 1
  107 +/* If software targets a *range* of hardware versions, these are the bounds: */
  108 +#define XCHAL_HW_MIN_VERSION_MAJOR 2210 /* major v of earliest tgt hw */
  109 +#define XCHAL_HW_MIN_VERSION_MINOR 1 /* minor v of earliest tgt hw */
  110 +#define XCHAL_HW_MIN_VERSION 221001 /* earliest targeted hw */
  111 +#define XCHAL_HW_MAX_VERSION_MAJOR 2210 /* major v of latest tgt hw */
  112 +#define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */
  113 +#define XCHAL_HW_MAX_VERSION 221001 /* latest targeted hw */
  114 +
  115 +
  116 +/*----------------------------------------------------------------------
  117 + CACHE
  118 + ----------------------------------------------------------------------*/
  119 +
  120 +#define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */
  121 +#define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */
  122 +#define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */
  123 +#define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */
  124 +
  125 +#define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */
  126 +#define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */
  127 +
  128 +#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
  129 +
  130 +
  131 +
  132 +
  133 +/****************************************************************************
  134 + Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
  135 + ****************************************************************************/
  136 +
  137 +
  138 +#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
  139 +
  140 +/*----------------------------------------------------------------------
  141 + CACHE
  142 + ----------------------------------------------------------------------*/
  143 +
  144 +#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
  145 +
  146 +/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
  147 +
  148 +/* Number of cache sets in log2(lines per way): */
  149 +#define XCHAL_ICACHE_SETWIDTH 7
  150 +#define XCHAL_DCACHE_SETWIDTH 7
  151 +
  152 +/* Cache set associativity (number of ways): */
  153 +#define XCHAL_ICACHE_WAYS 4
  154 +#define XCHAL_DCACHE_WAYS 4
  155 +
  156 +/* Cache features: */
  157 +#define XCHAL_ICACHE_LINE_LOCKABLE 1
  158 +#define XCHAL_DCACHE_LINE_LOCKABLE 1
  159 +#define XCHAL_ICACHE_ECC_PARITY 0
  160 +#define XCHAL_DCACHE_ECC_PARITY 0
  161 +
  162 +/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
  163 +#define XCHAL_CA_BITS 4
  164 +
  165 +
  166 +/*----------------------------------------------------------------------
  167 + INTERNAL I/D RAM/ROMs and XLMI
  168 + ----------------------------------------------------------------------*/
  169 +
  170 +#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
  171 +#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
  172 +#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
  173 +#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
  174 +#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
  175 +#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
  176 +
  177 +
  178 +/*----------------------------------------------------------------------
  179 + INTERRUPTS and TIMERS
  180 + ----------------------------------------------------------------------*/
  181 +
  182 +#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
  183 +#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
  184 +#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
  185 +#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
  186 +#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
  187 +#define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */
  188 +#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
  189 +#define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */
  190 +#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
  191 + (not including level zero) */
  192 +#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
  193 + /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
  194 +
  195 +/* Masks of interrupts at each interrupt level: */
  196 +#define XCHAL_INTLEVEL1_MASK 0x001F80FF
  197 +#define XCHAL_INTLEVEL2_MASK 0x00000100
  198 +#define XCHAL_INTLEVEL3_MASK 0x00200E00
  199 +#define XCHAL_INTLEVEL4_MASK 0x00001000
  200 +#define XCHAL_INTLEVEL5_MASK 0x00002000
  201 +#define XCHAL_INTLEVEL6_MASK 0x00000000
  202 +#define XCHAL_INTLEVEL7_MASK 0x00004000
  203 +
  204 +/* Masks of interrupts at each range 1..n of interrupt levels: */
  205 +#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F80FF
  206 +#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F81FF
  207 +#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F8FFF
  208 +#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF
  209 +#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF
  210 +#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF
  211 +#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF
  212 +
  213 +/* Level of each interrupt: */
  214 +#define XCHAL_INT0_LEVEL 1
  215 +#define XCHAL_INT1_LEVEL 1
  216 +#define XCHAL_INT2_LEVEL 1
  217 +#define XCHAL_INT3_LEVEL 1
  218 +#define XCHAL_INT4_LEVEL 1
  219 +#define XCHAL_INT5_LEVEL 1
  220 +#define XCHAL_INT6_LEVEL 1
  221 +#define XCHAL_INT7_LEVEL 1
  222 +#define XCHAL_INT8_LEVEL 2
  223 +#define XCHAL_INT9_LEVEL 3
  224 +#define XCHAL_INT10_LEVEL 3
  225 +#define XCHAL_INT11_LEVEL 3
  226 +#define XCHAL_INT12_LEVEL 4
  227 +#define XCHAL_INT13_LEVEL 5
  228 +#define XCHAL_INT14_LEVEL 7
  229 +#define XCHAL_INT15_LEVEL 1
  230 +#define XCHAL_INT16_LEVEL 1
  231 +#define XCHAL_INT17_LEVEL 1
  232 +#define XCHAL_INT18_LEVEL 1
  233 +#define XCHAL_INT19_LEVEL 1
  234 +#define XCHAL_INT20_LEVEL 1
  235 +#define XCHAL_INT21_LEVEL 3
  236 +#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
  237 +#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
  238 +#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
  239 + EXCSAVE/EPS/EPC_n, RFI n) */
  240 +
  241 +/* Type of each interrupt: */
  242 +#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
  243 +#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
  244 +#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
  245 +#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
  246 +#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
  247 +#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
  248 +#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
  249 +#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
  250 +#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
  251 +#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
  252 +#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
  253 +#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
  254 +#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
  255 +#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
  256 +#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
  257 +#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE
  258 +#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE
  259 +#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE
  260 +#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE
  261 +#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE
  262 +#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE
  263 +#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE
  264 +
  265 +/* Masks of interrupts for each type of interrupt: */
  266 +#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000
  267 +#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880
  268 +#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F8000
  269 +#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F
  270 +#define XCHAL_INTTYPE_MASK_TIMER 0x00002440
  271 +#define XCHAL_INTTYPE_MASK_NMI 0x00004000
  272 +#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
  273 +
  274 +/* Interrupt numbers assigned to specific interrupt sources: */
  275 +#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
  276 +#define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */
  277 +#define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */
  278 +#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
  279 +#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
  280 +
  281 +/* Interrupt numbers for levels at which only one interrupt is configured: */
  282 +#define XCHAL_INTLEVEL2_NUM 8
  283 +#define XCHAL_INTLEVEL4_NUM 12
  284 +#define XCHAL_INTLEVEL5_NUM 13
  285 +#define XCHAL_INTLEVEL7_NUM 14
  286 +/* (There are many interrupts each at level(s) 1, 3.) */
  287 +
  288 +
  289 +/*
  290 + * External interrupt vectors/levels.
  291 + * These macros describe how Xtensa processor interrupt numbers
  292 + * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
  293 + * map to external BInterrupt<n> pins, for those interrupts
  294 + * configured as external (level-triggered, edge-triggered, or NMI).
  295 + * See the Xtensa processor databook for more details.
  296 + */
  297 +
  298 +/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
  299 +#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
  300 +#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
  301 +#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
  302 +#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
  303 +#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
  304 +#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
  305 +#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */
  306 +#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */
  307 +#define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */
  308 +#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */
  309 +#define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */
  310 +#define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */
  311 +#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */
  312 +#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */
  313 +#define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */
  314 +#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */
  315 +#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */
  316 +
  317 +
  318 +/*----------------------------------------------------------------------
  319 + EXCEPTIONS and VECTORS
  320 + ----------------------------------------------------------------------*/
  321 +
  322 +#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
  323 + number: 1 == XEA1 (old)
  324 + 2 == XEA2 (new)
  325 + 0 == XEAX (extern) */
  326 +#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
  327 +#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
  328 +#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
  329 +#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
  330 +#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
  331 +#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
  332 +#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
  333 +#define XCHAL_VECBASE_RESET_VADDR 0xD0000000 /* VECBASE reset value */
  334 +#define XCHAL_VECBASE_RESET_PADDR 0x00000000
  335 +#define XCHAL_RESET_VECBASE_OVERLAP 0
  336 +
  337 +#define XCHAL_RESET_VECTOR0_VADDR 0xFE000000
  338 +#define XCHAL_RESET_VECTOR0_PADDR 0xFE000000
  339 +#define XCHAL_RESET_VECTOR1_VADDR 0xD8000500
  340 +#define XCHAL_RESET_VECTOR1_PADDR 0x00000500
  341 +#define XCHAL_RESET_VECTOR_VADDR 0xFE000000
  342 +#define XCHAL_RESET_VECTOR_PADDR 0xFE000000
  343 +#define XCHAL_USER_VECOFS 0x00000340
  344 +#define XCHAL_USER_VECTOR_VADDR 0xD0000340
  345 +#define XCHAL_USER_VECTOR_PADDR 0x00000340
  346 +#define XCHAL_KERNEL_VECOFS 0x00000300
  347 +#define XCHAL_KERNEL_VECTOR_VADDR 0xD0000300
  348 +#define XCHAL_KERNEL_VECTOR_PADDR 0x00000300
  349 +#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
  350 +#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xD00003C0
  351 +#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000003C0
  352 +#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
  353 +#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
  354 +#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
  355 +#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
  356 +#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
  357 +#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
  358 +#define XCHAL_WINDOW_VECTORS_VADDR 0xD0000000
  359 +#define XCHAL_WINDOW_VECTORS_PADDR 0x00000000
  360 +#define XCHAL_INTLEVEL2_VECOFS 0x00000180
  361 +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0xD0000180
  362 +#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00000180
  363 +#define XCHAL_INTLEVEL3_VECOFS 0x000001C0
  364 +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0xD00001C0
  365 +#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x000001C0
  366 +#define XCHAL_INTLEVEL4_VECOFS 0x00000200
  367 +#define XCHAL_INTLEVEL4_VECTOR_VADDR 0xD0000200
  368 +#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x00000200
  369 +#define XCHAL_INTLEVEL5_VECOFS 0x00000240
  370 +#define XCHAL_INTLEVEL5_VECTOR_VADDR 0xD0000240
  371 +#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x00000240
  372 +#define XCHAL_INTLEVEL6_VECOFS 0x00000280
  373 +#define XCHAL_INTLEVEL6_VECTOR_VADDR 0xD0000280
  374 +#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00000280
  375 +#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
  376 +#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
  377 +#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
  378 +#define XCHAL_NMI_VECOFS 0x000002C0
  379 +#define XCHAL_NMI_VECTOR_VADDR 0xD00002C0
  380 +#define XCHAL_NMI_VECTOR_PADDR 0x000002C0
  381 +#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
  382 +#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
  383 +#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
  384 +
  385 +
  386 +/*----------------------------------------------------------------------
  387 + DEBUG
  388 + ----------------------------------------------------------------------*/
  389 +
  390 +#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
  391 +#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
  392 +#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
  393 +#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */
  394 +
  395 +
  396 +/*----------------------------------------------------------------------
  397 + MMU
  398 + ----------------------------------------------------------------------*/
  399 +
  400 +/* See core-matmap.h header file for more details. */
  401 +
  402 +#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
  403 +#define XCHAL_HAVE_SPANNING_WAY 0 /* one way maps I+D 4GB vaddr */
  404 +#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */
  405 +#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
  406 +#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */
  407 +#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
  408 +#define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table
  409 + [autorefill] and protection)
  410 + usable for an MMU-based OS */
  411 +/* If none of the above last 4 are set, it's a custom TLB configuration. */
  412 +#define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
  413 +#define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
  414 +
  415 +#define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */
  416 +#define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */
  417 +#define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */
  418 +
  419 +#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
  420 +
  421 +
  422 +#endif /* _XTENSA_CORE_CONFIGURATION_H */
arch/xtensa/include/asm/arch-dc232b/tie-asm.h
Diff comments   View file @ da188a0
  1 +/*
  2 + * This header file contains assembly-language definitions (assembly
  3 + * macros, etc.) for this specific Xtensa processor's TIE extensions
  4 + * and options. It is customized to this Xtensa processor configuration.
  5 + * This file is autogenerated, please do not edit.
  6 + *
  7 + * Copyright (C) 1999-2007 Tensilica Inc.
  8 + *
  9 + * SPDX-License-Identifier: GPL-2.0+
  10 + */
  11 +
  12 +#ifndef _XTENSA_CORE_TIE_ASM_H
  13 +#define _XTENSA_CORE_TIE_ASM_H
  14 +
  15 +/* Selection parameter values for save-area save/restore macros: */
  16 +/* Option vs. TIE: */
  17 +#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
  18 +#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
  19 +/* Whether used automatically by compiler: */
  20 +#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
  21 +#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
  22 +/* ABI handling across function calls: */
  23 +#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
  24 +#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
  25 +#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
  26 +/* Misc */
  27 +#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
  28 +
  29 +
  30 +
  31 +/* Macro to save all non-coprocessor (extra) custom TIE and optional state
  32 + * (not including zero-overhead loop registers).
  33 + * Save area ptr (clobbered): ptr (1 byte aligned)
  34 + * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
  35 + */
  36 + .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
  37 + xchal_sa_start \continue, \ofs
  38 + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select
  39 + xchal_sa_align \ptr, 0, 1024-8, 4, 4
  40 + rsr \at1, ACCLO // MAC16 accumulator
  41 + rsr \at2, ACCHI
  42 + s32i \at1, \ptr, .Lxchal_ofs_ + 0
  43 + s32i \at2, \ptr, .Lxchal_ofs_ + 4
  44 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
  45 + .endif
  46 + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
  47 + xchal_sa_align \ptr, 0, 1024-16, 4, 4
  48 + rsr \at1, M0 // MAC16 registers
  49 + rsr \at2, M1
  50 + s32i \at1, \ptr, .Lxchal_ofs_ + 0
  51 + s32i \at2, \ptr, .Lxchal_ofs_ + 4
  52 + rsr \at1, M2
  53 + rsr \at2, M3
  54 + s32i \at1, \ptr, .Lxchal_ofs_ + 8
  55 + s32i \at2, \ptr, .Lxchal_ofs_ + 12
  56 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 16
  57 + .endif
  58 + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
  59 + xchal_sa_align \ptr, 0, 1024-4, 4, 4
  60 + rsr \at1, SCOMPARE1 // conditional store option
  61 + s32i \at1, \ptr, .Lxchal_ofs_ + 0
  62 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
  63 + .endif
  64 + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
  65 + xchal_sa_align \ptr, 0, 1024-4, 4, 4
  66 + rur \at1, THREADPTR // threadptr option
  67 + s32i \at1, \ptr, .Lxchal_ofs_ + 0
  68 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
  69 + .endif
  70 + .endm // xchal_ncp_store
  71 +
  72 +/* Macro to save all non-coprocessor (extra) custom TIE and optional state
  73 + * (not including zero-overhead loop registers).
  74 + * Save area ptr (clobbered): ptr (1 byte aligned)
  75 + * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
  76 + */
  77 + .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
  78 + xchal_sa_start \continue, \ofs
  79 + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select
  80 + xchal_sa_align \ptr, 0, 1024-8, 4, 4
  81 + l32i \at1, \ptr, .Lxchal_ofs_ + 0
  82 + l32i \at2, \ptr, .Lxchal_ofs_ + 4
  83 + wsr \at1, ACCLO // MAC16 accumulator
  84 + wsr \at2, ACCHI
  85 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
  86 + .endif
  87 + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
  88 + xchal_sa_align \ptr, 0, 1024-16, 4, 4
  89 + l32i \at1, \ptr, .Lxchal_ofs_ + 0
  90 + l32i \at2, \ptr, .Lxchal_ofs_ + 4
  91 + wsr \at1, M0 // MAC16 registers
  92 + wsr \at2, M1
  93 + l32i \at1, \ptr, .Lxchal_ofs_ + 8
  94 + l32i \at2, \ptr, .Lxchal_ofs_ + 12
  95 + wsr \at1, M2
  96 + wsr \at2, M3
  97 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 16
  98 + .endif
  99 + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
  100 + xchal_sa_align \ptr, 0, 1024-4, 4, 4
  101 + l32i \at1, \ptr, .Lxchal_ofs_ + 0
  102 + wsr \at1, SCOMPARE1 // conditional store option
  103 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
  104 + .endif
  105 + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
  106 + xchal_sa_align \ptr, 0, 1024-4, 4, 4
  107 + l32i \at1, \ptr, .Lxchal_ofs_ + 0
  108 + wur \at1, THREADPTR // threadptr option
  109 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
  110 + .endif
  111 + .endm // xchal_ncp_load
  112 +
  113 +
  114 +
  115 +#define XCHAL_NCP_NUM_ATMPS 2
  116 +
  117 +
  118 +#define XCHAL_SA_NUM_ATMPS 2
  119 +
  120 +#endif /*_XTENSA_CORE_TIE_ASM_H*/
arch/xtensa/include/asm/arch-dc232b/tie.h
Diff comments   View file @ da188a0
  1 +/*
  2 + * This header file describes this specific Xtensa processor's TIE extensions
  3 + * that extend basic Xtensa core functionality. It is customized to this
  4 + * Xtensa processor configuration.
  5 + * This file is autogenerated, please do not edit.
  6 + *
  7 + * Copyright (C) 1999-2007 Tensilica Inc.
  8 + *
  9 + * SPDX-License-Identifier: GPL-2.0+
  10 + */
  11 +
  12 +#ifndef _XTENSA_CORE_TIE_H
  13 +#define _XTENSA_CORE_TIE_H
  14 +
  15 +#define XCHAL_CP_NUM 1 /* number of coprocessors */
  16 +#define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
  17 +#define XCHAL_CP_MASK 0x80 /* bitmask of all CPs by ID */
  18 +#define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
  19 +
  20 +/* Basic parameters of each coprocessor: */
  21 +#define XCHAL_CP7_NAME "XTIOP"
  22 +#define XCHAL_CP7_IDENT XTIOP
  23 +#define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
  24 +#define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */
  25 +#define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
  26 +
  27 +/* Filler info for unassigned coprocessors, to simplify arrays etc: */
  28 +#define XCHAL_CP0_SA_SIZE 0
  29 +#define XCHAL_CP0_SA_ALIGN 1
  30 +#define XCHAL_CP1_SA_SIZE 0
  31 +#define XCHAL_CP1_SA_ALIGN 1
  32 +#define XCHAL_CP2_SA_SIZE 0
  33 +#define XCHAL_CP2_SA_ALIGN 1
  34 +#define XCHAL_CP3_SA_SIZE 0
  35 +#define XCHAL_CP3_SA_ALIGN 1
  36 +#define XCHAL_CP4_SA_SIZE 0
  37 +#define XCHAL_CP4_SA_ALIGN 1
  38 +#define XCHAL_CP5_SA_SIZE 0
  39 +#define XCHAL_CP5_SA_ALIGN 1
  40 +#define XCHAL_CP6_SA_SIZE 0
  41 +#define XCHAL_CP6_SA_ALIGN 1
  42 +
  43 +/* Save area for non-coprocessor optional and custom (TIE) state: */
  44 +#define XCHAL_NCP_SA_SIZE 32
  45 +#define XCHAL_NCP_SA_ALIGN 4
  46 +
  47 +/* Total save area for optional and custom state (NCP + CPn): */
  48 +#define XCHAL_TOTAL_SA_SIZE 32 /* with 16-byte align padding */
  49 +#define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */
  50 +
  51 +/*
  52 + * Detailed contents of save areas.
  53 + * NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
  54 + * before expanding the XCHAL_xxx_SA_LIST() macros.
  55 + *
  56 + * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
  57 + * dbnum,base,regnum,bitsz,gapsz,reset,x...)
  58 + *
  59 + * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
  60 + * ccused = set if used by compiler without special options or code
  61 + * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
  62 + * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
  63 + * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
  64 + * name = lowercase reg name (no quotes)
  65 + * galign = group byte alignment (power of 2) (galign >= align)
  66 + * align = register byte alignment (power of 2)
  67 + * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
  68 + * (not including any pad bytes required to galign this or next reg)
  69 + * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
  70 + * base = reg shortname w/o index (or sr=special, ur=TIE user reg)
  71 + * regnum = reg index in regfile, or special/TIE-user reg number
  72 + * bitsz = number of significant bits (regfile width, or ur/sr mask bits)
  73 + * gapsz = intervening bits, if bitsz bits not stored contiguously
  74 + * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
  75 + * reset = register reset value (or 0 if undefined at reset)
  76 + * x = reserved for future use (0 until then)
  77 + *
  78 + * To filter out certain registers, e.g. to expand only the non-global
  79 + * registers used by the compiler, you can do something like this:
  80 + *
  81 + * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
  82 + * #define SELCC0(p...)
  83 + * #define SELCC1(abikind,p...) SELAK##abikind(p)
  84 + * #define SELAK0(p...) REG(p)
  85 + * #define SELAK1(p...) REG(p)
  86 + * #define SELAK2(p...)
  87 + * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
  88 + * ...what you want to expand...
  89 + */
  90 +
  91 +#define XCHAL_NCP_SA_NUM 8
  92 +#define XCHAL_NCP_SA_LIST(s) \
  93 + XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
  94 + XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
  95 + XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
  96 + XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
  97 + XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
  98 + XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
  99 + XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
  100 + XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0)
  101 +
  102 +#define XCHAL_CP0_SA_NUM 0
  103 +#define XCHAL_CP0_SA_LIST(s) /* empty */
  104 +
  105 +#define XCHAL_CP1_SA_NUM 0
  106 +#define XCHAL_CP1_SA_LIST(s) /* empty */
  107 +
  108 +#define XCHAL_CP2_SA_NUM 0
  109 +#define XCHAL_CP2_SA_LIST(s) /* empty */
  110 +
  111 +#define XCHAL_CP3_SA_NUM 0
  112 +#define XCHAL_CP3_SA_LIST(s) /* empty */
  113 +
  114 +#define XCHAL_CP4_SA_NUM 0
  115 +#define XCHAL_CP4_SA_LIST(s) /* empty */
  116 +
  117 +#define XCHAL_CP5_SA_NUM 0
  118 +#define XCHAL_CP5_SA_LIST(s) /* empty */
  119 +
  120 +#define XCHAL_CP6_SA_NUM 0
  121 +#define XCHAL_CP6_SA_LIST(s) /* empty */
  122 +
  123 +#define XCHAL_CP7_SA_NUM 0
  124 +#define XCHAL_CP7_SA_LIST(s) /* empty */
  125 +
  126 +/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
  127 +#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
  128 +
  129 +#endif /*_XTENSA_CORE_TIE_H*/