Commit da419027afe8336284f5db9867a880dfb3b3ab26
Committed by
York Sun
York Sun
1 parent
306fa01279
Exists in
v2017.01-smarct4x
and in
37 other branches
arm: ls102xa: Update PCIe dts node status
The patch changes PCIe dts node status to 'disabled' if the corresponding controller is disabled according to serdes protocol. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Showing 8 changed files with 93 additions and 0 deletions Side-by-side Diff
arch/arm/include/asm/arch-ls102xa/config.h
| ... | ... | @@ -53,6 +53,9 @@ |
| 53 | 53 | |
| 54 | 54 | #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) |
| 55 | 55 | |
| 56 | +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) | |
| 57 | +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) | |
| 58 | + | |
| 56 | 59 | #ifdef CONFIG_DDR_SPD |
| 57 | 60 | #define CONFIG_SYS_FSL_DDR_BE |
| 58 | 61 | #define CONFIG_VERY_BIG_RAM |
arch/arm/include/asm/pcie_layerscape.h
board/freescale/ls1021aqds/ls1021aqds.c
| ... | ... | @@ -10,6 +10,7 @@ |
| 10 | 10 | #include <asm/arch/immap_ls102xa.h> |
| 11 | 11 | #include <asm/arch/clock.h> |
| 12 | 12 | #include <asm/arch/fsl_serdes.h> |
| 13 | +#include <asm/pcie_layerscape.h> | |
| 13 | 14 | #include <mmc.h> |
| 14 | 15 | #include <fsl_esdhc.h> |
| 15 | 16 | #include <fsl_ifc.h> |
| ... | ... | @@ -257,6 +258,10 @@ |
| 257 | 258 | int ft_board_setup(void *blob, bd_t *bd) |
| 258 | 259 | { |
| 259 | 260 | ft_cpu_setup(blob, bd); |
| 261 | + | |
| 262 | +#ifdef CONFIG_PCIE_LAYERSCAPE | |
| 263 | + ft_pcie_setup(blob, bd); | |
| 264 | +#endif | |
| 260 | 265 | |
| 261 | 266 | return 0; |
| 262 | 267 | } |
board/freescale/ls1021atwr/ls1021atwr.c
| ... | ... | @@ -10,6 +10,7 @@ |
| 10 | 10 | #include <asm/arch/immap_ls102xa.h> |
| 11 | 11 | #include <asm/arch/clock.h> |
| 12 | 12 | #include <asm/arch/fsl_serdes.h> |
| 13 | +#include <asm/pcie_layerscape.h> | |
| 13 | 14 | #include <mmc.h> |
| 14 | 15 | #include <fsl_esdhc.h> |
| 15 | 16 | #include <fsl_ifc.h> |
| ... | ... | @@ -306,6 +307,10 @@ |
| 306 | 307 | int ft_board_setup(void *blob, bd_t *bd) |
| 307 | 308 | { |
| 308 | 309 | ft_cpu_setup(blob, bd); |
| 310 | + | |
| 311 | +#ifdef CONFIG_PCIE_LAYERSCAPE | |
| 312 | + ft_pcie_setup(blob, bd); | |
| 313 | +#endif | |
| 309 | 314 | |
| 310 | 315 | return 0; |
| 311 | 316 | } |
drivers/pci/Makefile
drivers/pci/pcie_layerscape.c
| 1 | +/* | |
| 2 | + * Copyright 2014 Freescale Semiconductor, Inc. | |
| 3 | + * Layerscape PCIe driver | |
| 4 | + * | |
| 5 | + * SPDX-License-Identifier: GPL-2.0+ | |
| 6 | + */ | |
| 7 | + | |
| 8 | +#include <common.h> | |
| 9 | +#include <asm/arch/fsl_serdes.h> | |
| 10 | +#include <pci.h> | |
| 11 | +#include <asm/io.h> | |
| 12 | +#include <asm/pcie_layerscape.h> | |
| 13 | + | |
| 14 | +#ifdef CONFIG_OF_BOARD_SETUP | |
| 15 | +#include <libfdt.h> | |
| 16 | +#include <fdt_support.h> | |
| 17 | + | |
| 18 | +static void ft_pcie_ls_setup(void *blob, const char *pci_compat, | |
| 19 | + unsigned long ctrl_addr, enum srds_prtcl dev) | |
| 20 | +{ | |
| 21 | + int off; | |
| 22 | + | |
| 23 | + off = fdt_node_offset_by_compat_reg(blob, pci_compat, | |
| 24 | + (phys_addr_t)ctrl_addr); | |
| 25 | + if (off < 0) | |
| 26 | + return; | |
| 27 | + | |
| 28 | + if (!is_serdes_configured(dev)) | |
| 29 | + fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); | |
| 30 | +} | |
| 31 | + | |
| 32 | +void ft_pcie_setup(void *blob, bd_t *bd) | |
| 33 | +{ | |
| 34 | + #ifdef CONFIG_PCIE1 | |
| 35 | + ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE1_ADDR, PCIE1); | |
| 36 | + #endif | |
| 37 | + | |
| 38 | + #ifdef CONFIG_PCIE2 | |
| 39 | + ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2); | |
| 40 | + #endif | |
| 41 | +} | |
| 42 | + | |
| 43 | +#else | |
| 44 | +void ft_pcie_setup(void *blob, bd_t *bd) | |
| 45 | +{ | |
| 46 | +} | |
| 47 | +#endif | |
| 48 | + | |
| 49 | +void pci_init_board(void) | |
| 50 | +{ | |
| 51 | +} |
include/configs/ls1021aqds.h
| ... | ... | @@ -341,6 +341,14 @@ |
| 341 | 341 | #endif |
| 342 | 342 | |
| 343 | 343 | #endif |
| 344 | + | |
| 345 | +/* PCIe */ | |
| 346 | +#define CONFIG_PCI /* Enable PCI/PCIE */ | |
| 347 | +#define CONFIG_PCIE1 /* PCIE controler 1 */ | |
| 348 | +#define CONFIG_PCIE2 /* PCIE controler 2 */ | |
| 349 | +#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ | |
| 350 | +#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" | |
| 351 | + | |
| 344 | 352 | #define CONFIG_CMD_PING |
| 345 | 353 | #define CONFIG_CMD_DHCP |
| 346 | 354 | #define CONFIG_CMD_MII |
include/configs/ls1021atwr.h
| ... | ... | @@ -236,6 +236,13 @@ |
| 236 | 236 | #define CONFIG_HAS_ETH2 |
| 237 | 237 | #endif |
| 238 | 238 | |
| 239 | +/* PCIe */ | |
| 240 | +#define CONFIG_PCI /* Enable PCI/PCIE */ | |
| 241 | +#define CONFIG_PCIE1 /* PCIE controler 1 */ | |
| 242 | +#define CONFIG_PCIE2 /* PCIE controler 2 */ | |
| 243 | +#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ | |
| 244 | +#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" | |
| 245 | + | |
| 239 | 246 | #define CONFIG_CMD_PING |
| 240 | 247 | #define CONFIG_CMD_DHCP |
| 241 | 248 | #define CONFIG_CMD_MII |