Eric Lee / smarc-uboot

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Commit da4d620c90eb6dd9466a89837ab8667048d856e3

Authored by Qianyu Gong
Committed by York Sun
1 parent 86336e60c5
Exists in v2017.01-smarct4x and in 26 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2017.01-smarct3x, v2017.01-smarct3x-emmc

armv8: fsl_lsch2: Add SerDes 2 support 

New SoC LS1046A belongs to Freescale Chassis Generation 2 and
has two SerDes so we need to add this support in fsl_lsch2.
The SoC related SerDes 2 support will be added in SoC patch.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

Showing 3 changed files with 22 additions and 0 deletions Side-by-side Diff

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
Diff comments   View file @ da4d620
... ... @@ -13,6 +13,9 @@
13 13 #ifdef CONFIG_SYS_FSL_SRDS_1
14 14 static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
15 15 #endif
  16 +#ifdef CONFIG_SYS_FSL_SRDS_2
  17 +static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
  18 +#endif
16 19  
17 20 int is_serdes_configured(enum srds_prtcl device)
18 21 {
... ... @@ -21,6 +24,9 @@
21 24 #ifdef CONFIG_SYS_FSL_SRDS_1
22 25 ret |= serdes1_prtcl_map[device];
23 26 #endif
  27 +#ifdef CONFIG_SYS_FSL_SRDS_2
  28 + ret |= serdes2_prtcl_map[device];
  29 +#endif
24 30  
25 31 return !!ret;
26 32 }
... ... @@ -38,6 +44,12 @@
38 44 cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
39 45 break;
40 46 #endif
  47 +#ifdef CONFIG_SYS_FSL_SRDS_2
  48 + case FSL_SRDS_2:
  49 + cfg &= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
  50 + cfg >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;
  51 + break;
  52 +#endif
41 53 default:
42 54 printf("invalid SerDes%d\n", sd);
43 55 break;
... ... @@ -113,6 +125,13 @@
113 125 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK,
114 126 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT,
115 127 serdes1_prtcl_map);
  128 +#endif
  129 +#ifdef CONFIG_SYS_FSL_SRDS_2
  130 + serdes_init(FSL_SRDS_2,
  131 + CONFIG_SYS_FSL_SERDES_ADDR,
  132 + FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK,
  133 + FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT,
  134 + serdes2_prtcl_map);
116 135 #endif
117 136 }
arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
Diff comments   View file @ da4d620
... ... @@ -140,6 +140,7 @@
140 140  
141 141 enum srds {
142 142 FSL_SRDS_1 = 0,
  143 + FSL_SRDS_2 = 1,
143 144 };
144 145  
145 146 #endif
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
Diff comments   View file @ da4d620
... ... @@ -228,6 +228,8 @@
228 228 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
229 229 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000
230 230 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16
  231 +#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK 0x0000ffff
  232 +#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT 0
231 233 #define RCW_SB_EN_REG_INDEX 7
232 234 #define RCW_SB_EN_MASK 0x00200000
233 235