Eric Lee / smarc-uboot | Embedian Git Server

Commit da9971d1b3bdb554d4a4ac948119f8b2616bbcce

Authored by Ian Campbell 2015-06-27 02:42:24 +0800

Committed by Tom Rini 2015-06-28 23:46:31 +0800

Exists in v2017.01-smarct4x and in 34 other branches

Revert "sunxi/nand: Add support to the SPL for loading u-boot from internal NAND memory"

This reverts commit f76eba38b3eda905ff3bdc18dd1240d3dcbc6e5a.

This patch did not have a full and proper copyright/S-o-b chain.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>

Conflicts:
	include/configs/sun6i.h
	include/configs/sun8i.h

Showing 13 changed files with 2 additions and 415 deletions Inline Diff

arch/arm/cpu/armv7/sunxi/board.c
arch/arm/include/asm/arch-sunxi/gpio.h
arch/arm/include/asm/arch-sunxi/nand.h
board/sunxi/Kconfig
board/sunxi/board.c
drivers/mtd/nand/Makefile
drivers/mtd/nand/sunxi_nand_spl.c
include/configs/sun4i.h
include/configs/sun5i.h
include/configs/sun6i.h
include/configs/sun7i.h
include/configs/sun8i.h
include/configs/sunxi-common.h

arch/arm/cpu/armv7/sunxi/board.c

Diff comments View file @ da9971d

 /*
  * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
  *
  * (C) Copyright 2007-2011
  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  * Tom Cubie <tangliang@allwinnertech.com>
  *
  * Some init for sunxi platform.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <i2c.h>
 #include <serial.h>
 #ifdef CONFIG_SPL_BUILD
 #include <spl.h>
 #endif
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/timer.h>
 #include <linux/compiler.h>
 struct fel_stash {
 	uint32_t sp;
 	uint32_t lr;
 	uint32_t cpsr;
 	uint32_t sctlr;
 	uint32_t vbar;
 	uint32_t cr;
 };
 struct fel_stash fel_stash __attribute__((section(".data")));
 static int gpio_init(void)
 {
 #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
 	/* disable GPB22,23 as uart0 tx,rx to avoid conflict */
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
 #endif
 #if defined(CONFIG_MACH_SUN8I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0_TX);
 	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0_RX);
 #else
 	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0_TX);
 	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0_RX);
 #endif
 	sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
 #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
 	sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
 	sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
 	sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
 	sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
 	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
 	sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
 	sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
 	sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
 	sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
 #else
 #error Unsupported console port number. Please fix pin mux settings in board.c
 #endif
 	return 0;
 }
 void spl_board_load_image(void)
 {
 	debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
 	return_to_fel(fel_stash.sp, fel_stash.lr);
 }
 void s_init(void)
 {
 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_A23
 	/* Magic (undocmented) value taken from boot0, without this DRAM
 	 * access gets messed up (seems cache related) */
 	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
 #endif
 #if defined CONFIG_MACH_SUN6I || \
     defined CONFIG_MACH_SUN7I || \
     defined CONFIG_MACH_SUN8I
 	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
 	asm volatile(
 		"mrc p15, 0, r0, c1, c0, 1\n"
 		"orr r0, r0, #1 << 6\n"
 		"mcr p15, 0, r0, c1, c0, 1\n");
 #endif
 	clock_init();
 	timer_init();
 	gpio_init();
 	i2c_init_board();
 }
 #ifdef CONFIG_SPL_BUILD
 /* The sunxi internal brom will try to loader external bootloader
  * from mmc0, nand flash, mmc2.
- *
+ * Unfortunately we can't check how SPL was loaded so assume
- * Unfortunately we can't check how SPL was loaded so assume it's
+ * it's always the first SD/MMC controller
- * always the first SD/MMC controller, unless it was explicitly
- * stated that SPL is on nand flash.
  */
 u32 spl_boot_device(void)
 {
-#if defined(CONFIG_SPL_NAND_SUPPORT)
 	/*
-	 * This is compile time configuration informing SPL, that it
-	 * was loaded from nand flash.
-	 */
-	return BOOT_DEVICE_NAND;
-#else
-	/*
 	 * When booting from the SD card, the "eGON.BT0" signature is expected
 	 * to be found in memory at the address 0x0004 (see the "mksunxiboot"
 	 * tool, which generates this header).
 	 *
 	 * When booting in the FEL mode over USB, this signature is patched in
 	 * memory and replaced with something else by the 'fel' tool. This other
 	 * signature is selected in such a way, that it can't be present in a
 	 * valid bootable SD card image (because the BROM would refuse to
 	 * execute the SPL in this case).
 	 *
 	 * This branch is just making a decision at runtime whether to load
 	 * the main u-boot binary from the SD card (if the "eGON.BT0" signature
 	 * is found) or return to the FEL code in the BROM to wait and receive
 	 * the main u-boot binary over USB.
 	 */
 	if (readl(4) == 0x4E4F4765 && readl(8) == 0x3054422E) /* eGON.BT0 */
 		return BOOT_DEVICE_MMC1;
 	else
 		return BOOT_DEVICE_BOARD;
-#endif
 }
 /* No confirmation data available in SPL yet. Hardcode bootmode */
 u32 spl_boot_mode(void)
 {
 	return MMCSD_MODE_RAW;
 }
 void board_init_f(ulong dummy)
 {
 	preloader_console_init();
 #ifdef CONFIG_SPL_I2C_SUPPORT
 	/* Needed early by sunxi_board_init if PMU is enabled */
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 	sunxi_board_init();
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);
 	board_init_r(NULL, 0);
 }
 #endif
 void reset_cpu(ulong addr)
 {
 #ifdef CONFIG_SUNXI_GEN_SUN4I
 	static const struct sunxi_wdog *wdog =
 		 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
 	/* Set the watchdog for its shortest interval (.5s) and wait */
 	writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
 	writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
 	while (1) {
 		/* sun5i sometimes gets stuck without this */
 		writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
 	}
 #endif
 #ifdef CONFIG_SUNXI_GEN_SUN6I
 	static const struct sunxi_wdog *wdog =
 		 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
 	/* Set the watchdog for its shortest interval (.5s) and wait */
 	writel(WDT_CFG_RESET, &wdog->cfg);
 	writel(WDT_MODE_EN, &wdog->mode);
 	writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
 	while (1) { }
 #endif
 }
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
 {
 	/* Enable D-cache. I-cache is already enabled in start.S */
 	dcache_enable();
 }
 #endif
 #ifdef CONFIG_CMD_NET
 /*
  * Initializes on-chip ethernet controllers.
  * to override, implement board_eth_init()
  */
 int cpu_eth_init(bd_t *bis)
 {
 	__maybe_unused int rc;
 #ifdef CONFIG_MACPWR
 	gpio_request(CONFIG_MACPWR, "macpwr");
 	gpio_direction_output(CONFIG_MACPWR, 1);
 	mdelay(200);
 #endif
 #ifdef CONFIG_SUNXI_GMAC
 	rc = sunxi_gmac_initialize(bis);
 	if (rc < 0) {
 		printf("sunxi: failed to initialize gmac\n");
 		return rc;
 	}
 #endif
 	return 0;
 }
 #endif

arch/arm/include/asm/arch-sunxi/gpio.h

Diff comments View file @ da9971d

 /*
  * (C) Copyright 2007-2012
  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  * Tom Cubie <tangliang@allwinnertech.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef _SUNXI_GPIO_H
 #define _SUNXI_GPIO_H
 #include <linux/types.h>
 #include <asm/arch/cpu.h>
 /*
  * sunxi has 9 banks of gpio, they are:
  * PA0 - PA17 | PB0 - PB23 | PC0 - PC24
  * PD0 - PD27 | PE0 - PE31 | PF0 - PF5
  * PG0 - PG9  | PH0 - PH27 | PI0 - PI12
  */
 #define SUNXI_GPIO_A	0
 #define SUNXI_GPIO_B	1
 #define SUNXI_GPIO_C	2
 #define SUNXI_GPIO_D	3
 #define SUNXI_GPIO_E	4
 #define SUNXI_GPIO_F	5
 #define SUNXI_GPIO_G	6
 #define SUNXI_GPIO_H	7
 #define SUNXI_GPIO_I	8
 /*
  * This defines the number of GPIO banks for the _main_ GPIO controller.
  * You should fix up the padding in struct sunxi_gpio_reg below if you
  * change this.
  */
 #define SUNXI_GPIO_BANKS 9
 /*
  * sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO)
  * at a different register offset.
  *
  * sun6i has 2 banks:
  * PL0 - PL8  | PM0 - PM7
  *
  * sun8i has 1 bank:
  * PL0 - PL11
  *
  * sun9i has 3 banks:
  * PL0 - PL9  | PM0 - PM15  | PN0 - PN1
  */
 #define SUNXI_GPIO_L	11
 #define SUNXI_GPIO_M	12
 #define SUNXI_GPIO_N	13
 struct sunxi_gpio {
 	u32 cfg[4];
 	u32 dat;
 	u32 drv[2];
 	u32 pull[2];
 };
 /* gpio interrupt control */
 struct sunxi_gpio_int {
 	u32 cfg[3];
 	u32 ctl;
 	u32 sta;
 	u32 deb;		/* interrupt debounce */
 };
 struct sunxi_gpio_reg {
 	struct sunxi_gpio gpio_bank[SUNXI_GPIO_BANKS];
 	u8 res[0xbc];
 	struct sunxi_gpio_int gpio_int;
 };
 #define BANK_TO_GPIO(bank)	(((bank) < SUNXI_GPIO_L) ? \
 	&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \
 	&((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L])
 #define GPIO_BANK(pin)		((pin) >> 5)
 #define GPIO_NUM(pin)		((pin) & 0x1f)
 #define GPIO_CFG_INDEX(pin)	(((pin) & 0x1f) >> 3)
 #define GPIO_CFG_OFFSET(pin)	((((pin) & 0x1f) & 0x7) << 2)
 #define GPIO_DRV_INDEX(pin)	(((pin) & 0x1f) >> 4)
 #define GPIO_DRV_OFFSET(pin)	((((pin) & 0x1f) & 0xf) << 1)
 #define GPIO_PULL_INDEX(pin)	(((pin) & 0x1f) >> 4)
 #define GPIO_PULL_OFFSET(pin)	((((pin) & 0x1f) & 0xf) << 1)
 /* GPIO bank sizes */
 #define SUNXI_GPIO_A_NR		32
 #define SUNXI_GPIO_B_NR		32
 #define SUNXI_GPIO_C_NR		32
 #define SUNXI_GPIO_D_NR		32
 #define SUNXI_GPIO_E_NR		32
 #define SUNXI_GPIO_F_NR		32
 #define SUNXI_GPIO_G_NR		32
 #define SUNXI_GPIO_H_NR		32
 #define SUNXI_GPIO_I_NR		32
 #define SUNXI_GPIO_L_NR		32
 #define SUNXI_GPIO_M_NR		32
 #define SUNXI_GPIO_NEXT(__gpio) \
 	((__gpio##_START) + (__gpio##_NR) + 0)
 enum sunxi_gpio_number {
 	SUNXI_GPIO_A_START = 0,
 	SUNXI_GPIO_B_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_A),
 	SUNXI_GPIO_C_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_B),
 	SUNXI_GPIO_D_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_C),
 	SUNXI_GPIO_E_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_D),
 	SUNXI_GPIO_F_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_E),
 	SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F),
 	SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G),
 	SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H),
 	SUNXI_GPIO_L_START = 352,
 	SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),
 	SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M),
 	SUNXI_GPIO_AXP0_START = 1024,
 };
 /* SUNXI GPIO number definitions */
 #define SUNXI_GPA(_nr)	(SUNXI_GPIO_A_START + (_nr))
 #define SUNXI_GPB(_nr)	(SUNXI_GPIO_B_START + (_nr))
 #define SUNXI_GPC(_nr)	(SUNXI_GPIO_C_START + (_nr))
 #define SUNXI_GPD(_nr)	(SUNXI_GPIO_D_START + (_nr))
 #define SUNXI_GPE(_nr)	(SUNXI_GPIO_E_START + (_nr))
 #define SUNXI_GPF(_nr)	(SUNXI_GPIO_F_START + (_nr))
 #define SUNXI_GPG(_nr)	(SUNXI_GPIO_G_START + (_nr))
 #define SUNXI_GPH(_nr)	(SUNXI_GPIO_H_START + (_nr))
 #define SUNXI_GPI(_nr)	(SUNXI_GPIO_I_START + (_nr))
 #define SUNXI_GPL(_nr)	(SUNXI_GPIO_L_START + (_nr))
 #define SUNXI_GPM(_nr)	(SUNXI_GPIO_M_START + (_nr))
 #define SUNXI_GPN(_nr)	(SUNXI_GPIO_N_START + (_nr))
 #define SUNXI_GPAXP0(_nr)	(SUNXI_GPIO_AXP0_START + (_nr))
 /* GPIO pin function config */
 #define SUNXI_GPIO_INPUT	0
 #define SUNXI_GPIO_OUTPUT	1
 #define SUNXI_GPA_EMAC		2
 #define SUN6I_GPA_GMAC		2
 #define SUN7I_GPA_GMAC		5
 #define SUN6I_GPA_SDC2		5
 #define SUN6I_GPA_SDC3		4
 #define SUN4I_GPB_TWI0		2
 #define SUN4I_GPB_TWI1		2
 #define SUN5I_GPB_TWI1		2
 #define SUN4I_GPB_TWI2		2
 #define SUN5I_GPB_TWI2		2
 #define SUN4I_GPB_UART0		2
 #define SUN5I_GPB_UART0		2
 #define SUN8I_GPB_UART2		2
-#define SUNXI_GPC_NAND		2
 #define SUNXI_GPC_SDC2		3
 #define SUN6I_GPC_SDC3		4
 #define SUN8I_GPD_SDC1		3
 #define SUNXI_GPD_LCD0		2
 #define SUNXI_GPD_LVDS0		3
 #define SUN5I_GPE_SDC2		3
 #define SUN8I_GPE_TWI2		3
 #define SUNXI_GPF_SDC0		2
 #define SUNXI_GPF_UART0		4
 #define SUN8I_GPF_UART0		3
 #define SUN4I_GPG_SDC1		4
 #define SUN5I_GPG_SDC1		2
 #define SUN6I_GPG_SDC1		2
 #define SUN8I_GPG_SDC1		2
 #define SUN6I_GPG_TWI3		2
 #define SUN5I_GPG_UART1		4
 #define SUN4I_GPH_SDC1		5
 #define SUN6I_GPH_TWI0		2
 #define SUN8I_GPH_TWI0		2
 #define SUN6I_GPH_TWI1		2
 #define SUN8I_GPH_TWI1		2
 #define SUN6I_GPH_TWI2		2
 #define SUN6I_GPH_UART0		2
 #define SUN9I_GPH_UART0		2
 #define SUNXI_GPI_SDC3		2
 #define SUN7I_GPI_TWI3		3
 #define SUN7I_GPI_TWI4		3
 #define SUN6I_GPL0_R_P2WI_SCK	3
 #define SUN6I_GPL1_R_P2WI_SDA	3
 #define SUN8I_GPL_R_RSB		2
 #define SUN8I_GPL_R_UART	2
 #define SUN9I_GPN_R_RSB		3
 /* GPIO pin pull-up/down config */
 #define SUNXI_GPIO_PULL_DISABLE	0
 #define SUNXI_GPIO_PULL_UP	1
 #define SUNXI_GPIO_PULL_DOWN	2
 /* Virtual AXP0 GPIOs */
 #define SUNXI_GPIO_AXP0_PREFIX "AXP0-"
 #define SUNXI_GPIO_AXP0_VBUS_DETECT	4
 #define SUNXI_GPIO_AXP0_VBUS_ENABLE	5
 #define SUNXI_GPIO_AXP0_GPIO_COUNT	6
 void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val);
 void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
 int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset);
 int sunxi_gpio_get_cfgpin(u32 pin);
 int sunxi_gpio_set_drv(u32 pin, u32 val);
 int sunxi_gpio_set_pull(u32 pin, u32 val);
 int sunxi_name_to_gpio_bank(const char *name);
 int sunxi_name_to_gpio(const char *name);
 #define name_to_gpio(name) sunxi_name_to_gpio(name)
 #if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
 int axp_gpio_init(void);
 #else
 static inline int axp_gpio_init(void) { return 0; }
 #endif
 #endif /* _SUNXI_GPIO_H */

arch/arm/include/asm/arch-sunxi/nand.h

View file @ da9971d

1	/*		File was deleted
2	* (C) Copyright 2015 Roy Spliet <rspliet@ultimaker.com>
3	*
4	* SPDX-License-Identifier: GPL-2.0+
5	*/
6
7	#ifndef _SUNXI_NAND_H
8	#define _SUNXI_NAND_H
9
10	#include <linux/types.h>
11
12	struct sunxi_nand
13	{
14	u32 ctl; /* 0x000 Configure and control */
15	u32 st; /* 0x004 Status information */
16	u32 intr; /* 0x008 Interrupt control */
17	u32 timing_ctl; /* 0x00C Timing control */
18	u32 timing_cfg; /* 0x010 Timing configure */
19	u32 addr_low; /* 0x014 Low word address */
20	u32 addr_high; /* 0x018 High word address */
21	u32 block_num; /* 0x01C Data block number */
22	u32 data_cnt; /* 0x020 Data counter for transfer */
23	u32 cmd; /* 0x024 NDFC commands */
24	u32 rcmd_set; /* 0x028 Read command set for vendor NAND mem */
25	u32 wcmd_set; /* 0x02C Write command set */
26	u32 io_data; /* 0x030 IO data */
27	u32 ecc_ctl; /* 0x034 ECC configure and control */
28	u32 ecc_st; /* 0x038 ECC status and operation info */
29	u32 efr; /* 0x03C Enhanced feature */
30	u32 err_cnt0; /* 0x040 Corrected error bit counter 0 */
31	u32 err_cnt1; /* 0x044 Corrected error bit counter 1 */
32	u32 user_data[16]; /* 0x050[16] User data field */
33	u32 efnand_st; /* 0x090 EFNAND status */
34	u32 res0[3];
35	u32 spare_area; /* 0x0A0 Spare area configure */
36	u32 pat_id; /* 0x0A4 Pattern ID register */
37	u32 rdata_sta_ctl; /* 0x0A8 Read data status control */
38	u32 rdata_sta_0; /* 0x0AC Read data status 0 */
39	u32 rdata_sta_1; /* 0x0B0 Read data status 1 */
40	u32 res1[3];
41	u32 mdma_addr; /* 0x0C0 MBUS DMA Address */
42	u32 mdma_cnt; /* 0x0C4 MBUS DMA data counter */
43	};
44
45	#define SUNXI_NAND_CTL_EN (1 << 0)
46	#define SUNXI_NAND_CTL_RST (1 << 1)
47	#define SUNXI_NAND_CTL_PAGE_SIZE(a) ((fls(a) - 11) << 8)
48	#define SUNXI_NAND_CTL_RAM_METHOD_DMA (1 << 14)
49
50	#define SUNXI_NAND_ST_CMD_INT (1 << 1)
51	#define SUNXI_NAND_ST_DMA_INT (1 << 2)
52	#define SUNXI_NAND_ST_FIFO_FULL (1 << 3)
53
54	#define SUNXI_NAND_CMD_ADDR_CYCLES(a) ((a - 1) << 16);
55	#define SUNXI_NAND_CMD_SEND_CMD1 (1 << 22)
56	#define SUNXI_NAND_CMD_WAIT_FLAG (1 << 23)
57	#define SUNXI_NAND_CMD_ORDER_INTERLEAVE 0
58	#define SUNXI_NAND_CMD_ORDER_SEQ (1 << 25)
59
60	#define SUNXI_NAND_ECC_CTL_ECC_EN (1 << 0)
61	#define SUNXI_NAND_ECC_CTL_PIPELINE (1 << 3)
62	#define SUNXI_NAND_ECC_CTL_BS_512B (1 << 5)
63	#define SUNXI_NAND_ECC_CTL_RND_EN (1 << 9)
64	#define SUNXI_NAND_ECC_CTL_MODE(a) ((a) << 12)
65	#define SUNXI_NAND_ECC_CTL_RND_SEED(a) ((a) << 16)
66
67	#endif /* _SUNXI_NAND_H */
68		1	/*

board/sunxi/Kconfig

Diff comments View file @ da9971d

 if ARCH_SUNXI
 # Note only one of these may be selected at a time! But hidden choices are
 # not supported by Kconfig
 config SUNXI_GEN_SUN4I
 	bool
 	---help---
 	Select this for sunxi SoCs which have resets and clocks set up
 	as the original A10 (mach-sun4i).
 config SUNXI_GEN_SUN6I
 	bool
 	---help---
 	Select this for sunxi SoCs which have sun6i like periphery, like
 	separate ahb reset control registers, custom pmic bus, new style
 	watchdog, etc.
 choice
 	prompt "Sunxi SoC Variant"
 	optional
 config MACH_SUN4I
 	bool "sun4i (Allwinner A10)"
 	select CPU_V7
 	select SUNXI_GEN_SUN4I
 	select SUPPORT_SPL
 config MACH_SUN5I
 	bool "sun5i (Allwinner A13)"
 	select CPU_V7
 	select SUNXI_GEN_SUN4I
 	select SUPPORT_SPL
 config MACH_SUN6I
 	bool "sun6i (Allwinner A31)"
 	select CPU_V7
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 config MACH_SUN7I
 	bool "sun7i (Allwinner A20)"
 	select CPU_V7
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select SUNXI_GEN_SUN4I
 	select SUPPORT_SPL
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 config MACH_SUN8I_A23
 	bool "sun8i (Allwinner A23)"
 	select CPU_V7
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 config MACH_SUN8I_A33
 	bool "sun8i (Allwinner A33)"
 	select CPU_V7
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 config MACH_SUN9I
 	bool "sun9i (Allwinner A80)"
 	select CPU_V7
 	select SUNXI_GEN_SUN6I
 endchoice
 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
 config MACH_SUN8I
 	bool
 	default y if MACH_SUN8I_A23 || MACH_SUN8I_A33
 config DRAM_CLK
 	int "sunxi dram clock speed"
 	default 312 if MACH_SUN6I || MACH_SUN8I
 	default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
 	---help---
 	Set the dram clock speed, valid range 240 - 480, must be a multiple
 	of 24.
 if MACH_SUN5I || MACH_SUN7I
 config DRAM_MBUS_CLK
 	int "sunxi mbus clock speed"
 	default 300
 	---help---
 	Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
 endif
 config DRAM_ZQ
 	int "sunxi dram zq value"
 	default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
 	default 127 if MACH_SUN7I
 	---help---
 	Set the dram zq value.
 config DRAM_ODT_EN
 	bool "sunxi dram odt enable"
 	default n if !MACH_SUN8I_A23
 	default y if MACH_SUN8I_A23
 	---help---
 	Select this to enable dram odt (on die termination).
 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
 config DRAM_EMR1
 	int "sunxi dram emr1 value"
 	default 0 if MACH_SUN4I
 	default 4 if MACH_SUN5I || MACH_SUN7I
 	---help---
 	Set the dram controller emr1 value.
 config DRAM_TPR3
 	hex "sunxi dram tpr3 value"
 	default 0
 	---help---
 	Set the dram controller tpr3 parameter. This parameter configures
 	the delay on the command lane and also phase shifts, which are
 	applied for sampling incoming read data. The default value 0
 	means that no phase/delay adjustments are necessary. Properly
 	configuring this parameter increases reliability at high DRAM
 	clock speeds.
 config DRAM_DQS_GATING_DELAY
 	hex "sunxi dram dqs_gating_delay value"
 	default 0
 	---help---
 	Set the dram controller dqs_gating_delay parmeter. Each byte
 	encodes the DQS gating delay for each byte lane. The delay
 	granularity is 1/4 cycle. For example, the value 0x05060606
 	means that the delay is 5 quarter-cycles for one lane (1.25
 	cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
 	The default value 0 means autodetection. The results of hardware
 	autodetection are not very reliable and depend on the chip
 	temperature (sometimes producing different results on cold start
 	and warm reboot). But the accuracy of hardware autodetection
 	is usually good enough, unless running at really high DRAM
 	clocks speeds (up to 600MHz). If unsure, keep as 0.
 choice
 	prompt "sunxi dram timings"
 	default DRAM_TIMINGS_VENDOR_MAGIC
 	---help---
 	Select the timings of the DDR3 chips.
 config DRAM_TIMINGS_VENDOR_MAGIC
 	bool "Magic vendor timings from Android"
 	---help---
 	The same DRAM timings as in the Allwinner boot0 bootloader.
 config DRAM_TIMINGS_DDR3_1066F_1333H
 	bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
 	---help---
 	Use the timings of the standard JEDEC DDR3-1066F speed bin for
 	DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
 	for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
 	used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
 	or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
 	that down binning to DDR3-1066F is supported (because DDR3-1066F
 	uses a bit faster timings than DDR3-1333H).
 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
 	bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
 	---help---
 	Use the timings of the slowest possible JEDEC speed bin for the
 	selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
 	DDR3-800E, DDR3-1066G or DDR3-1333J.
 endchoice
 endif
 if MACH_SUN8I_A23
 config DRAM_ODT_CORRECTION
 	int "sunxi dram odt correction value"
 	default 0
 	---help---
 	Set the dram odt correction value (range -255 - 255). In allwinner
 	fex files, this option is found in bits 8-15 of the u32 odt_en variable
 	in the [dram] section. When bit 31 of the odt_en variable is set
 	then the correction is negative. Usually the value for this is 0.
 endif
 config SYS_CLK_FREQ
 	default 912000000 if MACH_SUN7I
 	default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
 config SYS_CONFIG_NAME
 	default "sun4i" if MACH_SUN4I
 	default "sun5i" if MACH_SUN5I
 	default "sun6i" if MACH_SUN6I
 	default "sun7i" if MACH_SUN7I
 	default "sun8i" if MACH_SUN8I
 	default "sun9i" if MACH_SUN9I
 config SYS_BOARD
 	default "sunxi"
 config SYS_SOC
 	default "sunxi"
 config UART0_PORT_F
 	bool "UART0 on MicroSD breakout board"
 	default n
 	---help---
 	Repurpose the SD card slot for getting access to the UART0 serial
 	console. Primarily useful only for low level u-boot debugging on
 	tablets, where normal UART0 is difficult to access and requires
 	device disassembly and/or soldering. As the SD card can't be used
 	at the same time, the system can be only booted in the FEL mode.
 	Only enable this if you really know what you are doing.
 config OLD_SUNXI_KERNEL_COMPAT
 	boolean "Enable workarounds for booting old kernels"
 	default n
 	---help---
 	Set this to enable various workarounds for old kernels, this results in
 	sub-optimal settings for newer kernels, only enable if needed.
 config MMC0_CD_PIN
 	string "Card detect pin for mmc0"
 	default ""
 	---help---
 	Set the card detect pin for mmc0, leave empty to not use cd. This
 	takes a string in the format understood by sunxi_name_to_gpio, e.g.
 	PH1 for pin 1 of port H.
 config MMC1_CD_PIN
 	string "Card detect pin for mmc1"
 	default ""
 	---help---
 	See MMC0_CD_PIN help text.
 config MMC2_CD_PIN
 	string "Card detect pin for mmc2"
 	default ""
 	---help---
 	See MMC0_CD_PIN help text.
 config MMC3_CD_PIN
 	string "Card detect pin for mmc3"
 	default ""
 	---help---
 	See MMC0_CD_PIN help text.
 config MMC1_PINS
 	string "Pins for mmc1"
 	default ""
 	---help---
 	Set the pins used for mmc1, when applicable. This takes a string in the
 	format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
 config MMC2_PINS
 	string "Pins for mmc2"
 	default ""
 	---help---
 	See MMC1_PINS help text.
 config MMC3_PINS
 	string "Pins for mmc3"
 	default ""
 	---help---
 	See MMC1_PINS help text.
 config MMC_SUNXI_SLOT_EXTRA
 	int "mmc extra slot number"
 	default -1
 	---help---
 	sunxi builds always enable mmc0, some boards also have a second sdcard
 	slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
 	support for this.
-config SPL_NAND_SUPPORT
-	bool "SPL/NAND mode support"
-	depends on SPL
-	default n
-	---help---
-	  This enables support for booting from NAND internal
-	  memory. U-Boot SPL doesn't detect where is it load from,
-	  therefore this option is needed to properly load image from
-	  flash. Option also disables MMC functionality on U-Boot due to
-	  initialization errors encountered, when both controllers are
-	  enabled.
 config USB0_VBUS_PIN
 	string "Vbus enable pin for usb0 (otg)"
 	default ""
 	---help---
 	Set the Vbus enable pin for usb0 (otg). This takes a string in the
 	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 config USB0_VBUS_DET
 	string "Vbus detect pin for usb0 (otg)"
 	default ""
 	---help---
 	Set the Vbus detect pin for usb0 (otg). This takes a string in the
 	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 config USB1_VBUS_PIN
 	string "Vbus enable pin for usb1 (ehci0)"
 	default "PH6" if MACH_SUN4I || MACH_SUN7I
 	default "PH27" if MACH_SUN6I
 	---help---
 	Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
 	a string in the format understood by sunxi_name_to_gpio, e.g.
 	PH1 for pin 1 of port H.
 config USB2_VBUS_PIN
 	string "Vbus enable pin for usb2 (ehci1)"
 	default "PH3" if MACH_SUN4I || MACH_SUN7I
 	default "PH24" if MACH_SUN6I
 	---help---
 	See USB1_VBUS_PIN help text.
 config I2C0_ENABLE
 	bool "Enable I2C/TWI controller 0"
 	default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
 	default n if MACH_SUN6I || MACH_SUN8I
 	---help---
 	This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
 	its clock and setting up the bus. This is especially useful on devices
 	with slaves connected to the bus or with pins exposed through e.g. an
 	expansion port/header.
 config I2C1_ENABLE
 	bool "Enable I2C/TWI controller 1"
 	default n
 	---help---
 	See I2C0_ENABLE help text.
 config I2C2_ENABLE
 	bool "Enable I2C/TWI controller 2"
 	default n
 	---help---
 	See I2C0_ENABLE help text.
 if MACH_SUN6I || MACH_SUN7I
 config I2C3_ENABLE
 	bool "Enable I2C/TWI controller 3"
 	default n
 	---help---
 	See I2C0_ENABLE help text.
 endif
 if MACH_SUN7I
 config I2C4_ENABLE
 	bool "Enable I2C/TWI controller 4"
 	default n
 	---help---
 	See I2C0_ENABLE help text.
 endif
 config AXP_GPIO
 	boolean "Enable support for gpio-s on axp PMICs"
 	default n
 	---help---
 	Say Y here to enable support for the gpio pins of the axp PMIC ICs.
 config VIDEO
 	boolean "Enable graphical uboot console on HDMI, LCD or VGA"
 	default y
 	---help---
 	Say Y here to add support for using a cfb console on the HDMI, LCD
 	or VGA output found on most sunxi devices. See doc/README.video for
 	info on how to select the video output and mode.
 config VIDEO_HDMI
 	boolean "HDMI output support"
 	depends on VIDEO && !MACH_SUN8I
 	default y
 	---help---
 	Say Y here to add support for outputting video over HDMI.
 config VIDEO_VGA
 	boolean "VGA output support"
 	depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
 	default n
 	---help---
 	Say Y here to add support for outputting video over VGA.
 config VIDEO_VGA_VIA_LCD
 	boolean "VGA via LCD controller support"
 	depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
 	default n
 	---help---
 	Say Y here to add support for external DACs connected to the parallel
 	LCD interface driving a VGA connector, such as found on the
 	Olimex A13 boards.
 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
 	boolean "Force sync active high for VGA via LCD controller support"
 	depends on VIDEO_VGA_VIA_LCD
 	default n
 	---help---
 	Say Y here if you've a board which uses opendrain drivers for the vga
 	hsync and vsync signals. Opendrain drivers cannot generate steep enough
 	positive edges for a stable video output, so on boards with opendrain
 	drivers the sync signals must always be active high.
 config VIDEO_VGA_EXTERNAL_DAC_EN
 	string "LCD panel power enable pin"
 	depends on VIDEO_VGA_VIA_LCD
 	default ""
 	---help---
 	Set the enable pin for the external VGA DAC. This takes a string in the
 	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 config VIDEO_LCD_MODE
 	string "LCD panel timing details"
 	depends on VIDEO
 	default ""
 	---help---
 	LCD panel timing details string, leave empty if there is no LCD panel.
 	This is in drivers/video/videomodes.c: video_get_params() format, e.g.
 	x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
 config VIDEO_LCD_DCLK_PHASE
 	int "LCD panel display clock phase"
 	depends on VIDEO
 	default 1
 	---help---
 	Select LCD panel display clock phase shift, range 0-3.
 config VIDEO_LCD_POWER
 	string "LCD panel power enable pin"
 	depends on VIDEO
 	default ""
 	---help---
 	Set the power enable pin for the LCD panel. This takes a string in the
 	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 config VIDEO_LCD_RESET
 	string "LCD panel reset pin"
 	depends on VIDEO
 	default ""
 	---help---
 	Set the reset pin for the LCD panel. This takes a string in the format
 	understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 config VIDEO_LCD_BL_EN
 	string "LCD panel backlight enable pin"
 	depends on VIDEO
 	default ""
 	---help---
 	Set the backlight enable pin for the LCD panel. This takes a string in the
 	the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
 	port H.
 config VIDEO_LCD_BL_PWM
 	string "LCD panel backlight pwm pin"
 	depends on VIDEO
 	default ""
 	---help---
 	Set the backlight pwm pin for the LCD panel. This takes a string in the
 	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
 	bool "LCD panel backlight pwm is inverted"
 	depends on VIDEO
 	default y
 	---help---
 	Set this if the backlight pwm output is active low.
 config VIDEO_LCD_PANEL_I2C
 	bool "LCD panel needs to be configured via i2c"
 	depends on VIDEO
 	default n
 	---help---
 	Say y here if the LCD panel needs to be configured via i2c. This
 	will add a bitbang i2c controller using gpios to talk to the LCD.
 config VIDEO_LCD_PANEL_I2C_SDA
 	string "LCD panel i2c interface SDA pin"
 	depends on VIDEO_LCD_PANEL_I2C
 	default "PG12"
 	---help---
 	Set the SDA pin for the LCD i2c interface. This takes a string in the
 	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 config VIDEO_LCD_PANEL_I2C_SCL
 	string "LCD panel i2c interface SCL pin"
 	depends on VIDEO_LCD_PANEL_I2C
 	default "PG10"
 	---help---
 	Set the SCL pin for the LCD i2c interface. This takes a string in the
 	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 # Note only one of these may be selected at a time! But hidden choices are
 # not supported by Kconfig
 config VIDEO_LCD_IF_PARALLEL
 	bool
 config VIDEO_LCD_IF_LVDS
 	bool
 choice
 	prompt "LCD panel support"
 	depends on VIDEO
 	---help---
 	Select which type of LCD panel to support.
 config VIDEO_LCD_PANEL_PARALLEL
 	bool "Generic parallel interface LCD panel"
 	select VIDEO_LCD_IF_PARALLEL
 config VIDEO_LCD_PANEL_LVDS
 	bool "Generic lvds interface LCD panel"
 	select VIDEO_LCD_IF_LVDS
 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
 	bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
 	select VIDEO_LCD_SSD2828
 	select VIDEO_LCD_IF_PARALLEL
 	---help---
 	 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
 	bool "Hitachi tx18d42vm LCD panel"
 	select VIDEO_LCD_HITACHI_TX18D42VM
 	select VIDEO_LCD_IF_LVDS
 	---help---
 	7.85" 1024x768 Hitachi tx18d42vm LCD panel support
 config VIDEO_LCD_TL059WV5C0
 	bool "tl059wv5c0 LCD panel"
 	select VIDEO_LCD_PANEL_I2C
 	select VIDEO_LCD_IF_PARALLEL
 	---help---
 	6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
 	Aigo M60/M608/M606 tablets.
 endchoice
 config USB_MUSB_SUNXI
 	bool "Enable sunxi OTG / DRC USB controller in host mode"
 	default n
 	---help---
 	Say y here to enable support for the sunxi OTG / DRC USB controller
 	used on almost all sunxi boards. Note currently u-boot can only have
 	one usb host controller enabled at a time, so enabling this on boards
 	which also use the ehci host controller will result in build errors.
 config USB_KEYBOARD
 	boolean "Enable USB keyboard support"
 	default y
 	---help---
 	Say Y here to add support for using a USB keyboard (typically used
 	in combination with a graphical console).
 config GMAC_TX_DELAY
 	int "GMAC Transmit Clock Delay Chain"
 	default 0
 	---help---
 	Set the GMAC Transmit Clock Delay Chain value.
 endif

board/sunxi/board.c

Diff comments View file @ da9971d

 /*
  * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
  * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  *
  * (C) Copyright 2007-2011
  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  * Tom Cubie <tangliang@allwinnertech.com>
  *
  * Some board init for the Allwinner A10-evb board.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <mmc.h>
 #ifdef CONFIG_AXP152_POWER
 #include <axp152.h>
 #endif
 #ifdef CONFIG_AXP209_POWER
 #include <axp209.h>
 #endif
 #ifdef CONFIG_AXP221_POWER
 #include <axp221.h>
 #endif
-#ifdef CONFIG_NAND_SUNXI
-#include <nand.h>
-#endif
 #include <asm/arch/clock.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/display.h>
 #include <asm/arch/dram.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/usb_phy.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <linux/usb/musb.h>
 #include <net.h>
 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
 int soft_i2c_gpio_sda;
 int soft_i2c_gpio_scl;
 static int soft_i2c_board_init(void)
 {
 	int ret;
 	soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
 	if (soft_i2c_gpio_sda < 0) {
 		printf("Error invalid soft i2c sda pin: '%s', err %d\n",
 		       CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
 		return soft_i2c_gpio_sda;
 	}
 	ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
 	if (ret) {
 		printf("Error requesting soft i2c sda pin: '%s', err %d\n",
 		       CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
 		return ret;
 	}
 	soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
 	if (soft_i2c_gpio_scl < 0) {
 		printf("Error invalid soft i2c scl pin: '%s', err %d\n",
 		       CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
 		return soft_i2c_gpio_scl;
 	}
 	ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
 	if (ret) {
 		printf("Error requesting soft i2c scl pin: '%s', err %d\n",
 		       CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
 		return ret;
 	}
 	return 0;
 }
 #else
 static int soft_i2c_board_init(void) { return 0; }
 #endif
 DECLARE_GLOBAL_DATA_PTR;
 /* add board specific code here */
 int board_init(void)
 {
 	int id_pfr1, ret;
 	gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
 	asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
 	debug("id_pfr1: 0x%08x\n", id_pfr1);
 	/* Generic Timer Extension available? */
 	if ((id_pfr1 >> 16) & 0xf) {
 		debug("Setting CNTFRQ\n");
 		/* CNTFRQ == 24 MHz */
 		asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000));
 	}
 	ret = axp_gpio_init();
 	if (ret)
 		return ret;
 	/* Uses dm gpio code so do this here and not in i2c_init_board() */
 	return soft_i2c_board_init();
 }
 int dram_init(void)
 {
 	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
 	return 0;
 }
 #ifdef CONFIG_GENERIC_MMC
 static void mmc_pinmux_setup(int sdc)
 {
 	unsigned int pin;
 	__maybe_unused int pins;
 	switch (sdc) {
 	case 0:
 		/* SDC0: PF0-PF5 */
 		for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
 			sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
 			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 			sunxi_gpio_set_drv(pin, 2);
 		}
 		break;
 	case 1:
 		pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
 		if (pins == SUNXI_GPIO_H) {
 			/* SDC1: PH22-PH-27 */
 			for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
 				sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
 				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 				sunxi_gpio_set_drv(pin, 2);
 			}
 		} else {
 			/* SDC1: PG0-PG5 */
 			for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
 				sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
 				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 				sunxi_gpio_set_drv(pin, 2);
 			}
 		}
 #elif defined(CONFIG_MACH_SUN5I)
 		/* SDC1: PG3-PG8 */
 		for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
 			sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
 			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 			sunxi_gpio_set_drv(pin, 2);
 		}
 #elif defined(CONFIG_MACH_SUN6I)
 		/* SDC1: PG0-PG5 */
 		for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
 			sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
 			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 			sunxi_gpio_set_drv(pin, 2);
 		}
 #elif defined(CONFIG_MACH_SUN8I)
 		if (pins == SUNXI_GPIO_D) {
 			/* SDC1: PD2-PD7 */
 			for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
 				sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
 				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 				sunxi_gpio_set_drv(pin, 2);
 			}
 		} else {
 			/* SDC1: PG0-PG5 */
 			for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
 				sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
 				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 				sunxi_gpio_set_drv(pin, 2);
 			}
 		}
 #endif
 		break;
 	case 2:
 		pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
 		/* SDC2: PC6-PC11 */
 		for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
 			sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
 			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 			sunxi_gpio_set_drv(pin, 2);
 		}
 #elif defined(CONFIG_MACH_SUN5I)
 		if (pins == SUNXI_GPIO_E) {
 			/* SDC2: PE4-PE9 */
 			for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
 				sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
 				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 				sunxi_gpio_set_drv(pin, 2);
 			}
 		} else {
 			/* SDC2: PC6-PC15 */
 			for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
 				sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
 				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 				sunxi_gpio_set_drv(pin, 2);
 			}
 		}
 #elif defined(CONFIG_MACH_SUN6I)
 		if (pins == SUNXI_GPIO_A) {
 			/* SDC2: PA9-PA14 */
 			for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
 				sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
 				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 				sunxi_gpio_set_drv(pin, 2);
 			}
 		} else {
 			/* SDC2: PC6-PC15, PC24 */
 			for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
 				sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
 				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 				sunxi_gpio_set_drv(pin, 2);
 			}
 			sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
 			sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
 			sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
 		}
 #elif defined(CONFIG_MACH_SUN8I)
 		/* SDC2: PC5-PC6, PC8-PC16 */
 		for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
 			sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
 			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 			sunxi_gpio_set_drv(pin, 2);
 		}
 		for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
 			sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
 			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 			sunxi_gpio_set_drv(pin, 2);
 		}
 #endif
 		break;
 	case 3:
 		pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
 		/* SDC3: PI4-PI9 */
 		for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
 			sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
 			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 			sunxi_gpio_set_drv(pin, 2);
 		}
 #elif defined(CONFIG_MACH_SUN6I)
 		if (pins == SUNXI_GPIO_A) {
 			/* SDC3: PA9-PA14 */
 			for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
 				sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
 				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 				sunxi_gpio_set_drv(pin, 2);
 			}
 		} else {
 			/* SDC3: PC6-PC15, PC24 */
 			for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
 				sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
 				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 				sunxi_gpio_set_drv(pin, 2);
 			}
 			sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
 			sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
 			sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
 		}
 #endif
 		break;
 	default:
 		printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
 		break;
 	}
 }
 int board_mmc_init(bd_t *bis)
 {
 	__maybe_unused struct mmc *mmc0, *mmc1;
 	__maybe_unused char buf[512];
 	mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
 	mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
 	if (!mmc0)
 		return -1;
 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
 	mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
 	mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
 	if (!mmc1)
 		return -1;
 #endif
 #if CONFIG_MMC_SUNXI_SLOT == 0 && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2
 	/*
 	 * Both mmc0 and mmc2 are bootable, figure out where we're booting
 	 * from. Try mmc0 first, just like the brom does.
 	 */
 	if (mmc_getcd(mmc0) && mmc_init(mmc0) == 0 &&
 	    mmc0->block_dev.block_read(0, 16, 1, buf) == 1) {
 		buf[12] = 0;
 		if (strcmp(&buf[4], "eGON.BT0") == 0)
 			return 0;
 	}
 	/* no bootable card in mmc0, so we must be booting from mmc2, swap */
 	mmc0->block_dev.dev = 1;
 	mmc1->block_dev.dev = 0;
 #endif
 	return 0;
-}
-#endif
-#ifdef CONFIG_NAND
-void board_nand_init(void)
-{
-	unsigned int pin;
-	static u8 ports[] = CONFIG_NAND_SUNXI_GPC_PORTS;
-	/* Configure AHB muxes to connect output pins with NAND controller */
-	for (pin = 0; pin < 16; pin++)
-		sunxi_gpio_set_cfgpin(SUNXI_GPC(pin), SUNXI_GPC_NAND);
-	for (pin = 0; pin < ARRAY_SIZE(ports); pin++)
-		sunxi_gpio_set_cfgpin(SUNXI_GPC(ports[pin]), SUNXI_GPC_NAND);
 }
 #endif
 void i2c_init_board(void)
 {
 #ifdef CONFIG_I2C0_ENABLE
 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
 	clock_twi_onoff(0, 1);
 #elif defined(CONFIG_MACH_SUN6I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
 	clock_twi_onoff(0, 1);
 #elif defined(CONFIG_MACH_SUN8I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
 	clock_twi_onoff(0, 1);
 #endif
 #endif
 #ifdef CONFIG_I2C1_ENABLE
 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
 	clock_twi_onoff(1, 1);
 #elif defined(CONFIG_MACH_SUN5I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
 	clock_twi_onoff(1, 1);
 #elif defined(CONFIG_MACH_SUN6I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
 	clock_twi_onoff(1, 1);
 #elif defined(CONFIG_MACH_SUN8I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
 	clock_twi_onoff(1, 1);
 #endif
 #endif
 #ifdef CONFIG_I2C2_ENABLE
 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
 	clock_twi_onoff(2, 1);
 #elif defined(CONFIG_MACH_SUN5I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
 	clock_twi_onoff(2, 1);
 #elif defined(CONFIG_MACH_SUN6I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
 	clock_twi_onoff(2, 1);
 #elif defined(CONFIG_MACH_SUN8I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
 	sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
 	clock_twi_onoff(2, 1);
 #endif
 #endif
 #ifdef CONFIG_I2C3_ENABLE
 #if defined(CONFIG_MACH_SUN6I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
 	sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
 	clock_twi_onoff(3, 1);
 #elif defined(CONFIG_MACH_SUN7I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
 	sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
 	clock_twi_onoff(3, 1);
 #endif
 #endif
 #ifdef CONFIG_I2C4_ENABLE
 #if defined(CONFIG_MACH_SUN7I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
 	sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
 	clock_twi_onoff(4, 1);
 #endif
 #endif
 }
 #ifdef CONFIG_SPL_BUILD
 void sunxi_board_init(void)
 {
 	int power_failed = 0;
 	unsigned long ramsize;
 #ifdef CONFIG_AXP152_POWER
 	power_failed = axp152_init();
 	power_failed |= axp152_set_dcdc2(1400);
 	power_failed |= axp152_set_dcdc3(1500);
 	power_failed |= axp152_set_dcdc4(1250);
 	power_failed |= axp152_set_ldo2(3000);
 #endif
 #ifdef CONFIG_AXP209_POWER
 	power_failed |= axp209_init();
 	power_failed |= axp209_set_dcdc2(1400);
 	power_failed |= axp209_set_dcdc3(1250);
 	power_failed |= axp209_set_ldo2(3000);
 	power_failed |= axp209_set_ldo3(2800);
 	power_failed |= axp209_set_ldo4(2800);
 #endif
 #ifdef CONFIG_AXP221_POWER
 	power_failed = axp221_init();
 	power_failed |= axp221_set_dcdc1(CONFIG_AXP221_DCDC1_VOLT);
 	power_failed |= axp221_set_dcdc2(1200); /* A31:VDD-GPU, A23:VDD-SYS */
 	power_failed |= axp221_set_dcdc3(1200); /* VDD-CPU */
 #ifdef CONFIG_MACH_SUN6I
 	power_failed |= axp221_set_dcdc4(1200); /* A31:VDD-SYS */
 #else
 	power_failed |= axp221_set_dcdc4(0);    /* A23:unused */
 #endif
 	power_failed |= axp221_set_dcdc5(1500); /* VCC-DRAM */
 	power_failed |= axp221_set_dldo1(CONFIG_AXP221_DLDO1_VOLT);
 	power_failed |= axp221_set_dldo4(CONFIG_AXP221_DLDO4_VOLT);
 	power_failed |= axp221_set_aldo1(CONFIG_AXP221_ALDO1_VOLT);
 	power_failed |= axp221_set_aldo2(CONFIG_AXP221_ALDO2_VOLT);
 	power_failed |= axp221_set_aldo3(CONFIG_AXP221_ALDO3_VOLT);
 	power_failed |= axp221_set_eldo(3, CONFIG_AXP221_ELDO3_VOLT);
 #endif
 	printf("DRAM:");
 	ramsize = sunxi_dram_init();
 	printf(" %lu MiB\n", ramsize >> 20);
 	if (!ramsize)
 		hang();
 	/*
 	 * Only clock up the CPU to full speed if we are reasonably
 	 * assured it's being powered with suitable core voltage
 	 */
 	if (!power_failed)
 		clock_set_pll1(CONFIG_SYS_CLK_FREQ);
 	else
 		printf("Failed to set core voltage! Can't set CPU frequency\n");
 }
 #endif
 #if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET)
 extern const struct musb_platform_ops sunxi_musb_ops;
 static struct musb_hdrc_config musb_config = {
 	.multipoint     = 1,
 	.dyn_fifo       = 1,
 	.num_eps        = 6,
 	.ram_bits       = 11,
 };
 static struct musb_hdrc_platform_data musb_plat = {
 #if defined(CONFIG_MUSB_HOST)
 	.mode           = MUSB_HOST,
 #else
 	.mode		= MUSB_PERIPHERAL,
 #endif
 	.config         = &musb_config,
 	.power          = 250,
 	.platform_ops	= &sunxi_musb_ops,
 };
 #endif
 #ifdef CONFIG_USB_GADGET
 int g_dnl_board_usb_cable_connected(void)
 {
 	return sunxi_usb_phy_vbus_detect(0);
 }
 #endif
 #ifdef CONFIG_SERIAL_TAG
 void get_board_serial(struct tag_serialnr *serialnr)
 {
 	char *serial_string;
 	unsigned long long serial;
 	serial_string = getenv("serial#");
 	if (serial_string) {
 		serial = simple_strtoull(serial_string, NULL, 16);
 		serialnr->high = (unsigned int) (serial >> 32);
 		serialnr->low = (unsigned int) (serial & 0xffffffff);
 	} else {
 		serialnr->high = 0;
 		serialnr->low = 0;
 	}
 }
 #endif
 #ifdef CONFIG_MISC_INIT_R
 int misc_init_r(void)
 {
 	char serial_string[17] = { 0 };
 	unsigned int sid[4];
 	uint8_t mac_addr[6];
 	int ret;
 	ret = sunxi_get_sid(sid);
 	if (ret == 0 && sid[0] != 0 && sid[3] != 0) {
 		if (!getenv("ethaddr")) {
 			/* Non OUI / registered MAC address */
 			mac_addr[0] = 0x02;
 			mac_addr[1] = (sid[0] >>  0) & 0xff;
 			mac_addr[2] = (sid[3] >> 24) & 0xff;
 			mac_addr[3] = (sid[3] >> 16) & 0xff;
 			mac_addr[4] = (sid[3] >>  8) & 0xff;
 			mac_addr[5] = (sid[3] >>  0) & 0xff;
 			eth_setenv_enetaddr("ethaddr", mac_addr);
 		}
 		if (!getenv("serial#")) {
 			snprintf(serial_string, sizeof(serial_string),
 				"%08x%08x", sid[0], sid[3]);
 			setenv("serial#", serial_string);
 		}
 	}
 #ifndef CONFIG_MACH_SUN9I
 	ret = sunxi_usb_phy_probe();
 	if (ret)
 		return ret;
 #endif
 #if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET)
 	musb_register(&musb_plat, NULL, (void *)SUNXI_USB0_BASE);
 #endif
 	return 0;
 }
 #endif
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
 	return sunxi_simplefb_setup(blob);
 #endif
 }
 #endif /* CONFIG_OF_BOARD_SETUP */

drivers/mtd/nand/Makefile

Diff comments View file @ da9971d

 #
 # (C) Copyright 2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
 ifdef CONFIG_SPL_BUILD
 ifdef CONFIG_SPL_NAND_DRIVERS
 NORMAL_DRIVERS=y
 endif
 obj-$(CONFIG_SPL_NAND_AM33XX_BCH) += am335x_spl_bch.o
 obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o
 obj-$(CONFIG_SPL_NAND_DOCG4) += docg4_spl.o
 obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o
 obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o
 obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o
 obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o
 obj-$(CONFIG_SPL_NAND_INIT) += nand.o
 ifeq ($(CONFIG_SPL_ENV_SUPPORT),y)
 obj-$(CONFIG_ENV_IS_IN_NAND) += nand_util.o
 endif
 else # not spl
 NORMAL_DRIVERS=y
 obj-y += nand.o
 obj-y += nand_bbt.o
 obj-y += nand_ids.o
 obj-y += nand_util.o
 obj-y += nand_ecc.o
 obj-y += nand_base.o
 endif # not spl
 ifdef NORMAL_DRIVERS
 obj-$(CONFIG_NAND_ECC_BCH) += nand_bch.o
 obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o
 obj-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
 obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
 obj-$(CONFIG_NAND_DENALI) += denali.o
 obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
 obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
 obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
 obj-$(CONFIG_NAND_FSMC) += fsmc_nand.o
 obj-$(CONFIG_NAND_JZ4740) += jz4740_nand.o
 obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o
 obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
 obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
 obj-$(CONFIG_NAND_LPC32XX_MLC) += lpc32xx_nand_mlc.o
 obj-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
 obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
 obj-$(CONFIG_NAND_MXC) += mxc_nand.o
 obj-$(CONFIG_NAND_MXS) += mxs_nand.o
 obj-$(CONFIG_NAND_NDFC) += ndfc.o
 obj-$(CONFIG_NAND_NOMADIK) += nomadik.o
 obj-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o
 obj-$(CONFIG_NAND_SPEAR) += spr_nand.o
 obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o
 obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
 obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o
 obj-$(CONFIG_NAND_PLAT) += nand_plat.o
 obj-$(CONFIG_NAND_DOCG4) += docg4.o
 else  # minimal SPL drivers
 obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o
 obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o
 obj-$(CONFIG_NAND_MXC) += mxc_nand_spl.o
 obj-$(CONFIG_NAND_MXS) += mxs_nand_spl.o mxs_nand.o
-obj-$(CONFIG_NAND_SUNXI) += sunxi_nand_spl.o
 endif # drivers

drivers/mtd/nand/sunxi_nand_spl.c

View file @ da9971d

1	/*		File was deleted
2	* Copyright (c) 2014, Antmicro Ltd <www.antmicro.com>
3	* Copyright (c) 2015, Turtle Solutions <www.turtle-solutions.eu>
4	* Copyright (c) 2015, Roy Spliet <rspliet@ultimaker.com>
5	*
6	* SPDX-License-Identifier: GPL-2.0+
7	*
8	* \todo Detect chip parameters (page size, ECC mode, randomisation...)
9	*/
10
11	#include <common.h>
12	#include <config.h>
13	#include <asm/io.h>
14	#include <nand.h>
15	#include <asm/arch/cpu.h>
16	#include <asm/arch/clock.h>
17	#include <asm/arch/dma.h>
18	#include <asm/arch/nand.h>
19
20	void
21	nand_init(void)
22	{
23	struct sunxi_ccm_reg * const ccm =
24	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
25	struct sunxi_nand * const nand = (struct sunxi_nand *)SUNXI_NFC_BASE;
26	u32 val;
27
28	board_nand_init();
29
30	/* "un-gate" NAND clock and clock source
31	* This assumes that the clock was already correctly configured by
32	* BootROM */
33	setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_NAND0));
34	#ifdef CONFIG_MACH_SUN9I
35	setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
36	#else
37	setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
38	#endif
39	setbits_le32(&ccm->nand0_clk_cfg, 0x80000000);
40
41	val = readl(&nand->ctl);
42	val \|= SUNXI_NAND_CTL_RST;
43	writel(val, &nand->ctl);
44
45	/* Wait until reset pin is deasserted */
46	do {
47	val = readl(&nand->ctl);
48	if (!(val & SUNXI_NAND_CTL_RST))
49	break;
50	} while (1);
51
52	/** \todo Chip select, currently kind of static */
53	val = readl(&nand->ctl);
54	val &= 0xf0fff0f2;
55	val \|= SUNXI_NAND_CTL_EN;
56	val \|= SUNXI_NAND_CTL_PAGE_SIZE(CONFIG_NAND_SUNXI_PAGE_SIZE);
57	writel(val, &nand->ctl);
58
59	writel(0x100, &nand->timing_ctl);
60	writel(0x7ff, &nand->timing_cfg);
61
62	/* reset CMD */
63	val = SUNXI_NAND_CMD_SEND_CMD1 \| SUNXI_NAND_CMD_WAIT_FLAG \|
64	NAND_CMD_RESET;
65	writel(val, &nand->cmd);
66	do {
67	val = readl(&nand->st);
68	if (val & (1<<1))
69	break;
70	udelay(1000);
71	} while (1);
72
73	printf("Nand initialised\n");
74	}
75
76	int
77	nand_wait_timeout(u32 *reg, u32 mask, u32 val)
78	{
79	unsigned long tmo = timer_get_us() + 1000000; /* 1s */
80
81	while ((readl(reg) & mask) != val) {
82	if (timer_get_us() > tmo)
83	return -ETIMEDOUT;
84	}
85
86	return 0;
87	}
88
89	/* random seed */
90	static const uint16_t random_seed[128] = {
91	0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
92	0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
93	0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
94	0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
95	0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
96	0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
97	0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
98	0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
99	0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
100	0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
101	0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
102	0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
103	0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
104	0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
105	0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
106	0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
107	};
108
109	uint32_t ecc_errors = 0;
110
111	static void
112	nand_config_ecc(struct sunxi_nand *nand, uint32_t page, int syndrome)
113	{
114	static u8 strength[] = {16, 24, 28, 32, 40, 48, 56, 60, 64};
115	int i;
116	uint32_t ecc_mode;
117	u32 ecc;
118	u16 seed = 0;
119
120	for (i = 0; i < ARRAY_SIZE(strength); i++) {
121	if (CONFIG_NAND_SUNXI_ECC_STRENGTH == strength[i]) {
122	ecc_mode = i;
123	break;
124	}
125	}
126
127	if (i == ARRAY_SIZE(strength)) {
128	printf("ECC strength unsupported\n");
129	return;
130	}
131
132	ecc = SUNXI_NAND_ECC_CTL_ECC_EN \|
133	SUNXI_NAND_ECC_CTL_PIPELINE \|
134	SUNXI_NAND_ECC_CTL_RND_EN \|
135	SUNXI_NAND_ECC_CTL_MODE(ecc_mode);
136
137	if (CONFIG_NAND_SUNXI_ECC_STEP == 512)
138	ecc \|= SUNXI_NAND_ECC_CTL_BS_512B;
139
140	if (syndrome)
141	seed = 0x4A80;
142	else
143	seed = random_seed[page % ARRAY_SIZE(random_seed)];
144
145	ecc \|= SUNXI_NAND_ECC_CTL_RND_SEED(seed);
146
147	writel(ecc, &nand->ecc_ctl);
148	}
149
150	/* read CONFIG_NAND_SUNXI_ECC_STEP bytes from real_addr to temp_buf */
151	void
152	nand_read_block(struct sunxi_nand *nand, phys_addr_t src, dma_addr_t dst,
153	int syndrome)
154	{
155	struct sunxi_dma * const dma = (struct sunxi_dma *)SUNXI_DMA_BASE;
156	struct sunxi_dma_cfg * const dma_cfg = &dma->ddma[0];
157
158	uint32_t shift;
159	uint32_t page;
160	uint32_t addr;
161	uint32_t oob_offset;
162	uint32_t ecc_bytes;
163	u32 val;
164	u32 cmd;
165
166	page = src / CONFIG_NAND_SUNXI_PAGE_SIZE;
167	if (page > 0xFFFF) {
168	/* TODO: currently this is not supported */
169	printf("Reading from address >= %08X is not allowed.\n",
170	0xFFFF * CONFIG_NAND_SUNXI_PAGE_SIZE);
171	return;
172	}
173
174	shift = src % CONFIG_NAND_SUNXI_PAGE_SIZE;
175	writel(0, &nand->ecc_st);
176
177	/* ECC_CTL, randomization */
178	ecc_bytes = CONFIG_NAND_SUNXI_ECC_STRENGTH *
179	fls(CONFIG_NAND_SUNXI_ECC_STEP * 8);
180	ecc_bytes = DIV_ROUND_UP(ecc_bytes, 8);
181	ecc_bytes += (ecc_bytes & 1); /* Align to 2-bytes */
182	ecc_bytes += 4;
183
184	nand_config_ecc(nand, page, syndrome);
185	if (syndrome) {
186	/* shift every 1kB in syndrome */
187	shift += (shift / CONFIG_NAND_SUNXI_ECC_STEP) * ecc_bytes;
188	oob_offset = CONFIG_NAND_SUNXI_ECC_STEP + shift;
189	} else {
190	oob_offset = CONFIG_NAND_SUNXI_PAGE_SIZE +
191	(shift / CONFIG_NAND_SUNXI_ECC_STEP) * ecc_bytes;
192	}
193
194	addr = (page << 16) \| shift;
195
196	/* DMA */
197	val = readl(&nand->ctl);
198	writel(val \| SUNXI_NAND_CTL_RAM_METHOD_DMA, &nand->ctl);
199
200	writel(oob_offset, &nand->spare_area);
201
202	/* DMAC
203	* \todo Separate this into a tidy driver */
204	writel(0x0, &dma->irq_en); /* clear dma interrupts */
205	writel((uint32_t) &nand->io_data , &dma_cfg->src_addr);
206	writel(dst , &dma_cfg->dst_addr);
207	writel(0x00007F0F , &dma_cfg->ddma_para);
208	writel(CONFIG_NAND_SUNXI_ECC_STEP, &dma_cfg->bc);
209
210	val = SUNXI_DMA_CTL_SRC_DRQ(DDMA_SRC_DRQ_NAND) \|
211	SUNXI_DMA_CTL_MODE_IO \|
212	SUNXI_DMA_CTL_SRC_DATA_WIDTH_32 \|
213	SUNXI_DMA_CTL_DST_DRQ(DDMA_DST_DRQ_SDRAM) \|
214	SUNXI_DMA_CTL_DST_DATA_WIDTH_32 \|
215	SUNXI_DMA_CTL_TRIGGER;
216	writel(val, &dma_cfg->ctl);
217
218	writel(0x00E00530, &nand->rcmd_set);
219	nand_wait_timeout(&nand->st, SUNXI_NAND_ST_FIFO_FULL, 0);
220
221	writel(1 , &nand->block_num);
222	writel(addr, &nand->addr_low);
223	writel(0 , &nand->addr_high);
224
225	/* CMD (PAGE READ) */
226	cmd = 0x85E80000;
227	cmd \|= SUNXI_NAND_CMD_ADDR_CYCLES(CONFIG_NAND_SUNXI_ADDR_CYCLES);
228	cmd \|= (syndrome ? SUNXI_NAND_CMD_ORDER_SEQ :
229	SUNXI_NAND_CMD_ORDER_INTERLEAVE);
230	writel(cmd, &nand->cmd);
231
232	if(nand_wait_timeout(&nand->st, SUNXI_NAND_ST_DMA_INT,
233	SUNXI_NAND_ST_DMA_INT)) {
234	printf("NAND timeout reading data\n");
235	return;
236	}
237
238	if(nand_wait_timeout(&dma_cfg->ctl, SUNXI_DMA_CTL_TRIGGER, 0)) {
239	printf("NAND timeout reading data\n");
240	return;
241	}
242
243	if (readl(&nand->ecc_st))
244	ecc_errors++;
245	}
246
247	int
248	nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
249	{
250	struct sunxi_nand * const nand = (struct sunxi_nand *)SUNXI_NFC_BASE;
251	dma_addr_t dst_block;
252	dma_addr_t dst_end;
253	phys_addr_t addr = offs;
254
255	dst_end = ((dma_addr_t) dest) + size;
256
257	memset((void *)dest, 0x0, size);
258	ecc_errors = 0;
259	for (dst_block = (dma_addr_t) dest; dst_block < dst_end;
260	dst_block += CONFIG_NAND_SUNXI_ECC_STEP,
261	addr += CONFIG_NAND_SUNXI_ECC_STEP) {
262	/* syndrome read first 4MiB to match Allwinner BootROM */
263	nand_read_block(nand, addr, dst_block, addr < 0x400000);
264	}
265
266	if (ecc_errors)
267	printf("Error: %d ECC failures detected\n", ecc_errors);
268	return ecc_errors == 0;
269	}
270
271	void
272	nand_deselect(void)
273	{}
274		1	/*

include/configs/sun4i.h

Diff comments View file @ da9971d

 /*
  * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
  *
  * Configuration settings for the Allwinner A10 (sun4i) CPU
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*
  * A10 specific configuration
  */
 #ifdef CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_SUNXI
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #endif
 #define CONFIG_SUNXI_USB_PHYS	3
-#define CONFIG_NAND_SUNXI_GPC_PORTS	{16, 17, 18, 19, 20, 21, 22, 24}
 /*
  * Include common sunxi configuration where most the settings are
  */
 #include <configs/sunxi-common.h>
 #define CONFIG_MACH_TYPE	(4104 | ((CONFIG_MACH_TYPE_COMPAT_REV) << 28))
 #endif /* __CONFIG_H */

include/configs/sun5i.h

Diff comments View file @ da9971d

 /*
  * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
  *
  * Configuration settings for the Allwinner A13 (sun5i) CPU
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*
  * High Level Configuration Options
  */
 #ifdef CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_SUNXI
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #endif
 #define CONFIG_SUNXI_USB_PHYS	2
-/* \todo A13 only defines port 19, whereas A10s requires each of these */
-#define CONFIG_NAND_SUNXI_GPC_PORTS	{16, 17, 18, 19}
 /*
  * Include common sunxi configuration where most the settings are
  */
 #include <configs/sunxi-common.h>
 #define CONFIG_MACH_TYPE	(4138 | ((CONFIG_MACH_TYPE_COMPAT_REV) << 28))
 #endif /* __CONFIG_H */

include/configs/sun6i.h

Diff comments View file @ da9971d

 /*
  * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
  * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  * (C) Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
  *
  * Configuration settings for the Allwinner A31 (sun6i) CPU
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*
  * A31 specific configuration
  */
 #ifdef CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_SUNXI
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #endif
 #define CONFIG_SUNXI_USB_PHYS	3
 #define CONFIG_ARMV7_PSCI		1
 #define CONFIG_ARMV7_PSCI_NR_CPUS	4
 #define CONFIG_ARMV7_SECURE_BASE	SUNXI_SRAM_B_BASE
 #define CONFIG_TIMER_CLK_FREQ		24000000
-#define CONFIG_NAND_SUNXI_GPC_PORTS	{24, 25, 26}
 /*
  * Include common sunxi configuration where most the settings are
  */
 #include <configs/sunxi-common.h>
 #endif /* __CONFIG_H */

include/configs/sun7i.h

Diff comments View file @ da9971d

 /*
  * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
  * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  *
  * Configuration settings for the Allwinner A20 (sun7i) CPU
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*
  * A20 specific configuration
  */
 #ifdef CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_SUNXI
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #endif
 #define CONFIG_SUNXI_USB_PHYS	3
 #define CONFIG_ARMV7_PSCI		1
 #define CONFIG_ARMV7_SECURE_BASE	SUNXI_SRAM_B_BASE
 #define CONFIG_TIMER_CLK_FREQ		24000000
-#define CONFIG_NAND_SUNXI_GPC_PORTS	{16, 17, 18, 19, 20, 21, 22, 24}
 /*
  * Include common sunxi configuration where most the settings are
  */
 #include <configs/sunxi-common.h>
 #define CONFIG_MACH_TYPE	(4283 | ((CONFIG_MACH_TYPE_COMPAT_REV) << 28))
 #endif /* __CONFIG_H */

include/configs/sun8i.h

Diff comments View file @ da9971d

 /*
  * (C) Copyright 2014 Chen-Yu Tsai <wens@csie.org>
  *
  * Configuration settings for the Allwinner A23 (sun8i) CPU
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*
  * A23 specific configuration
  */
 #ifdef CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_SUNXI
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #endif
 #define CONFIG_SUNXI_USB_PHYS	2
 #define CONFIG_ARMV7_PSCI		1
 #if defined(CONFIG_MACH_SUN8I_A23)
 #define CONFIG_ARMV7_PSCI_NR_CPUS	2
-#define CONFIG_NAND_SUNXI_GPC_PORTS	{16, 17, 18}
 #elif defined(CONFIG_MACH_SUN8I_A33)
 #define CONFIG_ARMV7_PSCI_NR_CPUS	4
-#define CONFIG_NAND_SUNXI_GPC_PORTS	{16}
 #else
 #error Unsupported sun8i variant
 #endif
 #define CONFIG_TIMER_CLK_FREQ		24000000
 /*
  * Include common sunxi configuration where most the settings are
  */
 #include <configs/sunxi-common.h>
 #endif /* __CONFIG_H */

include/configs/sunxi-common.h

Diff comments View file @ da9971d

 /*
  * (C) Copyright 2012-2012 Henrik Nordstrom <henrik@henriknordstrom.net>
  *
  * (C) Copyright 2007-2011
  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  * Tom Cubie <tangliang@allwinnertech.com>
  *
  * Configuration settings for the Allwinner sunxi series of boards.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef _SUNXI_COMMON_CONFIG_H
 #define _SUNXI_COMMON_CONFIG_H
 #include <linux/stringify.h>
 #ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT
 /*
  * The U-Boot workarounds bugs in the outdated buggy sunxi-3.4 kernels at the
  * expense of restricting some features, so the regular machine id values can
  * be used.
  */
 # define CONFIG_MACH_TYPE_COMPAT_REV	0
 #else
 /*
  * A compatibility guard to prevent loading outdated buggy sunxi-3.4 kernels.
  * Only sunxi-3.4 kernels with appropriate fixes applied are able to pass
  * beyond the machine id check.
  */
 # define CONFIG_MACH_TYPE_COMPAT_REV	1
 #endif
 /*
  * High Level Configuration Options
  */
 #define CONFIG_SUNXI		/* sunxi family */
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_THUMB_BUILD	/* Thumbs mode to save space in SPL */
 #endif
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM_SERIAL)
 # define CONFIG_DW_SERIAL
 #endif
 /*
  * Display CPU information
  */
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_SYS_PROMPT	"sunxi# "
 /* Serial & console */
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 /* ns16550 reg in the low bits of cpu reg */
 #define CONFIG_SYS_NS16550_CLK		24000000
 #ifndef CONFIG_DM_SERIAL
 # define CONFIG_SYS_NS16550_REG_SIZE	-4
 # define CONFIG_SYS_NS16550_COM1		SUNXI_UART0_BASE
 # define CONFIG_SYS_NS16550_COM2		SUNXI_UART1_BASE
 # define CONFIG_SYS_NS16550_COM3		SUNXI_UART2_BASE
 # define CONFIG_SYS_NS16550_COM4		SUNXI_UART3_BASE
 # define CONFIG_SYS_NS16550_COM5		SUNXI_R_UART_BASE
 #endif
 /* CPU */
 #define CONFIG_SYS_CACHELINE_SIZE	64
 /*
  * The DRAM Base differs between some models. We cannot use macros for the
  * CONFIG_FOO defines which contain the DRAM base address since they end
  * up unexpanded in include/autoconf.mk .
  *
  * So we have to have this #ifdef #else #endif block for these.
  */
 #ifdef CONFIG_MACH_SUN9I
 #define SDRAM_OFFSET(x) 0x2##x
 #define CONFIG_SYS_SDRAM_BASE		0x20000000
 #define CONFIG_SYS_LOAD_ADDR		0x22000000 /* default load address */
 #define CONFIG_SYS_TEXT_BASE		0x2a000000
 #define CONFIG_PRE_CON_BUF_ADDR		0x2f000000
 #define CONFIG_SYS_SPL_MALLOC_START	0x2ff00000
 #define CONFIG_SPL_BSS_START_ADDR	0x2ff80000
 #else
 #define SDRAM_OFFSET(x) 0x4##x
 #define CONFIG_SYS_SDRAM_BASE		0x40000000
 #define CONFIG_SYS_LOAD_ADDR		0x42000000 /* default load address */
 #define CONFIG_SYS_TEXT_BASE		0x4a000000
 #define CONFIG_PRE_CON_BUF_ADDR		0x4f000000
 #define CONFIG_SYS_SPL_MALLOC_START	0x4ff00000
 #define CONFIG_SPL_BSS_START_ADDR	0x4ff80000
 #endif
 #define CONFIG_SPL_BSS_MAX_SIZE		0x00080000 /* 512 KiB */
 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x00080000 /* 512 KiB */
 #ifdef CONFIG_MACH_SUN9I
 /*
  * The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is
  * slightly bigger. Note that it is possible to map the first 32 KiB of the
  * A1 at 0x00000000 like with older SoCs by writing 0x16aa0001 to the
  * undocumented 0x008000e0 SYS_CTRL register. Where the 16aa is a key and
  * the 1 actually activates the mapping of the first 32 KiB to 0x00000000.
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x10000
 #define CONFIG_SYS_INIT_RAM_SIZE	0x0a000	/* 40 KiB */
 #else
 #define CONFIG_SYS_INIT_RAM_ADDR	0x0
 #define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* 32 KiB */
 #endif
 #define CONFIG_SYS_INIT_SP_OFFSET \
 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR \
 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM_0			CONFIG_SYS_SDRAM_BASE
 #define PHYS_SDRAM_0_SIZE		0x80000000 /* 2 GiB */
 #ifdef CONFIG_AHCI
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
 #define CONFIG_SCSI_AHCI_PLAT
 #define CONFIG_SUNXI_AHCI
 #define CONFIG_SYS_64BIT_LBA
 #define CONFIG_SYS_SCSI_MAX_SCSI_ID	1
 #define CONFIG_SYS_SCSI_MAX_LUN		1
 #define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 					 CONFIG_SYS_SCSI_MAX_LUN)
 #define CONFIG_CMD_SCSI
 #endif
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_INITRD_TAG
 #define CONFIG_SERIAL_TAG
 /* mmc config */
 #if !defined(CONFIG_UART0_PORT_F)
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_CMD_MMC
 #define CONFIG_MMC_SUNXI
 #define CONFIG_MMC_SUNXI_SLOT		0
-#if !defined(CONFIG_SPL_NAND_SUPPORT)
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		0	/* first detected MMC controller */
-#endif /* CONFIG_SPL_NAND_SUPPORT */
 #endif
 /* 4MB of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (4 << 20))
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE	1024	/* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
 #define CONFIG_SYS_GENERIC_BOARD
 /* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 /* standalone support */
 #define CONFIG_STANDALONE_LOAD_ADDR	CONFIG_SYS_LOAD_ADDR
 /* baudrate */
 #define CONFIG_BAUDRATE			115200
 /* The stack sizes are set up in start.S using the settings below */
 #define CONFIG_STACKSIZE		(256 << 10)	/* 256 KiB */
 /* FLASH and environment organization */
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* 512 KiB */
 #define CONFIG_IDENT_STRING		" Allwinner Technology"
 #define CONFIG_ENV_OFFSET		(544 << 10) /* (8 + 24 + 512) KiB */
 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
 #define CONFIG_FAT_WRITE	/* enable write access */
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_BOARD_LOAD_IMAGE
 #define CONFIG_SPL_TEXT_BASE		0x20		/* sram start+header */
 #define CONFIG_SPL_MAX_SIZE		0x5fe0		/* 24KB on sun4i/sun7i */
 #define CONFIG_SPL_LIBDISK_SUPPORT
 #if !defined(CONFIG_UART0_PORT_F)
 #define CONFIG_SPL_MMC_SUPPORT
 #endif
 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	80	/* 40KiB */
 #define CONFIG_SPL_PAD_TO		32768		/* decimal for 'dd' */
 /* end of 32 KiB in sram */
 #define LOW_LEVEL_SRAM_STACK		0x00008000 /* End of sram */
 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
 /* I2C */
 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER
 #define CONFIG_SPL_I2C_SUPPORT
 #endif
 #if defined CONFIG_I2C0_ENABLE || defined CONFIG_I2C1_ENABLE || \
     defined CONFIG_I2C2_ENABLE || defined CONFIG_I2C3_ENABLE || \
     defined CONFIG_I2C4_ENABLE
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MVTWSI
 #define CONFIG_SYS_I2C_SPEED		400000
 #define CONFIG_SYS_I2C_SLAVE		0x7f
 #define CONFIG_CMD_I2C
 #endif
 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
 #define CONFIG_SYS_I2C_SOFT
 #define CONFIG_SYS_I2C_SOFT_SPEED	50000
 #define CONFIG_SYS_I2C_SOFT_SLAVE	0x00
 /* We use pin names in Kconfig and sunxi_name_to_gpio() */
 #define CONFIG_SOFT_I2C_GPIO_SDA	soft_i2c_gpio_sda
 #define CONFIG_SOFT_I2C_GPIO_SCL	soft_i2c_gpio_scl
 #ifndef __ASSEMBLY__
 extern int soft_i2c_gpio_sda;
 extern int soft_i2c_gpio_scl;
 #endif
 #define CONFIG_VIDEO_LCD_I2C_BUS	0 /* The lcd panel soft i2c is bus 0 */
 #define CONFIG_SYS_SPD_BUS_NUM		1 /* And the axp209 i2c bus is bus 1 */
 #else
 #define CONFIG_SYS_SPD_BUS_NUM		0 /* The axp209 i2c bus is bus 0 */
 #define CONFIG_VIDEO_LCD_I2C_BUS	-1 /* NA, but necessary to compile */
 #endif
 /* PMU */
 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || defined CONFIG_AXP221_POWER
 #define CONFIG_SPL_POWER_SUPPORT
 #endif
 #ifndef CONFIG_CONS_INDEX
 #define CONFIG_CONS_INDEX              1       /* UART0 */
 #endif
 #if CONFIG_CONS_INDEX == 1
 #ifdef CONFIG_MACH_SUN9I
 #define OF_STDOUT_PATH		"/soc/serial@07000000:115200"
 #else
 #define OF_STDOUT_PATH		"/soc@01c00000/serial@01c28000:115200"
 #endif
 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
 #define OF_STDOUT_PATH		"/soc@01c00000/serial@01c28400:115200"
 #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
 #define OF_STDOUT_PATH		"/soc@01c00000/serial@01c28800:115200"
 #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
 #define OF_STDOUT_PATH		"/soc@01c00000/serial@01f02800:115200"
 #else
 #error Unsupported console port nr. Please fix stdout-path in sunxi-common.h.
 #endif
 /* GPIO */
 #define CONFIG_SUNXI_GPIO
 #define CONFIG_SPL_GPIO_SUPPORT
 #define CONFIG_CMD_GPIO
 #ifdef CONFIG_VIDEO
 /*
  * The amount of RAM to keep free at the top of RAM when relocating u-boot,
  * to use as framebuffer. This must be a multiple of 4096.
  */
 #define CONFIG_SUNXI_MAX_FB_SIZE (9 << 20)
 /* Do we want to initialize a simple FB? */
 #define CONFIG_VIDEO_DT_SIMPLEFB
 #define CONFIG_VIDEO_SUNXI
 #define CONFIG_CFB_CONSOLE
 #define CONFIG_VIDEO_SW_CURSOR
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_STD_TIMINGS
 #define CONFIG_I2C_EDID
 /* allow both serial and cfb console. */
 #define CONFIG_CONSOLE_MUX
 /* stop x86 thinking in cfbconsole from trying to init a pc keyboard */
 #define CONFIG_VGA_AS_SINGLE_DEVICE
 /* To be able to hook simplefb into dt */
 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
 #define CONFIG_OF_BOARD_SETUP
 #endif
 #endif /* CONFIG_VIDEO */
 /* Ethernet support */
 #ifdef CONFIG_SUNXI_EMAC
 #define CONFIG_PHY_ADDR		1
 #define CONFIG_MII			/* MII PHY management		*/
 #define CONFIG_PHYLIB
 #endif
 #ifdef CONFIG_SUNXI_GMAC
 #define CONFIG_DW_AUTONEG
 #define CONFIG_PHY_GIGE			/* GMAC can use gigabit PHY	*/
 #define CONFIG_PHY_ADDR		1
 #define CONFIG_MII			/* MII PHY management		*/
 #define CONFIG_PHYLIB
 #endif
 #ifdef CONFIG_USB_EHCI
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_USB_OHCI_SUNXI
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
 #endif
 #ifdef CONFIG_USB_MUSB_SUNXI
 #define CONFIG_MUSB_HOST
 #define CONFIG_MUSB_PIO_ONLY
 #endif
 #if defined CONFIG_USB_EHCI || defined CONFIG_USB_MUSB_SUNXI
 #define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #endif
 #ifdef CONFIG_USB_KEYBOARD
 #define CONFIG_CONSOLE_MUX
 #define CONFIG_PREBOOT
 #define CONFIG_SYS_STDIO_DEREGISTER
 #define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
 #endif
 #if !defined CONFIG_ENV_IS_IN_MMC && \
     !defined CONFIG_ENV_IS_IN_NAND && \
     !defined CONFIG_ENV_IS_IN_FAT && \
     !defined CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_IS_NOWHERE
 #endif
-#ifdef CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_NAND
-#define CONFIG_SYS_NAND_SELF_INIT
-#define CONFIG_NAND_SUNXI
-#define CONFIG_CMD_SPL_WRITE_SIZE		0x000400
-#define CONFIG_SYS_NAND_U_BOOT_OFFS		0x008000
-/* \todo Make these parameterisable in kernel config ? */
-#define CONFIG_NAND_SUNXI_PAGE_SIZE		8192
-#define CONFIG_NAND_SUNXI_ECC_STEP		1024
-#define CONFIG_NAND_SUNXI_ECC_STRENGTH		40
-#define CONFIG_NAND_SUNXI_ADDR_CYCLES		5
-#ifndef CONFIG_NAND_SUNXI_GPC_PORTS
-#error "No NAND GPC ports defined, NAND unsupported"
-#endif
-#endif /* CONFIG_SPL_NAND_SUPPORT */
 #define CONFIG_MISC_INIT_R
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 #ifndef CONFIG_SPL_BUILD
 #include <config_distro_defaults.h>
 /* Enable pre-console buffer to get complete log on the VGA console */
 #define CONFIG_PRE_CONSOLE_BUFFER
 #define CONFIG_PRE_CON_BUF_SZ		4096 /* Aprox 2 80*25 screens */
 /*
  * 240M RAM (256M minimum minus space for the framebuffer),
  * 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
  * 1M script, 1M pxe and the ramdisk at the end.
  */
 #define MEM_LAYOUT_ENV_SETTINGS \
 	"bootm_size=0xf000000\0" \
 	"kernel_addr_r=" __stringify(SDRAM_OFFSET(2000000)) "\0" \
 	"fdt_addr_r=" __stringify(SDRAM_OFFSET(3000000)) "\0" \
 	"scriptaddr=" __stringify(SDRAM_OFFSET(3100000)) "\0" \
 	"pxefile_addr_r=" __stringify(SDRAM_OFFSET(3200000)) "\0" \
 	"ramdisk_addr_r=" __stringify(SDRAM_OFFSET(3300000)) "\0"
 #ifdef CONFIG_MMC
 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
 #else
 #define BOOT_TARGET_DEVICES_MMC(func)
 #endif
 #ifdef CONFIG_AHCI
 #define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0)
 #else
 #define BOOT_TARGET_DEVICES_SCSI(func)
 #endif
 #ifdef CONFIG_USB_EHCI
 #define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
 #else
 #define BOOT_TARGET_DEVICES_USB(func)
 #endif
 #define BOOT_TARGET_DEVICES(func) \
 	BOOT_TARGET_DEVICES_MMC(func) \
 	BOOT_TARGET_DEVICES_SCSI(func) \
 	BOOT_TARGET_DEVICES_USB(func) \
 	func(PXE, pxe, na) \
 	func(DHCP, dhcp, na)
 #include <config_distro_bootcmd.h>
 #ifdef CONFIG_USB_KEYBOARD
 #define CONSOLE_STDIN_SETTINGS \
 	"preboot=usb start\0" \
 	"stdin=serial,usbkbd\0"
 #else
 #define CONSOLE_STDIN_SETTINGS \
 	"stdin=serial\0"
 #endif
 #ifdef CONFIG_VIDEO
 #define CONSOLE_STDOUT_SETTINGS \
 	"stdout=serial,vga\0" \
 	"stderr=serial,vga\0"
 #else
 #define CONSOLE_STDOUT_SETTINGS \
 	"stdout=serial\0" \
 	"stderr=serial\0"
 #endif
 #define CONSOLE_ENV_SETTINGS \
 	CONSOLE_STDIN_SETTINGS \
 	CONSOLE_STDOUT_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	CONSOLE_ENV_SETTINGS \
 	MEM_LAYOUT_ENV_SETTINGS \
 	"fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
 	"console=ttyS0,115200\0" \
 	BOOTENV
 #else /* ifndef CONFIG_SPL_BUILD */
 #define CONFIG_EXTRA_ENV_SETTINGS
 #endif
 #endif /* _SUNXI_COMMON_CONFIG_H */