Revert "sunxi/nand: Add support to the SPL for loading u-boot from internal NAND memory"

This reverts commit f76eba38b3eda905ff3bdc18dd1240d3dcbc6e5a. This patch did not have a full and proper copyright/S-o-b chain. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Conflicts: include/configs/sun6i.h include/configs/sun8i.h

Revert "sunxi/nand: Add support to the SPL for loading u-boot from internal NAND memory"
This reverts commit f76eba38b3eda905ff3bdc18dd1240d3dcbc6e5a. This patch did not have a full and proper copyright/S-o-b chain. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Conflicts: include/configs/sun6i.h include/configs/sun8i.h
Ian Campbell · Tom Rini
1 parent ef0f2f5752
Showing 13 changed files with 2 additions and 415 deletions Side-by-side Diff
arch/arm/cpu/armv7/sunxi/board.c
arch/arm/include/asm/arch-sunxi/gpio.h
arch/arm/include/asm/arch-sunxi/nand.h
board/sunxi/Kconfig
board/sunxi/board.c
drivers/mtd/nand/Makefile
drivers/mtd/nand/sunxi_nand_spl.c
include/configs/sun4i.h
include/configs/sun5i.h
include/configs/sun6i.h
include/configs/sun7i.h
include/configs/sun8i.h
include/configs/sunxi-common.h
@@ -119,21 +119,12 @@
 #ifdef CONFIG_SPL_BUILD
 /* The sunxi internal brom will try to loader external bootloader
  * from mmc0, nand flash, mmc2.
- *
- * Unfortunately we can't check how SPL was loaded so assume it's
- * always the first SD/MMC controller, unless it was explicitly
- * stated that SPL is on nand flash.
+ * Unfortunately we can't check how SPL was loaded so assume
+ * it's always the first SD/MMC controller
  */
 u32 spl_boot_device(void)
 {
-#if defined(CONFIG_SPL_NAND_SUPPORT)
 	/*
-	 * This is compile time configuration informing SPL, that it
-	 * was loaded from nand flash.
-	 */
-	return BOOT_DEVICE_NAND;
-#else
-	/*
 	 * When booting from the SD card, the "eGON.BT0" signature is expected
 	 * to be found in memory at the address 0x0004 (see the "mksunxiboot"
 	 * tool, which generates this header).
@@ -153,7 +144,6 @@
 		return BOOT_DEVICE_MMC1;
 	else
 		return BOOT_DEVICE_BOARD;
-#endif
 }
  
 /* No confirmation data available in SPL yet. Hardcode bootmode */
@@ -157,8 +157,6 @@
 #define SUN5I_GPB_UART0		2
 #define SUN8I_GPB_UART2		2
  
-#define SUNXI_GPC_NAND		2
-
 #define SUNXI_GPC_SDC2		3
 #define SUN6I_GPC_SDC3		4
  
-/*
- * (C) Copyright 2015 Roy Spliet <rspliet@ultimaker.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _SUNXI_NAND_H
-#define _SUNXI_NAND_H
-
-#include <linux/types.h>
-
-struct sunxi_nand
-{
-	u32 ctl;		/* 0x000 Configure and control */
-	u32 st;			/* 0x004 Status information */
-	u32 intr;		/* 0x008 Interrupt control */
-	u32 timing_ctl;		/* 0x00C Timing control */
-	u32 timing_cfg;		/* 0x010 Timing configure */
-	u32 addr_low;		/* 0x014 Low word address */
-	u32 addr_high;		/* 0x018 High word address */
-	u32 block_num;		/* 0x01C Data block number */
-	u32 data_cnt;		/* 0x020 Data counter for transfer */
-	u32 cmd;		/* 0x024 NDFC commands */
-	u32 rcmd_set;		/* 0x028 Read command set for vendor NAND mem */
-	u32 wcmd_set;		/* 0x02C Write command set */
-	u32 io_data;		/* 0x030 IO data */
-	u32 ecc_ctl;		/* 0x034 ECC configure and control */
-	u32 ecc_st;		/* 0x038 ECC status and operation info */
-	u32 efr;		/* 0x03C Enhanced feature */
-	u32 err_cnt0;		/* 0x040 Corrected error bit counter 0 */
-	u32 err_cnt1;		/* 0x044 Corrected error bit counter 1 */
-	u32 user_data[16];	/* 0x050[16] User data field */
-	u32 efnand_st;		/* 0x090 EFNAND status */
-	u32 res0[3];
-	u32 spare_area;		/* 0x0A0 Spare area configure */
-	u32 pat_id;		/* 0x0A4 Pattern ID register */
-	u32 rdata_sta_ctl;	/* 0x0A8 Read data status control */
-	u32 rdata_sta_0;	/* 0x0AC Read data status 0 */
-	u32 rdata_sta_1;	/* 0x0B0 Read data status 1 */
-	u32 res1[3];
-	u32 mdma_addr;		/* 0x0C0 MBUS DMA Address */
-	u32 mdma_cnt;		/* 0x0C4 MBUS DMA data counter */
-};
-
-#define SUNXI_NAND_CTL_EN			(1 << 0)
-#define SUNXI_NAND_CTL_RST			(1 << 1)
-#define SUNXI_NAND_CTL_PAGE_SIZE(a)		((fls(a) - 11) << 8)
-#define SUNXI_NAND_CTL_RAM_METHOD_DMA		(1 << 14)
-
-#define SUNXI_NAND_ST_CMD_INT			(1 << 1)
-#define SUNXI_NAND_ST_DMA_INT			(1 << 2)
-#define SUNXI_NAND_ST_FIFO_FULL			(1 << 3)
-
-#define SUNXI_NAND_CMD_ADDR_CYCLES(a)		((a - 1) << 16);
-#define SUNXI_NAND_CMD_SEND_CMD1		(1 << 22)
-#define SUNXI_NAND_CMD_WAIT_FLAG		(1 << 23)
-#define SUNXI_NAND_CMD_ORDER_INTERLEAVE		0
-#define SUNXI_NAND_CMD_ORDER_SEQ		(1 << 25)
-
-#define SUNXI_NAND_ECC_CTL_ECC_EN		(1 << 0)
-#define SUNXI_NAND_ECC_CTL_PIPELINE		(1 << 3)
-#define SUNXI_NAND_ECC_CTL_BS_512B		(1 << 5)
-#define SUNXI_NAND_ECC_CTL_RND_EN		(1 << 9)
-#define SUNXI_NAND_ECC_CTL_MODE(a)		((a) << 12)
-#define SUNXI_NAND_ECC_CTL_RND_SEED(a)		((a) << 16)
-
-#endif /* _SUNXI_NAND_H */
@@ -280,18 +280,6 @@
 	slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
 	support for this.
  
-config SPL_NAND_SUPPORT
-	bool "SPL/NAND mode support"
-	depends on SPL
-	default n
-	---help---
-	  This enables support for booting from NAND internal
-	  memory. U-Boot SPL doesn't detect where is it load from,
-	  therefore this option is needed to properly load image from
-	  flash. Option also disables MMC functionality on U-Boot due to
-	  initialization errors encountered, when both controllers are
-	  enabled.
-
 config USB0_VBUS_PIN
 	string "Vbus enable pin for usb0 (otg)"
 	default ""
@@ -22,9 +22,6 @@
 #ifdef CONFIG_AXP221_POWER
 #include <axp221.h>
 #endif
-#ifdef CONFIG_NAND_SUNXI
-#include <nand.h>
-#endif
 #include <asm/arch/clock.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/display.h>
@@ -315,21 +312,6 @@
 #endif
  
 	return 0;
-}
-#endif
-
-#ifdef CONFIG_NAND
-void board_nand_init(void)
-{
-	unsigned int pin;
-	static u8 ports[] = CONFIG_NAND_SUNXI_GPC_PORTS;
-
-	/* Configure AHB muxes to connect output pins with NAND controller */
-	for (pin = 0; pin < 16; pin++)
-		sunxi_gpio_set_cfgpin(SUNXI_GPC(pin), SUNXI_GPC_NAND);
-
-	for (pin = 0; pin < ARRAY_SIZE(ports); pin++)
-		sunxi_gpio_set_cfgpin(SUNXI_GPC(ports[pin]), SUNXI_GPC_NAND);
 }
 #endif
  
@@ -73,7 +73,6 @@
 obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o
 obj-$(CONFIG_NAND_MXC) += mxc_nand_spl.o
 obj-$(CONFIG_NAND_MXS) += mxs_nand_spl.o mxs_nand.o
-obj-$(CONFIG_NAND_SUNXI) += sunxi_nand_spl.o
  
 endif # drivers
-/*
- * Copyright (c) 2014, Antmicro Ltd <www.antmicro.com>
- * Copyright (c) 2015, Turtle Solutions <www.turtle-solutions.eu>
- * Copyright (c) 2015, Roy Spliet <rspliet@ultimaker.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * \todo Detect chip parameters (page size, ECC mode, randomisation...)
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/dma.h>
-#include <asm/arch/nand.h>
-
-void
-nand_init(void)
-{
-	struct sunxi_ccm_reg * const ccm =
-			(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-	struct sunxi_nand * const nand = (struct sunxi_nand *)SUNXI_NFC_BASE;
-	u32 val;
-
-	board_nand_init();
-
-	/* "un-gate" NAND clock and clock source
-	 * This assumes that the clock was already correctly configured by
-	 * BootROM */
-	setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_NAND0));
-#ifdef CONFIG_MACH_SUN9I
-	setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
-#else
-	setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
-#endif
-	setbits_le32(&ccm->nand0_clk_cfg, 0x80000000);
-
-	val = readl(&nand->ctl);
-	val |= SUNXI_NAND_CTL_RST;
-	writel(val, &nand->ctl);
-
-	/* Wait until reset pin is deasserted */
-	do {
-		val = readl(&nand->ctl);
-		if (!(val & SUNXI_NAND_CTL_RST))
-			break;
-	} while (1);
-
-	/** \todo Chip select, currently kind of static */
-	val = readl(&nand->ctl);
-	val &= 0xf0fff0f2;
-	val |= SUNXI_NAND_CTL_EN;
-	val |= SUNXI_NAND_CTL_PAGE_SIZE(CONFIG_NAND_SUNXI_PAGE_SIZE);
-	writel(val, &nand->ctl);
-
-	writel(0x100, &nand->timing_ctl);
-	writel(0x7ff, &nand->timing_cfg);
-
-	/* reset CMD  */
-	val = SUNXI_NAND_CMD_SEND_CMD1 | SUNXI_NAND_CMD_WAIT_FLAG |
-			NAND_CMD_RESET;
-	writel(val, &nand->cmd);
-	do {
-		val = readl(&nand->st);
-		if (val & (1<<1))
-			break;
-		udelay(1000);
-	} while (1);
-
-	printf("Nand initialised\n");
-}
-
-int
-nand_wait_timeout(u32 *reg, u32 mask, u32 val)
-{
-	unsigned long tmo = timer_get_us() + 1000000; /* 1s */
-
-	while ((readl(reg) & mask) != val) {
-		if (timer_get_us() > tmo)
-			return -ETIMEDOUT;
-	}
-
-	return 0;
-}
-
-/* random seed */
-static const uint16_t random_seed[128] = {
-	0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
-	0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
-	0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
-	0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
-	0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
-	0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
-	0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
-	0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
-	0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
-	0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
-	0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
-	0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
-	0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
-	0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
-	0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
-	0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
-};
-
-uint32_t ecc_errors = 0;
-
-static void
-nand_config_ecc(struct sunxi_nand *nand, uint32_t page, int syndrome)
-{
-	static u8 strength[] = {16, 24, 28, 32, 40, 48, 56, 60, 64};
-	int i;
-	uint32_t ecc_mode;
-	u32 ecc;
-	u16 seed = 0;
-
-	for (i = 0; i < ARRAY_SIZE(strength); i++) {
-		if (CONFIG_NAND_SUNXI_ECC_STRENGTH == strength[i]) {
-			ecc_mode = i;
-			break;
-		}
-	}
-
-	if (i == ARRAY_SIZE(strength)) {
-		printf("ECC strength unsupported\n");
-		return;
-	}
-
-	ecc = 	SUNXI_NAND_ECC_CTL_ECC_EN |
-		SUNXI_NAND_ECC_CTL_PIPELINE |
-		SUNXI_NAND_ECC_CTL_RND_EN |
-		SUNXI_NAND_ECC_CTL_MODE(ecc_mode);
-
-	if (CONFIG_NAND_SUNXI_ECC_STEP == 512)
-		ecc |= SUNXI_NAND_ECC_CTL_BS_512B;
-
-	if (syndrome)
-		seed = 0x4A80;
-	else
-		seed = random_seed[page % ARRAY_SIZE(random_seed)];
-
-	ecc |= SUNXI_NAND_ECC_CTL_RND_SEED(seed);
-
-	writel(ecc, &nand->ecc_ctl);
-}
-
-/* read CONFIG_NAND_SUNXI_ECC_STEP bytes from real_addr to temp_buf */
-void
-nand_read_block(struct sunxi_nand *nand, phys_addr_t src, dma_addr_t dst,
-		int syndrome)
-{
-	struct sunxi_dma * const dma = (struct sunxi_dma *)SUNXI_DMA_BASE;
-	struct sunxi_dma_cfg * const dma_cfg = &dma->ddma[0];
-
-	uint32_t shift;
-	uint32_t page;
-	uint32_t addr;
-	uint32_t oob_offset;
-	uint32_t ecc_bytes;
-	u32 val;
-	u32 cmd;
-
-	page = src / CONFIG_NAND_SUNXI_PAGE_SIZE;
-	if (page > 0xFFFF) {
-		/* TODO: currently this is not supported */
-		printf("Reading from address >= %08X is not allowed.\n",
-		       0xFFFF * CONFIG_NAND_SUNXI_PAGE_SIZE);
-		return;
-	}
-
-	shift = src % CONFIG_NAND_SUNXI_PAGE_SIZE;
-	writel(0, &nand->ecc_st);
-
-	/* ECC_CTL, randomization */
-	ecc_bytes = CONFIG_NAND_SUNXI_ECC_STRENGTH *
-			fls(CONFIG_NAND_SUNXI_ECC_STEP * 8);
-	ecc_bytes = DIV_ROUND_UP(ecc_bytes, 8);
-	ecc_bytes += (ecc_bytes & 1); /* Align to 2-bytes */
-	ecc_bytes += 4;
-
-	nand_config_ecc(nand, page, syndrome);
-	if (syndrome) {
-		/* shift every 1kB in syndrome */
-		shift += (shift / CONFIG_NAND_SUNXI_ECC_STEP) * ecc_bytes;
-		oob_offset = CONFIG_NAND_SUNXI_ECC_STEP + shift;
-	} else {
-		oob_offset = CONFIG_NAND_SUNXI_PAGE_SIZE  +
-			(shift / CONFIG_NAND_SUNXI_ECC_STEP) * ecc_bytes;
-	}
-
-	addr = (page << 16) | shift;
-
-	/* DMA */
-	val = readl(&nand->ctl);
-	writel(val | SUNXI_NAND_CTL_RAM_METHOD_DMA, &nand->ctl);
-
-	writel(oob_offset, &nand->spare_area);
-
-	/* DMAC
-	 * \todo Separate this into a tidy driver */
-	writel(0x0, &dma->irq_en); /* clear dma interrupts */
-	writel((uint32_t) &nand->io_data , &dma_cfg->src_addr);
-	writel(dst            , &dma_cfg->dst_addr);
-	writel(0x00007F0F     , &dma_cfg->ddma_para);
-	writel(CONFIG_NAND_SUNXI_ECC_STEP, &dma_cfg->bc);
-
-	val = 	SUNXI_DMA_CTL_SRC_DRQ(DDMA_SRC_DRQ_NAND) |
-		SUNXI_DMA_CTL_MODE_IO |
-		SUNXI_DMA_CTL_SRC_DATA_WIDTH_32 |
-		SUNXI_DMA_CTL_DST_DRQ(DDMA_DST_DRQ_SDRAM) |
-		SUNXI_DMA_CTL_DST_DATA_WIDTH_32 |
-		SUNXI_DMA_CTL_TRIGGER;
-	writel(val, &dma_cfg->ctl);
-
-	writel(0x00E00530, &nand->rcmd_set);
-	nand_wait_timeout(&nand->st, SUNXI_NAND_ST_FIFO_FULL, 0);
-
-	writel(1   , &nand->block_num);
-	writel(addr, &nand->addr_low);
-	writel(0   , &nand->addr_high);
-
-	/* CMD (PAGE READ) */
-	cmd = 0x85E80000;
-	cmd |= SUNXI_NAND_CMD_ADDR_CYCLES(CONFIG_NAND_SUNXI_ADDR_CYCLES);
-	cmd |= (syndrome ? SUNXI_NAND_CMD_ORDER_SEQ :
-			SUNXI_NAND_CMD_ORDER_INTERLEAVE);
-	writel(cmd, &nand->cmd);
-
-	if(nand_wait_timeout(&nand->st, SUNXI_NAND_ST_DMA_INT,
-			SUNXI_NAND_ST_DMA_INT)) {
-		printf("NAND timeout reading data\n");
-		return;
-	}
-
-	if(nand_wait_timeout(&dma_cfg->ctl, SUNXI_DMA_CTL_TRIGGER, 0)) {
-		printf("NAND timeout reading data\n");
-		return;
-	}
-
-	if (readl(&nand->ecc_st))
-		ecc_errors++;
-}
-
-int
-nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
-{
-	struct sunxi_nand * const nand = (struct sunxi_nand *)SUNXI_NFC_BASE;
-	dma_addr_t dst_block;
-	dma_addr_t dst_end;
-	phys_addr_t addr = offs;
-
-	dst_end = ((dma_addr_t) dest) + size;
-
-	memset((void *)dest, 0x0, size);
-	ecc_errors = 0;
-	for (dst_block = (dma_addr_t) dest; dst_block < dst_end;
-			dst_block += CONFIG_NAND_SUNXI_ECC_STEP,
-			addr += CONFIG_NAND_SUNXI_ECC_STEP) {
-		/* syndrome read first 4MiB to match Allwinner BootROM */
-		nand_read_block(nand, addr, dst_block, addr < 0x400000);
-	}
-
-	if (ecc_errors)
-		printf("Error: %d ECC failures detected\n", ecc_errors);
-	return ecc_errors == 0;
-}
-
-void
-nand_deselect(void)
-{}
@@ -18,7 +18,6 @@
 #endif
  
 #define CONFIG_SUNXI_USB_PHYS	3
-#define CONFIG_NAND_SUNXI_GPC_PORTS	{16, 17, 18, 19, 20, 21, 22, 24}
  
 /*
  * Include common sunxi configuration where most the settings are
@@ -19,9 +19,6 @@
  
 #define CONFIG_SUNXI_USB_PHYS	2
  
-/* \todo A13 only defines port 19, whereas A10s requires each of these */
-#define CONFIG_NAND_SUNXI_GPC_PORTS	{16, 17, 18, 19}
-
 /*
  * Include common sunxi configuration where most the settings are
  */
@@ -27,8 +27,6 @@
 #define CONFIG_ARMV7_SECURE_BASE	SUNXI_SRAM_B_BASE
 #define CONFIG_TIMER_CLK_FREQ		24000000
  
-#define CONFIG_NAND_SUNXI_GPC_PORTS	{24, 25, 26}
-
 /*
  * Include common sunxi configuration where most the settings are
  */
@@ -24,8 +24,6 @@
 #define CONFIG_ARMV7_SECURE_BASE	SUNXI_SRAM_B_BASE
 #define CONFIG_TIMER_CLK_FREQ		24000000
  
-#define CONFIG_NAND_SUNXI_GPC_PORTS	{16, 17, 18, 19, 20, 21, 22, 24}
-
 /*
  * Include common sunxi configuration where most the settings are
  */
@@ -23,10 +23,8 @@
 #define CONFIG_ARMV7_PSCI		1
 #if defined(CONFIG_MACH_SUN8I_A23)
 #define CONFIG_ARMV7_PSCI_NR_CPUS	2
-#define CONFIG_NAND_SUNXI_GPC_PORTS	{16, 17, 18}
 #elif defined(CONFIG_MACH_SUN8I_A33)
 #define CONFIG_ARMV7_PSCI_NR_CPUS	4
-#define CONFIG_NAND_SUNXI_GPC_PORTS	{16}
 #else
 #error Unsupported sun8i variant
 #endif
@@ -146,10 +146,8 @@
 #define CONFIG_CMD_MMC
 #define CONFIG_MMC_SUNXI
 #define CONFIG_MMC_SUNXI_SLOT		0
-#if !defined(CONFIG_SPL_NAND_SUPPORT)
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		0	/* first detected MMC controller */
-#endif /* CONFIG_SPL_NAND_SUPPORT */
 #endif
  
 /* 4MB of malloc() pool */
@@ -350,24 +348,6 @@
     !defined CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_IS_NOWHERE
 #endif
-
-#ifdef CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_NAND
-#define CONFIG_SYS_NAND_SELF_INIT
-#define CONFIG_NAND_SUNXI
-#define CONFIG_CMD_SPL_WRITE_SIZE		0x000400
-#define CONFIG_SYS_NAND_U_BOOT_OFFS		0x008000
-
-/* \todo Make these parameterisable in kernel config ? */
-#define CONFIG_NAND_SUNXI_PAGE_SIZE		8192
-#define CONFIG_NAND_SUNXI_ECC_STEP		1024
-#define CONFIG_NAND_SUNXI_ECC_STRENGTH		40
-#define CONFIG_NAND_SUNXI_ADDR_CYCLES		5
-
-#ifndef CONFIG_NAND_SUNXI_GPC_PORTS
-#error "No NAND GPC ports defined, NAND unsupported"
-#endif
-#endif /* CONFIG_SPL_NAND_SUPPORT */
  
 #define CONFIG_MISC_INIT_R
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
...	...	@@ -119,21 +119,12 @@
119	119	#ifdef CONFIG_SPL_BUILD
120	120	/* The sunxi internal brom will try to loader external bootloader
121	121	* from mmc0, nand flash, mmc2.
122		- *
123		- * Unfortunately we can't check how SPL was loaded so assume it's
124		- * always the first SD/MMC controller, unless it was explicitly
125		- * stated that SPL is on nand flash.
	122	+ * Unfortunately we can't check how SPL was loaded so assume
	123	+ * it's always the first SD/MMC controller
126	124	*/
127	125	u32 spl_boot_device(void)
128	126	{
129		-#if defined(CONFIG_SPL_NAND_SUPPORT)
130	127	/*
131		- * This is compile time configuration informing SPL, that it
132		- * was loaded from nand flash.
133		- */
134		- return BOOT_DEVICE_NAND;
135		-#else
136		- /*
137	128	* When booting from the SD card, the "eGON.BT0" signature is expected
138	129	* to be found in memory at the address 0x0004 (see the "mksunxiboot"
139	130	* tool, which generates this header).
...	...	@@ -153,7 +144,6 @@
153	144	return BOOT_DEVICE_MMC1;
154	145	else
155	146	return BOOT_DEVICE_BOARD;
156		-#endif
157	147	}
158	148
159	149	/* No confirmation data available in SPL yet. Hardcode bootmode */
...	...	@@ -157,8 +157,6 @@
157	157	#define SUN5I_GPB_UART0 2
158	158	#define SUN8I_GPB_UART2 2
159	159
160		-#define SUNXI_GPC_NAND 2
161		-
162	160	#define SUNXI_GPC_SDC2 3
163	161	#define SUN6I_GPC_SDC3 4
164	162
1		-/*
2		- * (C) Copyright 2015 Roy Spliet <rspliet@ultimaker.com>
3		- *
4		- * SPDX-License-Identifier: GPL-2.0+
5		- */
6		-
7		-#ifndef _SUNXI_NAND_H
8		-#define _SUNXI_NAND_H
9		-
10		-#include <linux/types.h>
11		-
12		-struct sunxi_nand
13		-{
14		- u32 ctl; /* 0x000 Configure and control */
15		- u32 st; /* 0x004 Status information */
16		- u32 intr; /* 0x008 Interrupt control */
17		- u32 timing_ctl; /* 0x00C Timing control */
18		- u32 timing_cfg; /* 0x010 Timing configure */
19		- u32 addr_low; /* 0x014 Low word address */
20		- u32 addr_high; /* 0x018 High word address */
21		- u32 block_num; /* 0x01C Data block number */
22		- u32 data_cnt; /* 0x020 Data counter for transfer */
23		- u32 cmd; /* 0x024 NDFC commands */
24		- u32 rcmd_set; /* 0x028 Read command set for vendor NAND mem */
25		- u32 wcmd_set; /* 0x02C Write command set */
26		- u32 io_data; /* 0x030 IO data */
27		- u32 ecc_ctl; /* 0x034 ECC configure and control */
28		- u32 ecc_st; /* 0x038 ECC status and operation info */
29		- u32 efr; /* 0x03C Enhanced feature */
30		- u32 err_cnt0; /* 0x040 Corrected error bit counter 0 */
31		- u32 err_cnt1; /* 0x044 Corrected error bit counter 1 */
32		- u32 user_data[16]; /* 0x050[16] User data field */
33		- u32 efnand_st; /* 0x090 EFNAND status */
34		- u32 res0[3];
35		- u32 spare_area; /* 0x0A0 Spare area configure */
36		- u32 pat_id; /* 0x0A4 Pattern ID register */
37		- u32 rdata_sta_ctl; /* 0x0A8 Read data status control */
38		- u32 rdata_sta_0; /* 0x0AC Read data status 0 */
39		- u32 rdata_sta_1; /* 0x0B0 Read data status 1 */
40		- u32 res1[3];
41		- u32 mdma_addr; /* 0x0C0 MBUS DMA Address */
42		- u32 mdma_cnt; /* 0x0C4 MBUS DMA data counter */
43		-};
44		-
45		-#define SUNXI_NAND_CTL_EN (1 << 0)
46		-#define SUNXI_NAND_CTL_RST (1 << 1)
47		-#define SUNXI_NAND_CTL_PAGE_SIZE(a) ((fls(a) - 11) << 8)
48		-#define SUNXI_NAND_CTL_RAM_METHOD_DMA (1 << 14)
49		-
50		-#define SUNXI_NAND_ST_CMD_INT (1 << 1)
51		-#define SUNXI_NAND_ST_DMA_INT (1 << 2)
52		-#define SUNXI_NAND_ST_FIFO_FULL (1 << 3)
53		-
54		-#define SUNXI_NAND_CMD_ADDR_CYCLES(a) ((a - 1) << 16);
55		-#define SUNXI_NAND_CMD_SEND_CMD1 (1 << 22)
56		-#define SUNXI_NAND_CMD_WAIT_FLAG (1 << 23)
57		-#define SUNXI_NAND_CMD_ORDER_INTERLEAVE 0
58		-#define SUNXI_NAND_CMD_ORDER_SEQ (1 << 25)
59		-
60		-#define SUNXI_NAND_ECC_CTL_ECC_EN (1 << 0)
61		-#define SUNXI_NAND_ECC_CTL_PIPELINE (1 << 3)
62		-#define SUNXI_NAND_ECC_CTL_BS_512B (1 << 5)
63		-#define SUNXI_NAND_ECC_CTL_RND_EN (1 << 9)
64		-#define SUNXI_NAND_ECC_CTL_MODE(a) ((a) << 12)
65		-#define SUNXI_NAND_ECC_CTL_RND_SEED(a) ((a) << 16)
66		-
67		-#endif /* _SUNXI_NAND_H */
...	...	@@ -280,18 +280,6 @@
280	280	slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
281	281	support for this.
282	282
283		-config SPL_NAND_SUPPORT
284		- bool "SPL/NAND mode support"
285		- depends on SPL
286		- default n
287		- ---help---
288		- This enables support for booting from NAND internal
289		- memory. U-Boot SPL doesn't detect where is it load from,
290		- therefore this option is needed to properly load image from
291		- flash. Option also disables MMC functionality on U-Boot due to
292		- initialization errors encountered, when both controllers are
293		- enabled.
294		-
295	283	config USB0_VBUS_PIN
296	284	string "Vbus enable pin for usb0 (otg)"
297	285	default ""
...	...	@@ -22,9 +22,6 @@
22	22	#ifdef CONFIG_AXP221_POWER
23	23	#include <axp221.h>
24	24	#endif
25		-#ifdef CONFIG_NAND_SUNXI
26		-#include <nand.h>
27		-#endif
28	25	#include <asm/arch/clock.h>
29	26	#include <asm/arch/cpu.h>
30	27	#include <asm/arch/display.h>
...	...	@@ -315,21 +312,6 @@
315	312	#endif
316	313
317	314	return 0;
318		-}
319		-#endif
320		-
321		-#ifdef CONFIG_NAND
322		-void board_nand_init(void)
323		-{
324		- unsigned int pin;
325		- static u8 ports[] = CONFIG_NAND_SUNXI_GPC_PORTS;
326		-
327		- /* Configure AHB muxes to connect output pins with NAND controller */
328		- for (pin = 0; pin < 16; pin++)
329		- sunxi_gpio_set_cfgpin(SUNXI_GPC(pin), SUNXI_GPC_NAND);
330		-
331		- for (pin = 0; pin < ARRAY_SIZE(ports); pin++)
332		- sunxi_gpio_set_cfgpin(SUNXI_GPC(ports[pin]), SUNXI_GPC_NAND);
333	315	}
334	316	#endif
335	317
...	...	@@ -73,7 +73,6 @@
73	73	obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o
74	74	obj-$(CONFIG_NAND_MXC) += mxc_nand_spl.o
75	75	obj-$(CONFIG_NAND_MXS) += mxs_nand_spl.o mxs_nand.o
76		-obj-$(CONFIG_NAND_SUNXI) += sunxi_nand_spl.o
77	76
78	77	endif # drivers
1		-/*
2		- * Copyright (c) 2014, Antmicro Ltd <www.antmicro.com>
3		- * Copyright (c) 2015, Turtle Solutions <www.turtle-solutions.eu>
4		- * Copyright (c) 2015, Roy Spliet <rspliet@ultimaker.com>
5		- *
6		- * SPDX-License-Identifier: GPL-2.0+
7		- *
8		- * \todo Detect chip parameters (page size, ECC mode, randomisation...)
9		- */
10		-
11		-#include <common.h>
12		-#include <config.h>
13		-#include <asm/io.h>
14		-#include <nand.h>
15		-#include <asm/arch/cpu.h>
16		-#include <asm/arch/clock.h>
17		-#include <asm/arch/dma.h>
18		-#include <asm/arch/nand.h>
19		-
20		-void
21		-nand_init(void)
22		-{
23		- struct sunxi_ccm_reg * const ccm =
24		- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
25		- struct sunxi_nand * const nand = (struct sunxi_nand *)SUNXI_NFC_BASE;
26		- u32 val;
27		-
28		- board_nand_init();
29		-
30		- /* "un-gate" NAND clock and clock source
31		- * This assumes that the clock was already correctly configured by
32		- * BootROM */
33		- setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_NAND0));
34		-#ifdef CONFIG_MACH_SUN9I
35		- setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
36		-#else
37		- setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
38		-#endif
39		- setbits_le32(&ccm->nand0_clk_cfg, 0x80000000);
40		-
41		- val = readl(&nand->ctl);
42		- val \|= SUNXI_NAND_CTL_RST;
43		- writel(val, &nand->ctl);
44		-
45		- /* Wait until reset pin is deasserted */
46		- do {
47		- val = readl(&nand->ctl);
48		- if (!(val & SUNXI_NAND_CTL_RST))
49		- break;
50		- } while (1);
51		-
52		- /** \todo Chip select, currently kind of static */
53		- val = readl(&nand->ctl);
54		- val &= 0xf0fff0f2;
55		- val \|= SUNXI_NAND_CTL_EN;
56		- val \|= SUNXI_NAND_CTL_PAGE_SIZE(CONFIG_NAND_SUNXI_PAGE_SIZE);
57		- writel(val, &nand->ctl);
58		-
59		- writel(0x100, &nand->timing_ctl);
60		- writel(0x7ff, &nand->timing_cfg);
61		-
62		- /* reset CMD */
63		- val = SUNXI_NAND_CMD_SEND_CMD1 \| SUNXI_NAND_CMD_WAIT_FLAG \|
64		- NAND_CMD_RESET;
65		- writel(val, &nand->cmd);
66		- do {
67		- val = readl(&nand->st);
68		- if (val & (1<<1))
69		- break;
70		- udelay(1000);
71		- } while (1);
72		-
73		- printf("Nand initialised\n");
74		-}
75		-
76		-int
77		-nand_wait_timeout(u32 *reg, u32 mask, u32 val)
78		-{
79		- unsigned long tmo = timer_get_us() + 1000000; /* 1s */
80		-
81		- while ((readl(reg) & mask) != val) {
82		- if (timer_get_us() > tmo)
83		- return -ETIMEDOUT;
84		- }
85		-
86		- return 0;
87		-}
88		-
89		-/* random seed */
90		-static const uint16_t random_seed[128] = {
91		- 0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
92		- 0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
93		- 0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
94		- 0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
95		- 0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
96		- 0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
97		- 0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
98		- 0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
99		- 0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
100		- 0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
101		- 0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
102		- 0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
103		- 0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
104		- 0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
105		- 0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
106		- 0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
107		-};
108		-
109		-uint32_t ecc_errors = 0;
110		-
111		-static void
112		-nand_config_ecc(struct sunxi_nand *nand, uint32_t page, int syndrome)
113		-{
114		- static u8 strength[] = {16, 24, 28, 32, 40, 48, 56, 60, 64};
115		- int i;
116		- uint32_t ecc_mode;
117		- u32 ecc;
118		- u16 seed = 0;
119		-
120		- for (i = 0; i < ARRAY_SIZE(strength); i++) {
121		- if (CONFIG_NAND_SUNXI_ECC_STRENGTH == strength[i]) {
122		- ecc_mode = i;
123		- break;
124		- }
125		- }
126		-
127		- if (i == ARRAY_SIZE(strength)) {
128		- printf("ECC strength unsupported\n");
129		- return;
130		- }
131		-
132		- ecc = SUNXI_NAND_ECC_CTL_ECC_EN \|
133		- SUNXI_NAND_ECC_CTL_PIPELINE \|
134		- SUNXI_NAND_ECC_CTL_RND_EN \|
135		- SUNXI_NAND_ECC_CTL_MODE(ecc_mode);
136		-
137		- if (CONFIG_NAND_SUNXI_ECC_STEP == 512)
138		- ecc \|= SUNXI_NAND_ECC_CTL_BS_512B;
139		-
140		- if (syndrome)
141		- seed = 0x4A80;
142		- else
143		- seed = random_seed[page % ARRAY_SIZE(random_seed)];
144		-
145		- ecc \|= SUNXI_NAND_ECC_CTL_RND_SEED(seed);
146		-
147		- writel(ecc, &nand->ecc_ctl);
148		-}
149		-
150		-/* read CONFIG_NAND_SUNXI_ECC_STEP bytes from real_addr to temp_buf */
151		-void
152		-nand_read_block(struct sunxi_nand *nand, phys_addr_t src, dma_addr_t dst,
153		- int syndrome)
154		-{
155		- struct sunxi_dma * const dma = (struct sunxi_dma *)SUNXI_DMA_BASE;
156		- struct sunxi_dma_cfg * const dma_cfg = &dma->ddma[0];
157		-
158		- uint32_t shift;
159		- uint32_t page;
160		- uint32_t addr;
161		- uint32_t oob_offset;
162		- uint32_t ecc_bytes;
163		- u32 val;
164		- u32 cmd;
165		-
166		- page = src / CONFIG_NAND_SUNXI_PAGE_SIZE;
167		- if (page > 0xFFFF) {
168		- /* TODO: currently this is not supported */
169		- printf("Reading from address >= %08X is not allowed.\n",
170		- 0xFFFF * CONFIG_NAND_SUNXI_PAGE_SIZE);
171		- return;
172		- }
173		-
174		- shift = src % CONFIG_NAND_SUNXI_PAGE_SIZE;
175		- writel(0, &nand->ecc_st);
176		-
177		- /* ECC_CTL, randomization */
178		- ecc_bytes = CONFIG_NAND_SUNXI_ECC_STRENGTH *
179		- fls(CONFIG_NAND_SUNXI_ECC_STEP * 8);
180		- ecc_bytes = DIV_ROUND_UP(ecc_bytes, 8);
181		- ecc_bytes += (ecc_bytes & 1); /* Align to 2-bytes */
182		- ecc_bytes += 4;
183		-
184		- nand_config_ecc(nand, page, syndrome);
185		- if (syndrome) {
186		- /* shift every 1kB in syndrome */
187		- shift += (shift / CONFIG_NAND_SUNXI_ECC_STEP) * ecc_bytes;
188		- oob_offset = CONFIG_NAND_SUNXI_ECC_STEP + shift;
189		- } else {
190		- oob_offset = CONFIG_NAND_SUNXI_PAGE_SIZE +
191		- (shift / CONFIG_NAND_SUNXI_ECC_STEP) * ecc_bytes;
192		- }
193		-
194		- addr = (page << 16) \| shift;
195		-
196		- /* DMA */
197		- val = readl(&nand->ctl);
198		- writel(val \| SUNXI_NAND_CTL_RAM_METHOD_DMA, &nand->ctl);
199		-
200		- writel(oob_offset, &nand->spare_area);
201		-
202		- /* DMAC
203		- * \todo Separate this into a tidy driver */
204		- writel(0x0, &dma->irq_en); /* clear dma interrupts */
205		- writel((uint32_t) &nand->io_data , &dma_cfg->src_addr);
206		- writel(dst , &dma_cfg->dst_addr);
207		- writel(0x00007F0F , &dma_cfg->ddma_para);
208		- writel(CONFIG_NAND_SUNXI_ECC_STEP, &dma_cfg->bc);
209		-
210		- val = SUNXI_DMA_CTL_SRC_DRQ(DDMA_SRC_DRQ_NAND) \|
211		- SUNXI_DMA_CTL_MODE_IO \|
212		- SUNXI_DMA_CTL_SRC_DATA_WIDTH_32 \|
213		- SUNXI_DMA_CTL_DST_DRQ(DDMA_DST_DRQ_SDRAM) \|
214		- SUNXI_DMA_CTL_DST_DATA_WIDTH_32 \|
215		- SUNXI_DMA_CTL_TRIGGER;
216		- writel(val, &dma_cfg->ctl);
217		-
218		- writel(0x00E00530, &nand->rcmd_set);
219		- nand_wait_timeout(&nand->st, SUNXI_NAND_ST_FIFO_FULL, 0);
220		-
221		- writel(1 , &nand->block_num);
222		- writel(addr, &nand->addr_low);
223		- writel(0 , &nand->addr_high);
224		-
225		- /* CMD (PAGE READ) */
226		- cmd = 0x85E80000;
227		- cmd \|= SUNXI_NAND_CMD_ADDR_CYCLES(CONFIG_NAND_SUNXI_ADDR_CYCLES);
228		- cmd \|= (syndrome ? SUNXI_NAND_CMD_ORDER_SEQ :
229		- SUNXI_NAND_CMD_ORDER_INTERLEAVE);
230		- writel(cmd, &nand->cmd);
231		-
232		- if(nand_wait_timeout(&nand->st, SUNXI_NAND_ST_DMA_INT,
233		- SUNXI_NAND_ST_DMA_INT)) {
234		- printf("NAND timeout reading data\n");
235		- return;
236		- }
237		-
238		- if(nand_wait_timeout(&dma_cfg->ctl, SUNXI_DMA_CTL_TRIGGER, 0)) {
239		- printf("NAND timeout reading data\n");
240		- return;
241		- }
242		-
243		- if (readl(&nand->ecc_st))
244		- ecc_errors++;
245		-}
246		-
247		-int
248		-nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
249		-{
250		- struct sunxi_nand * const nand = (struct sunxi_nand *)SUNXI_NFC_BASE;
251		- dma_addr_t dst_block;
252		- dma_addr_t dst_end;
253		- phys_addr_t addr = offs;
254		-
255		- dst_end = ((dma_addr_t) dest) + size;
256		-
257		- memset((void *)dest, 0x0, size);
258		- ecc_errors = 0;
259		- for (dst_block = (dma_addr_t) dest; dst_block < dst_end;
260		- dst_block += CONFIG_NAND_SUNXI_ECC_STEP,
261		- addr += CONFIG_NAND_SUNXI_ECC_STEP) {
262		- /* syndrome read first 4MiB to match Allwinner BootROM */
263		- nand_read_block(nand, addr, dst_block, addr < 0x400000);
264		- }
265		-
266		- if (ecc_errors)
267		- printf("Error: %d ECC failures detected\n", ecc_errors);
268		- return ecc_errors == 0;
269		-}
270		-
271		-void
272		-nand_deselect(void)
273		-{}
...	...	@@ -18,7 +18,6 @@
18	18	#endif
19	19
20	20	#define CONFIG_SUNXI_USB_PHYS 3
21		-#define CONFIG_NAND_SUNXI_GPC_PORTS {16, 17, 18, 19, 20, 21, 22, 24}
22	21
23	22	/*
24	23	* Include common sunxi configuration where most the settings are
...	...	@@ -19,9 +19,6 @@
19	19
20	20	#define CONFIG_SUNXI_USB_PHYS 2
21	21
22		-/* \todo A13 only defines port 19, whereas A10s requires each of these */
23		-#define CONFIG_NAND_SUNXI_GPC_PORTS {16, 17, 18, 19}
24		-
25	22	/*
26	23	* Include common sunxi configuration where most the settings are
27	24	*/
...	...	@@ -27,8 +27,6 @@
27	27	#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
28	28	#define CONFIG_TIMER_CLK_FREQ 24000000
29	29
30		-#define CONFIG_NAND_SUNXI_GPC_PORTS {24, 25, 26}
31		-
32	30	/*
33	31	* Include common sunxi configuration where most the settings are
34	32	*/