Add support for UEC to 8568

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>

Add support for UEC to 8568
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Andy Fleming · Andrew Fleming-AFLEMING
1 parent c59e4091ff
Showing 15 changed files with 313 additions and 35 deletions Side-by-side Diff
Makefile
board/mpc8568mds/bcsr.c
board/mpc8568mds/bcsr.h
board/mpc8568mds/mpc8568mds.c
cpu/mpc85xx/Makefile
cpu/mpc85xx/cpu.c
cpu/mpc85xx/cpu_init.c
cpu/mpc85xx/qe_io.c
drivers/qe/uec.c
drivers/qe/uec.h
drivers/qe/uec_phy.c
drivers/qe/uec_phy.h
include/asm-ppc/global_data.h
include/asm-ppc/immap_qe.h
include/configs/MPC8568MDS.h
@@ -212,6 +212,9 @@
 ifeq ($(CPU),mpc83xx)
 LIBS += drivers/qe/qe.a
 endif
+ifeq ($(CPU),mpc85xx)
+LIBS += drivers/qe/qe.a
+endif
 LIBS += drivers/sk98lin/libsk98lin.a
 LIBS += post/libpost.a post/drivers/libpostdrivers.a
 LIBS += $(shell if [ -d post/lib_$(ARCH) ]; then echo \
@@ -47,4 +47,11 @@
  
 	bcsr[9] &= ~(0x01);
 }
+
+void enable_8568mds_qe_mdio()
+{
+	u8 *bcsr = (u8 *)(CFG_BCSR);
+
+	bcsr[7] |= 0x01;
+}
@@ -95,6 +95,7 @@
 void enable_8568mds_duart(void);
 void enable_8568mds_flash_write(void);
 void disable_8568mds_flash_write(void);
+void enable_8568mds_qe_mdio(void);
  
 #endif	/* __BCSR_H_ */
@@ -28,10 +28,66 @@
 #include <asm/immap_85xx.h>
 #include <spd.h>
 #include <i2c.h>
+#include <ioports.h>
  
 #include "bcsr.h"
  
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+	/* GETH1 */
+	{4, 10, 1, 0, 2}, /* TxD0 */
+	{4,  9, 1, 0, 2}, /* TxD1 */
+	{4,  8, 1, 0, 2}, /* TxD2 */
+	{4,  7, 1, 0, 2}, /* TxD3 */
+	{4, 23, 1, 0, 2}, /* TxD4 */
+	{4, 22, 1, 0, 2}, /* TxD5 */
+	{4, 21, 1, 0, 2}, /* TxD6 */
+	{4, 20, 1, 0, 2}, /* TxD7 */
+	{4, 15, 2, 0, 2}, /* RxD0 */
+	{4, 14, 2, 0, 2}, /* RxD1 */
+	{4, 13, 2, 0, 2}, /* RxD2 */
+	{4, 12, 2, 0, 2}, /* RxD3 */
+	{4, 29, 2, 0, 2}, /* RxD4 */
+	{4, 28, 2, 0, 2}, /* RxD5 */
+	{4, 27, 2, 0, 2}, /* RxD6 */
+	{4, 26, 2, 0, 2}, /* RxD7 */
+	{4, 11, 1, 0, 2}, /* TX_EN */
+	{4, 24, 1, 0, 2}, /* TX_ER */
+	{4, 16, 2, 0, 2}, /* RX_DV */
+	{4, 30, 2, 0, 2}, /* RX_ER */
+	{4, 17, 2, 0, 2}, /* RX_CLK */
+	{4, 19, 1, 0, 2}, /* GTX_CLK */
+	{1, 31, 2, 0, 3}, /* GTX125 */
  
+	/* GETH2 */
+	{5, 10, 1, 0, 2}, /* TxD0 */
+	{5,  9, 1, 0, 2}, /* TxD1 */
+	{5,  8, 1, 0, 2}, /* TxD2 */
+	{5,  7, 1, 0, 2}, /* TxD3 */
+	{5, 23, 1, 0, 2}, /* TxD4 */
+	{5, 22, 1, 0, 2}, /* TxD5 */
+	{5, 21, 1, 0, 2}, /* TxD6 */
+	{5, 20, 1, 0, 2}, /* TxD7 */
+	{5, 15, 2, 0, 2}, /* RxD0 */
+	{5, 14, 2, 0, 2}, /* RxD1 */
+	{5, 13, 2, 0, 2}, /* RxD2 */
+	{5, 12, 2, 0, 2}, /* RxD3 */
+	{5, 29, 2, 0, 2}, /* RxD4 */
+	{5, 28, 2, 0, 2}, /* RxD5 */
+	{5, 27, 2, 0, 3}, /* RxD6 */
+	{5, 26, 2, 0, 2}, /* RxD7 */
+	{5, 11, 1, 0, 2}, /* TX_EN */
+	{5, 24, 1, 0, 2}, /* TX_ER */
+	{5, 16, 2, 0, 2}, /* RX_DV */
+	{5, 30, 2, 0, 2}, /* RX_ER */
+	{5, 17, 2, 0, 2}, /* RX_CLK */
+	{5, 19, 1, 0, 2}, /* GTX_CLK */
+	{1, 31, 2, 0, 3}, /* GTX125 */
+	{4,  6, 3, 0, 2}, /* MDIO */
+	{4,  5, 1, 0, 2}, /* MDC */
+	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
+};
+
+
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
@@ -50,6 +106,9 @@
  
 	enable_8568mds_duart();
 	enable_8568mds_flash_write();
+#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
+	enable_8568mds_qe_mdio();
+#endif
  
 #ifdef CFG_I2C2_OFFSET
 	/* Enable I2C2_SCL and I2C2_SDA */
@@ -335,7 +394,7 @@
 {
 #ifdef CONFIG_PCI
 	pib_init();
-	pci_mpc85xx_init(&hose);
+	pci_mpc85xx_init(hose);
 #endif
 }
@@ -30,7 +30,7 @@
  
 START	= start.o resetvec.o
 COBJS	= traps.o cpu.o cpu_init.o speed.o interrupts.o \
-	  pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o
+	  pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o
  
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
@@ -280,7 +280,7 @@
 	if (p != NULL)
 		*p = cpu_to_be32(clock);
  
-#if defined(CONFIG_TSEC1)
+#if defined(CONFIG_HAS_ETH0)
 	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
 	if (p)
 		memcpy(p, bd->bi_enetaddr, 6);
  
@@ -308,7 +308,18 @@
 	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/local-mac-address", &len);
 	if (p)
 		memcpy(p, bd->bi_enet2addr, 6);
+
+#ifdef CONFIG_UEC_ETH
+	p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len);
+	if (p)
+		memcpy(p, bd->bi_enet2addr, 6);
+
+	p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len);
+	if (p)
+		memcpy(p, bd->bi_enet2addr, 6);
+
 #endif
+#endif
  
 #if defined(CONFIG_HAS_ETH3)
 	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len);
@@ -318,6 +329,17 @@
 	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/local-mac-address", &len);
 	if (p)
 		memcpy(p, bd->bi_enet3addr, 6);
+
+#ifdef CONFIG_UEC_ETH
+	p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len);
+	if (p)
+		memcpy(p, bd->bi_enet3addr, 6);
+
+	p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len);
+	if (p)
+		memcpy(p, bd->bi_enet3addr, 6);
+
+#endif
 #endif
  
 }
@@ -34,7 +34,30 @@
  
 DECLARE_GLOBAL_DATA_PTR;
  
+#ifdef CONFIG_QE
+extern qe_iop_conf_t qe_iop_conf_tab[];
+extern void qe_config_iopin(u8 port, u8 pin, int dir,
+				int open_drain, int assign);
+extern void qe_init(uint qe_base);
+extern void qe_reset(void);
  
+static void config_qe_ioports(void)
+{
+	u8      port, pin;
+	int     dir, open_drain, assign;
+	int     i;
+
+	for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
+		port		= qe_iop_conf_tab[i].port;
+		pin		= qe_iop_conf_tab[i].pin;
+		dir		= qe_iop_conf_tab[i].dir;
+		open_drain	= qe_iop_conf_tab[i].open_drain;
+		assign		= qe_iop_conf_tab[i].assign;
+		qe_config_iopin(port, pin, dir, open_drain, assign);
+	}
+}
+#endif
+
 #ifdef CONFIG_CPM2
 static void config_8560_ioports (volatile immap_t * immr)
 {
@@ -181,6 +204,11 @@
 #if defined(CONFIG_CPM2)
 	m8560_cpm_reset();
 #endif
+#ifdef CONFIG_QE
+	/* Config QE ioports */
+	config_qe_ioports();
+#endif
+
 }
  
  
@@ -261,6 +289,11 @@
 	}
 #else
 	printf("L2 cache: disabled\n");
+#endif
+#ifdef CONFIG_QE
+	uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */
+	qe_init(qe_base);
+	qe_reset();
 #endif
  
 	return 0;
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *
+ * Dave Liu <daveliu@freescale.com>
+ * based on source code of Shlomi Gridish
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "common.h"
+#include "asm/errno.h"
+#include "asm/io.h"
+#include "asm/immap_85xx.h"
+
+#if defined(CONFIG_QE)
+#define	NUM_OF_PINS	32
+void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
+{
+	u32			pin_2bit_mask;
+	u32			pin_2bit_dir;
+	u32			pin_2bit_assign;
+	u32			pin_1bit_mask;
+	u32			tmp_val;
+	volatile immap_t	*im = (volatile immap_t *)CFG_IMMR;
+	volatile par_io_t	*par_io = (volatile par_io_t *)
+						&(im->im_gur.qe_par_io);
+
+	/* Caculate pin location and 2bit mask and dir */
+	pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
+	pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
+
+	/* Setup the direction */
+	tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? \
+		in_be32(&par_io[port].cpdir2) :
+		in_be32(&par_io[port].cpdir1);
+
+	if (pin > (NUM_OF_PINS/2) -1) {
+		out_be32(&par_io[port].cpdir2, ~pin_2bit_mask & tmp_val);
+		out_be32(&par_io[port].cpdir2, pin_2bit_dir | tmp_val);
+	} else {
+		out_be32(&par_io[port].cpdir1, ~pin_2bit_mask & tmp_val);
+		out_be32(&par_io[port].cpdir1, pin_2bit_dir | tmp_val);
+	}
+
+	/* Calculate pin location for 1bit mask */
+	pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1)));
+
+	/* Setup the open drain */
+	tmp_val = in_be32(&par_io[port].cpodr);
+	if (open_drain)
+		out_be32(&par_io[port].cpodr, pin_1bit_mask | tmp_val);
+	else
+		out_be32(&par_io[port].cpodr, ~pin_1bit_mask & tmp_val);
+
+	/* Setup the assignment */
+	tmp_val = (pin > (NUM_OF_PINS/2) - 1) ?
+		in_be32(&par_io[port].cppar2):
+		in_be32(&par_io[port].cppar1);
+	pin_2bit_assign = (u32)(assign
+				<< (NUM_OF_PINS - (pin%(NUM_OF_PINS/2)+1)*2));
+
+	/* Clear and set 2 bits mask */
+	if (pin > (NUM_OF_PINS/2) - 1) {
+		out_be32(&par_io[port].cppar2, ~pin_2bit_mask & tmp_val);
+		out_be32(&par_io[port].cppar2, pin_2bit_assign | tmp_val);
+	} else {
+		out_be32(&par_io[port].cppar1, ~pin_2bit_mask & tmp_val);
+		out_be32(&par_io[port].cppar1, pin_2bit_assign | tmp_val);
+	}
+}
+
+#endif /* CONFIG_QE */
@@ -391,17 +391,17 @@
 	return 0;
 }
  
-static int init_mii_management_configuration(uec_t *uec_regs)
+static int init_mii_management_configuration(uec_mii_t *uec_mii_regs)
 {
 	uint		timeout = 0x1000;
 	u32		miimcfg = 0;
  
-	miimcfg = in_be32(&uec_regs->miimcfg);
+	miimcfg = in_be32(&uec_mii_regs->miimcfg);
 	miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE;
-	out_be32(&uec_regs->miimcfg, miimcfg);
+	out_be32(&uec_mii_regs->miimcfg, miimcfg);
  
 	/* Wait until the bus is free */
-	while ((in_be32(&uec_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
+	while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
 	if (timeout <= 0) {
 		printf("%s: The MII Bus is stuck!", __FUNCTION__);
 		return -ETIMEDOUT;
  
@@ -413,13 +413,13 @@
 static int init_phy(struct eth_device *dev)
 {
 	uec_private_t		*uec;
-	uec_t			*uec_regs;
+	uec_mii_t		*umii_regs;
 	struct uec_mii_info	*mii_info;
 	struct phy_info		*curphy;
 	int			err;
  
 	uec = (uec_private_t *)dev->priv;
-	uec_regs = uec->uec_regs;
+	umii_regs = uec->uec_mii_regs;
  
 	uec->oldlink = 0;
 	uec->oldspeed = 0;
  
  
@@ -451,19 +451,19 @@
 	mii_info->mii_id = uec->uec_info->phy_address;
 	mii_info->dev = dev;
  
-	mii_info->mdio_read = &read_phy_reg;
-	mii_info->mdio_write = &write_phy_reg;
+	mii_info->mdio_read = &uec_read_phy_reg;
+	mii_info->mdio_write = &uec_write_phy_reg;
  
 	uec->mii_info = mii_info;
  
-	if (init_mii_management_configuration(uec_regs)) {
+	if (init_mii_management_configuration(umii_regs)) {
 		printf("%s: The MII Bus is stuck!", dev->name);
 		err = -1;
 		goto bus_fail;
 	}
  
 	/* get info for this PHY */
-	curphy = get_phy_info(uec->mii_info);
+	curphy = uec_get_phy_info(uec->mii_info);
 	if (!curphy) {
 		printf("%s: No PHY found", dev->name);
 		err = -1;
@@ -988,6 +988,13 @@
  
 	/* Setup MAC interface mode */
 	uec_set_mac_if_mode(uec, uec_info->enet_interface);
+
+	/* Setup MII management base */
+#ifndef CONFIG_eTSEC_MDIO_BUS
+	uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg);
+#else
+	uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS;
+#endif
  
 	/* Setup MII master clock source */
 	qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
@@ -675,6 +675,7 @@
 	ucc_fast_private_t		*uccf;
 	struct eth_device		*dev;
 	uec_t				*uec_regs;
+	uec_mii_t			*uec_mii_regs;
 	/* enet init command parameter */
 	uec_init_cmd_pram_t		*p_init_enet_param;
 	u32				init_enet_param_offset;
@@ -60,14 +60,14 @@
 /* Write value to the PHY for this device to the register at regnum, */
 /* waiting until the write is done before it returns.  All PHY */
 /* configuration has to be done through the TSEC1 MIIM regs */
-void write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value)
+void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value)
 {
 	uec_private_t *ugeth = (uec_private_t *) dev->priv;
-	uec_t *ug_regs;
+	uec_mii_t *ug_regs;
 	enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
 	u32 tmp_reg;
  
-	ug_regs = ugeth->uec_regs;
+	ug_regs = ugeth->uec_mii_regs;
  
 	/* Stop the MII management read cycle */
 	out_be32 (&ug_regs->miimcom, 0);
  
  
@@ -87,15 +87,15 @@
 /* Reads from register regnum in the PHY for device dev, */
 /* returning the value.  Clears miimcom first.  All PHY */
 /* configuration has to be done through the TSEC1 MIIM regs */
-int read_phy_reg (struct eth_device *dev, int mii_id, int regnum)
+int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum)
 {
 	uec_private_t *ugeth = (uec_private_t *) dev->priv;
-	uec_t *ug_regs;
+	uec_mii_t *ug_regs;
 	enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
 	u32 tmp_reg;
 	u16 value;
  
-	ug_regs = ugeth->uec_regs;
+	ug_regs = ugeth->uec_mii_regs;
  
 	/* Setting up the MII Mangement Address Register */
 	tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
@@ -521,7 +521,7 @@
 /* Use the PHY ID registers to determine what type of PHY is attached
  * to device dev.  return a struct phy_info structure describing that PHY
  */
-struct phy_info *get_phy_info (struct uec_mii_info *mii_info)
+struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info)
 {
 	u16 phy_reg;
 	u32 phy_ID;
@@ -249,10 +249,10 @@
 	void (*close) (struct uec_mii_info * mii_info);
 };
  
-struct phy_info *get_phy_info (struct uec_mii_info *mii_info);
-void write_phy_reg (struct eth_device *dev, int mii_id, int regnum,
+struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info);
+void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum,
 		    int value);
-int read_phy_reg (struct eth_device *dev, int mii_id, int regnum);
+int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum);
 void mii_clear_phy_interrupt (struct uec_mii_info *mii_info);
 void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
 				  u32 interrupts);
@@ -71,16 +71,16 @@
 	u32 lclk_clk;
 	u32 ddr_clk;
 	u32 pci_clk;
+#if defined(CONFIG_MPC8360)
+	u32  ddr_sec_clk;
+#endif /* CONFIG_MPC8360 */
+#endif
 #if defined(CONFIG_QE)
 	u32 qe_clk;
 	u32 brg_clk;
 	uint mp_alloc_base;
 	uint mp_alloc_top;
 #endif /* CONFIG_QE */
-#if defined (CONFIG_MPC8360)
-	u32  ddr_sec_clk;
-#endif /* CONFIG_MPC8360 */
-#endif
 #if defined(CONFIG_MPC5xxx)
 	unsigned long	ipb_clk;
 	unsigned long	pci_clk;
@@ -281,6 +281,17 @@
 	u8 res4[0x200 - 0x091];
 } __attribute__ ((packed)) ucc_slow_t;
  
+typedef struct ucc_mii_mng {
+	u32 miimcfg;		/* MII management configuration reg    */
+	u32 miimcom;		/* MII management command reg          */
+	u32 miimadd;		/* MII management address reg          */
+	u32 miimcon;		/* MII management control reg          */
+	u32 miimstat;		/* MII management status reg           */
+	u32 miimind;		/* MII management indication reg       */
+	u32 ifctl;		/* interface control reg               */
+	u32 ifstat;		/* interface statux reg                */
+} __attribute__ ((packed))uec_mii_t;
+
 typedef struct ucc_ethernet {
 	u32 maccfg1;		/* mac configuration reg. 1            */
 	u32 maccfg2;		/* mac configuration reg. 2            */
  
  
@@ -540,14 +551,21 @@
 	u8 res14[0x300];
 	u8 res15[0x3A00];
 	u8 res16[0x8000];	/* 0x108000 -  0x110000 */
+#if defined(CONFIG_MPC8568)
+	u8 muram[0x10000];	/* 0x1_0000 -  0x2_0000 Multi-user RAM */
+	u8 res17[0x20000];	/* 0x2_0000 -  0x4_0000 */
+#else
 	u8 muram[0xC000];	/* 0x110000 -  0x11C000 Multi-user RAM */
 	u8 res17[0x24000];	/* 0x11C000 -  0x140000 */
 	u8 res18[0xC0000];	/* 0x140000 -  0x200000 */
+#endif
 } __attribute__ ((packed)) qe_map_t;
  
 extern qe_map_t *qe_immr;
  
-#if defined(CONFIG_MPC8360)
+#if defined(CONFIG_MPC8568)
+#define QE_MURAM_SIZE		0x10000UL
+#elif defined(CONFIG_MPC8360)
 #define QE_MURAM_SIZE		0xc000UL
 #elif defined(CONFIG_MPC832X)
 #define QE_MURAM_SIZE		0x4000UL
@@ -28,20 +28,21 @@
  
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		1	/* BOOKE */
-#define CONFIG_E500			1	/* BOOKE e500 family */
+#define CONFIG_E500		1	/* BOOKE e500 family */
 #define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48/68 */
 #define CONFIG_MPC8568		1	/* MPC8568 specific */
 #define CONFIG_MPC8568MDS	1	/* MPC8568MDS board specific */
  
 #define CONFIG_PCI
 #define CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#undef CONFIG_QE			/* Enable QE */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
 /*#define CONFIG_DDR_2T_TIMING		 Sets the 2T timing bit */
  
 /*#define CONFIG_DDR_ECC*/			/* only for ECC DDR module */
-/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/	/* 	 DDR controller or DMA? */
+/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE		0xDeadBeef
  
  
@@ -297,6 +298,7 @@
  
 #define OF_CPU			"PowerPC,8568@0"
 #define OF_SOC			"soc8568@e0000000"
+#define OF_QE			"qe@e0080000"
 #define OF_TBCLK		(bd->bi_busfreq / 8)
 #define OF_STDOUT_PATH		"/soc8568@e0000000/serial@4600"
  
@@ -311,7 +313,7 @@
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CFG_I2C_EEPROM_ADDR	0x52
 #define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES        {0,0x69}	/* Don't probe these addrs */
+#define CFG_I2C_NOPROBES        {{0,0x69}}	/* Don't probe these addrs */
 #define CFG_I2C_OFFSET		0x3000
 #define CFG_I2C2_OFFSET		0x3100
  
@@ -340,6 +342,44 @@
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
  
+#ifdef CONFIG_QE
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH
+#ifndef CONFIG_TSEC_ENET
+#define CONFIG_ETHPRIME         "Freescale GETH"
+#endif
+#define CONFIG_PHY_MODE_NEED_CHANGE
+#define CONFIG_eTSEC_MDIO_BUS
+
+#ifdef CONFIG_eTSEC_MDIO_BUS
+#define CONFIG_MIIM_ADDRESS 	0xE0024520
+#endif
+
+#define CONFIG_UEC_ETH1         /* GETH1 */
+
+#ifdef CONFIG_UEC_ETH1
+#define CFG_UEC1_UCC_NUM        0       /* UCC1 */
+#define CFG_UEC1_RX_CLK         QE_CLK_NONE
+#define CFG_UEC1_TX_CLK         QE_CLK16
+#define CFG_UEC1_ETH_TYPE       GIGA_ETH
+#define CFG_UEC1_PHY_ADDR       7
+#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
+#endif
+
+#define CONFIG_UEC_ETH2         /* GETH2 */
+
+#ifdef CONFIG_UEC_ETH2
+#define CFG_UEC2_UCC_NUM        1       /* UCC2 */
+#define CFG_UEC2_RX_CLK         QE_CLK_NONE
+#define CFG_UEC2_TX_CLK         QE_CLK16
+#define CFG_UEC2_ETH_TYPE       GIGA_ETH
+#define CFG_UEC2_PHY_ADDR       1
+#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
+#endif
+#endif /* CONFIG_QE */
+
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
  
  
@@ -348,13 +388,12 @@
  
 #endif	/* CONFIG_PCI */
  
-
-#if defined(CONFIG_TSEC_ENET)
-
 #ifndef CONFIG_NET_MULTI
 #define CONFIG_NET_MULTI 	1
 #endif
  
+#if defined(CONFIG_TSEC_ENET)
+
 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_TSEC1	1
 #define CONFIG_TSEC1_NAME	"eTSEC0"
  
@@ -460,12 +499,15 @@
  */
  
 /* The mac addresses for all ethernet interface */
-#if defined(CONFIG_TSEC_ENET)
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
+#define CONFIG_HAS_ETH0
 #define CONFIG_ETHADDR   00:E0:0C:00:00:FD
 #define CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 #define CONFIG_HAS_ETH2
 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
+#define CONFIG_HAS_ETH3
+#define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
 #endif
  
 #define CONFIG_IPADDR    192.168.1.253
...	...	@@ -212,6 +212,9 @@
212	212	ifeq ($(CPU),mpc83xx)
213	213	LIBS += drivers/qe/qe.a
214	214	endif
	215	+ifeq ($(CPU),mpc85xx)
	216	+LIBS += drivers/qe/qe.a
	217	+endif
215	218	LIBS += drivers/sk98lin/libsk98lin.a
216	219	LIBS += post/libpost.a post/drivers/libpostdrivers.a
217	220	LIBS += $(shell if [ -d post/lib_$(ARCH) ]; then echo \
...	...	@@ -47,4 +47,11 @@
47	47
48	48	bcsr[9] &= ~(0x01);
49	49	}
	50	+
	51	+void enable_8568mds_qe_mdio()
	52	+{
	53	+ u8 bcsr = (u8 )(CFG_BCSR);
	54	+
	55	+ bcsr[7] \|= 0x01;
	56	+}
...	...	@@ -95,6 +95,7 @@
95	95	void enable_8568mds_duart(void);
96	96	void enable_8568mds_flash_write(void);
97	97	void disable_8568mds_flash_write(void);
	98	+void enable_8568mds_qe_mdio(void);
98	99
99	100	#endif /* __BCSR_H_ */
...	...	@@ -28,10 +28,66 @@
28	28	#include <asm/immap_85xx.h>
29	29	#include <spd.h>
30	30	#include <i2c.h>
	31	+#include <ioports.h>
31	32
32	33	#include "bcsr.h"
33	34
	35	+const qe_iop_conf_t qe_iop_conf_tab[] = {
	36	+ /* GETH1 */
	37	+ {4, 10, 1, 0, 2}, /* TxD0 */
	38	+ {4, 9, 1, 0, 2}, /* TxD1 */
	39	+ {4, 8, 1, 0, 2}, /* TxD2 */
	40	+ {4, 7, 1, 0, 2}, /* TxD3 */
	41	+ {4, 23, 1, 0, 2}, /* TxD4 */
	42	+ {4, 22, 1, 0, 2}, /* TxD5 */
	43	+ {4, 21, 1, 0, 2}, /* TxD6 */
	44	+ {4, 20, 1, 0, 2}, /* TxD7 */
	45	+ {4, 15, 2, 0, 2}, /* RxD0 */
	46	+ {4, 14, 2, 0, 2}, /* RxD1 */
	47	+ {4, 13, 2, 0, 2}, /* RxD2 */
	48	+ {4, 12, 2, 0, 2}, /* RxD3 */
	49	+ {4, 29, 2, 0, 2}, /* RxD4 */
	50	+ {4, 28, 2, 0, 2}, /* RxD5 */
	51	+ {4, 27, 2, 0, 2}, /* RxD6 */
	52	+ {4, 26, 2, 0, 2}, /* RxD7 */
	53	+ {4, 11, 1, 0, 2}, /* TX_EN */
	54	+ {4, 24, 1, 0, 2}, /* TX_ER */
	55	+ {4, 16, 2, 0, 2}, /* RX_DV */
	56	+ {4, 30, 2, 0, 2}, /* RX_ER */
	57	+ {4, 17, 2, 0, 2}, /* RX_CLK */
	58	+ {4, 19, 1, 0, 2}, /* GTX_CLK */
	59	+ {1, 31, 2, 0, 3}, /* GTX125 */
34	60
	61	+ /* GETH2 */
	62	+ {5, 10, 1, 0, 2}, /* TxD0 */
	63	+ {5, 9, 1, 0, 2}, /* TxD1 */
	64	+ {5, 8, 1, 0, 2}, /* TxD2 */
	65	+ {5, 7, 1, 0, 2}, /* TxD3 */
	66	+ {5, 23, 1, 0, 2}, /* TxD4 */
	67	+ {5, 22, 1, 0, 2}, /* TxD5 */
	68	+ {5, 21, 1, 0, 2}, /* TxD6 */
	69	+ {5, 20, 1, 0, 2}, /* TxD7 */
	70	+ {5, 15, 2, 0, 2}, /* RxD0 */
	71	+ {5, 14, 2, 0, 2}, /* RxD1 */
	72	+ {5, 13, 2, 0, 2}, /* RxD2 */
	73	+ {5, 12, 2, 0, 2}, /* RxD3 */
	74	+ {5, 29, 2, 0, 2}, /* RxD4 */
	75	+ {5, 28, 2, 0, 2}, /* RxD5 */
	76	+ {5, 27, 2, 0, 3}, /* RxD6 */
	77	+ {5, 26, 2, 0, 2}, /* RxD7 */
	78	+ {5, 11, 1, 0, 2}, /* TX_EN */
	79	+ {5, 24, 1, 0, 2}, /* TX_ER */
	80	+ {5, 16, 2, 0, 2}, /* RX_DV */
	81	+ {5, 30, 2, 0, 2}, /* RX_ER */
	82	+ {5, 17, 2, 0, 2}, /* RX_CLK */
	83	+ {5, 19, 1, 0, 2}, /* GTX_CLK */
	84	+ {1, 31, 2, 0, 3}, /* GTX125 */
	85	+ {4, 6, 3, 0, 2}, /* MDIO */
	86	+ {4, 5, 1, 0, 2}, /* MDC */
	87	+ {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
	88	+};
	89	+
	90	+
35	91	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
36	92	extern void ddr_enable_ecc(unsigned int dram_size);
37	93	#endif
...	...	@@ -50,6 +106,9 @@
50	106
51	107	enable_8568mds_duart();
52	108	enable_8568mds_flash_write();
	109	+#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
	110	+ enable_8568mds_qe_mdio();
	111	+#endif
53	112
54	113	#ifdef CFG_I2C2_OFFSET
55	114	/* Enable I2C2_SCL and I2C2_SDA */
...	...	@@ -335,7 +394,7 @@
335	394	{
336	395	#ifdef CONFIG_PCI
337	396	pib_init();
338		- pci_mpc85xx_init(&hose);
	397	+ pci_mpc85xx_init(hose);
339	398	#endif
340	399	}
...	...	@@ -30,7 +30,7 @@
30	30
31	31	START = start.o resetvec.o
32	32	COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \
33		- pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o
	33	+ pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o
34	34
35	35	SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
36	36	OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
...	...	@@ -280,7 +280,7 @@
280	280	if (p != NULL)
281	281	*p = cpu_to_be32(clock);
282	282
283		-#if defined(CONFIG_TSEC1)
	283	+#if defined(CONFIG_HAS_ETH0)
284	284	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
285	285	if (p)
286	286	memcpy(p, bd->bi_enetaddr, 6);
287	287
...	...	@@ -308,7 +308,18 @@
308	308	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/local-mac-address", &len);
309	309	if (p)
310	310	memcpy(p, bd->bi_enet2addr, 6);
	311	+
	312	+#ifdef CONFIG_UEC_ETH
	313	+ p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len);
	314	+ if (p)
	315	+ memcpy(p, bd->bi_enet2addr, 6);
	316	+
	317	+ p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len);
	318	+ if (p)
	319	+ memcpy(p, bd->bi_enet2addr, 6);
	320	+
311	321	#endif
	322	+#endif
312	323
313	324	#if defined(CONFIG_HAS_ETH3)
314	325	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len);
...	...	@@ -318,6 +329,17 @@
318	329	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/local-mac-address", &len);
319	330	if (p)
320	331	memcpy(p, bd->bi_enet3addr, 6);
	332	+
	333	+#ifdef CONFIG_UEC_ETH
	334	+ p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len);
	335	+ if (p)
	336	+ memcpy(p, bd->bi_enet3addr, 6);
	337	+
	338	+ p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len);
	339	+ if (p)
	340	+ memcpy(p, bd->bi_enet3addr, 6);
	341	+
	342	+#endif
321	343	#endif
322	344
323	345	}
...	...	@@ -34,7 +34,30 @@
34	34
35	35	DECLARE_GLOBAL_DATA_PTR;
36	36
	37	+#ifdef CONFIG_QE
	38	+extern qe_iop_conf_t qe_iop_conf_tab[];
	39	+extern void qe_config_iopin(u8 port, u8 pin, int dir,
	40	+ int open_drain, int assign);
	41	+extern void qe_init(uint qe_base);
	42	+extern void qe_reset(void);
37	43
	44	+static void config_qe_ioports(void)
	45	+{
	46	+ u8 port, pin;
	47	+ int dir, open_drain, assign;
	48	+ int i;
	49	+
	50	+ for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
	51	+ port = qe_iop_conf_tab[i].port;
	52	+ pin = qe_iop_conf_tab[i].pin;
	53	+ dir = qe_iop_conf_tab[i].dir;
	54	+ open_drain = qe_iop_conf_tab[i].open_drain;
	55	+ assign = qe_iop_conf_tab[i].assign;
	56	+ qe_config_iopin(port, pin, dir, open_drain, assign);
	57	+ }
	58	+}
	59	+#endif
	60	+
38	61	#ifdef CONFIG_CPM2
39	62	static void config_8560_ioports (volatile immap_t * immr)
40	63	{
...	...	@@ -181,6 +204,11 @@
181	204	#if defined(CONFIG_CPM2)
182	205	m8560_cpm_reset();
183	206	#endif
	207	+#ifdef CONFIG_QE
	208	+ /* Config QE ioports */
	209	+ config_qe_ioports();
	210	+#endif
	211	+
184	212	}
185	213
186	214
...	...	@@ -261,6 +289,11 @@
261	289	}
262	290	#else
263	291	printf("L2 cache: disabled\n");
	292	+#endif
	293	+#ifdef CONFIG_QE
	294	+ uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */
	295	+ qe_init(qe_base);
	296	+ qe_reset();
264	297	#endif
265	298
266	299	return 0;
	1	+/*
	2	+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
	3	+ *
	4	+ * Dave Liu <daveliu@freescale.com>
	5	+ * based on source code of Shlomi Gridish
	6	+ *
	7	+ * This program is free software; you can redistribute it and/or
	8	+ * modify it under the terms of the GNU General Public License as
	9	+ * published by the Free Software Foundation; either version 2 of
	10	+ * the License, or (at your option) any later version.
	11	+ *
	12	+ * This program is distributed in the hope that it will be useful,
	13	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	+ * GNU General Public License for more details.
	16	+ *
	17	+ * You should have received a copy of the GNU General Public License
	18	+ * along with this program; if not, write to the Free Software
	19	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	+ * MA 02111-1307 USA
	21	+ */
	22	+
	23	+#include "common.h"
	24	+#include "asm/errno.h"
	25	+#include "asm/io.h"
	26	+#include "asm/immap_85xx.h"
	27	+
	28	+#if defined(CONFIG_QE)
	29	+#define NUM_OF_PINS 32
	30	+void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
	31	+{
	32	+ u32 pin_2bit_mask;
	33	+ u32 pin_2bit_dir;
	34	+ u32 pin_2bit_assign;
	35	+ u32 pin_1bit_mask;
	36	+ u32 tmp_val;
	37	+ volatile immap_t im = (volatile immap_t )CFG_IMMR;
	38	+ volatile par_io_t par_io = (volatile par_io_t )
	39	+ &(im->im_gur.qe_par_io);
	40	+
	41	+ /* Caculate pin location and 2bit mask and dir */
	42	+ pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
	43	+ pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
	44	+
	45	+ /* Setup the direction */
	46	+ tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? \
	47	+ in_be32(&par_io[port].cpdir2) :
	48	+ in_be32(&par_io[port].cpdir1);
	49	+
	50	+ if (pin > (NUM_OF_PINS/2) -1) {
	51	+ out_be32(&par_io[port].cpdir2, ~pin_2bit_mask & tmp_val);
	52	+ out_be32(&par_io[port].cpdir2, pin_2bit_dir \| tmp_val);
	53	+ } else {
	54	+ out_be32(&par_io[port].cpdir1, ~pin_2bit_mask & tmp_val);
	55	+ out_be32(&par_io[port].cpdir1, pin_2bit_dir \| tmp_val);
	56	+ }
	57	+
	58	+ /* Calculate pin location for 1bit mask */
	59	+ pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1)));
	60	+
	61	+ /* Setup the open drain */
	62	+ tmp_val = in_be32(&par_io[port].cpodr);
	63	+ if (open_drain)
	64	+ out_be32(&par_io[port].cpodr, pin_1bit_mask \| tmp_val);
	65	+ else
	66	+ out_be32(&par_io[port].cpodr, ~pin_1bit_mask & tmp_val);
	67	+
	68	+ /* Setup the assignment */
	69	+ tmp_val = (pin > (NUM_OF_PINS/2) - 1) ?
	70	+ in_be32(&par_io[port].cppar2):
	71	+ in_be32(&par_io[port].cppar1);
	72	+ pin_2bit_assign = (u32)(assign
	73	+ << (NUM_OF_PINS - (pin%(NUM_OF_PINS/2)+1)*2));
	74	+
	75	+ /* Clear and set 2 bits mask */
	76	+ if (pin > (NUM_OF_PINS/2) - 1) {
	77	+ out_be32(&par_io[port].cppar2, ~pin_2bit_mask & tmp_val);
	78	+ out_be32(&par_io[port].cppar2, pin_2bit_assign \| tmp_val);
	79	+ } else {
	80	+ out_be32(&par_io[port].cppar1, ~pin_2bit_mask & tmp_val);
	81	+ out_be32(&par_io[port].cppar1, pin_2bit_assign \| tmp_val);
	82	+ }
	83	+}
	84	+
	85	+#endif /* CONFIG_QE */
...	...	@@ -391,17 +391,17 @@
391	391	return 0;
392	392	}
393	393
394		-static int init_mii_management_configuration(uec_t *uec_regs)
	394	+static int init_mii_management_configuration(uec_mii_t *uec_mii_regs)
395	395	{
396	396	uint timeout = 0x1000;
397	397	u32 miimcfg = 0;
398	398
399		- miimcfg = in_be32(&uec_regs->miimcfg);
	399	+ miimcfg = in_be32(&uec_mii_regs->miimcfg);
400	400	miimcfg \|= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE;
401		- out_be32(&uec_regs->miimcfg, miimcfg);
	401	+ out_be32(&uec_mii_regs->miimcfg, miimcfg);
402	402
403	403	/* Wait until the bus is free */
404		- while ((in_be32(&uec_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
	404	+ while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
405	405	if (timeout <= 0) {
406	406	printf("%s: The MII Bus is stuck!", __FUNCTION__);
407	407	return -ETIMEDOUT;
408	408
...	...	@@ -413,13 +413,13 @@
413	413	static int init_phy(struct eth_device *dev)
414	414	{
415	415	uec_private_t *uec;
416		- uec_t *uec_regs;
	416	+ uec_mii_t *umii_regs;
417	417	struct uec_mii_info *mii_info;
418	418	struct phy_info *curphy;
419	419	int err;
420	420
421	421	uec = (uec_private_t *)dev->priv;
422		- uec_regs = uec->uec_regs;
	422	+ umii_regs = uec->uec_mii_regs;
423	423
424	424	uec->oldlink = 0;
425	425	uec->oldspeed = 0;
426	426
427	427
...	...	@@ -451,19 +451,19 @@
451	451	mii_info->mii_id = uec->uec_info->phy_address;
452	452	mii_info->dev = dev;
453	453
454		- mii_info->mdio_read = &read_phy_reg;
455		- mii_info->mdio_write = &write_phy_reg;
	454	+ mii_info->mdio_read = &uec_read_phy_reg;
	455	+ mii_info->mdio_write = &uec_write_phy_reg;
456	456
457	457	uec->mii_info = mii_info;
458	458
459		- if (init_mii_management_configuration(uec_regs)) {
	459	+ if (init_mii_management_configuration(umii_regs)) {
460	460	printf("%s: The MII Bus is stuck!", dev->name);
461	461	err = -1;
462	462	goto bus_fail;
463	463	}
464	464
465	465	/* get info for this PHY */
466		- curphy = get_phy_info(uec->mii_info);
	466	+ curphy = uec_get_phy_info(uec->mii_info);
467	467	if (!curphy) {
468	468	printf("%s: No PHY found", dev->name);
469	469	err = -1;
...	...	@@ -988,6 +988,13 @@
988	988
989	989	/* Setup MAC interface mode */
990	990	uec_set_mac_if_mode(uec, uec_info->enet_interface);
	991	+
	992	+ /* Setup MII management base */
	993	+#ifndef CONFIG_eTSEC_MDIO_BUS
	994	+ uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg);
	995	+#else
	996	+ uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS;
	997	+#endif
991	998
992	999	/* Setup MII master clock source */
993	1000	qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
...	...	@@ -675,6 +675,7 @@
675	675	ucc_fast_private_t *uccf;
676	676	struct eth_device *dev;
677	677	uec_t *uec_regs;
	678	+ uec_mii_t *uec_mii_regs;
678	679	/* enet init command parameter */
679	680	uec_init_cmd_pram_t *p_init_enet_param;
680	681	u32 init_enet_param_offset;