Eric Lee / smarc-uboot

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Commit db2cc879f7e53ead1e3615c1d61ba0b571e81dfa

Authored by Ye Li
1 parent a84dedb351
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 5 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

MLK-17821-1 USB: gadget: Add the cadence USB3 gadget driver 

Porting the cadence USB3 (CDNS3) driver from kernel to u-boot. We only support
the gadget (device mode), while the host mode is not supported. Users remains
to use xhci-imx8 driver for host mode.

Some changes in the CDNS3 driver porting:

1. Add match_ep call back to usb_gadget_ops. The CDNS3 gadget driver replies
   on this operation to bind the usb_ep/usb_ss_ep with the endpoint descriptor
   when function layer uses usb_ep_autoconfig to add endpoint descriptors to gadget.
   So that CDNS3 driver can know the EP information and configure the EP once the
   set configuration request is received.

2. U-boot does not have CMA, so it won't allocate uncached memory. Need to flush
   TRB and its DMA buffer before prime to usb controller and after complete transfer.

3. In core.c, we add functions to hook with u-boot. It needs uplayer like
   to pass the register base address of each part of the USB controller.

4. Force the CDNS3 gadget max speed to HS. The SuperSpeed is not supported by u-boot,
   so disable it in gadget driver. A configuration USB_CDNS3_GADGET_FORCE_HIGHSPEED is
   selected.

5. Added gadget_is_cdns3 checking to provide bcdUSB value in device descriptor.

6. Moved some new fields in usb_ep structure to usb_ss_ep, since u-boot does not have them.

7. Remove host part codes as it is not supported by this driver.

Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peter Chen <peter.chen@nxp.com>
(cherry picked from commit 70514bd095ff9a94e9a523845641381486284257)

Showing 19 changed files with 4320 additions and 0 deletions Side-by-side Diff

... ... @@ -678,6 +678,7 @@
678 678 libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/
679 679 libs-$(CONFIG_ALTERA_SDRAM) += drivers/ddr/altera/
680 680 libs-y += drivers/serial/
  681 +libs-y += drivers/usb/cdns3/
681 682 libs-y += drivers/usb/dwc3/
682 683 libs-y += drivers/usb/common/
683 684 libs-y += drivers/usb/emul/
... ... @@ -51,6 +51,8 @@
51 51  
52 52 source "drivers/usb/dwc3/Kconfig"
53 53  
  54 +source "drivers/usb/cdns3/Kconfig"
  55 +
54 56 source "drivers/usb/musb/Kconfig"
55 57  
56 58 source "drivers/usb/musb-new/Kconfig"
drivers/usb/cdns3/Kconfig
Diff comments   View file @ db2cc87
  1 +config USB_CDNS3
  2 + tristate "Cadence USB3 Dual-Role Controller"
  3 + depends on (USB && USB_GADGET)
  4 + help
  5 + Say Y here if your system has a cadence USB3 dual-role controller.
  6 + It supports: dual-role switch Host-only, and Peripheral-only.
  7 +
  8 + When compiled dynamically, the module will be called cdns3.ko.
  9 +
  10 +if USB_CDNS3
  11 +
  12 +config USB_CDNS3_GADGET_FORCE_HIGHSPEED
  13 + bool
  14 +
  15 +config USB_CDNS3_GADGET
  16 + bool "Cadence USB3 device controller"
  17 + depends on USB_GADGET
  18 + select USB_GADGET_DUALSPEED
  19 + select USB_CDNS3_GADGET_FORCE_HIGHSPEED
  20 + help
  21 + Say Y here to enable device controller functionality of the
  22 + cadence usb3 driver.
  23 +
  24 +endif
drivers/usb/cdns3/Makefile
Diff comments   View file @ db2cc87
  1 +obj-$(CONFIG_USB_CDNS3) += cdns3.o
  2 +
  3 +cdns3-y := core.o
  4 +cdns3-$(CONFIG_USB_CDNS3_GADGET) += gadget.o
drivers/usb/cdns3/cdns3-nxp-reg-def.h
Diff comments   View file @ db2cc87
  1 +/*
  2 + * Copyright 2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __DRIVERS_USB_CDNS3_NXP_H
  8 +#define __DRIVERS_USB_CDNS3_NXP_H
  9 +
  10 +#define USB3_CORE_CTRL1 0x00
  11 +#define USB3_CORE_CTRL2 0x04
  12 +#define USB3_INT_REG 0x08
  13 +#define USB3_CORE_STATUS 0x0c
  14 +#define XHCI_DEBUG_LINK_ST 0x10
  15 +#define XHCI_DEBUG_BUS 0x14
  16 +#define USB3_SSPHY_CTRL1 0x40
  17 +#define USB3_SSPHY_CTRL2 0x44
  18 +#define USB3_SSPHY_STATUS 0x4c
  19 +#define USB2_PHY_CTRL1 0x50
  20 +#define USB2_PHY_CTRL2 0x54
  21 +#define USB2_PHY_STATUS 0x5c
  22 +
  23 +/* Register bits definition */
  24 +
  25 +/* USB3_CORE_CTRL1 */
  26 +#define SW_RESET_MASK (0x3f << 26)
  27 +#define PWR_SW_RESET (1 << 31)
  28 +#define APB_SW_RESET (1 << 30)
  29 +#define AXI_SW_RESET (1 << 29)
  30 +#define RW_SW_RESET (1 << 28)
  31 +#define PHY_SW_RESET (1 << 27)
  32 +#define PHYAHB_SW_RESET (1 << 26)
  33 +#define ALL_SW_RESET (PWR_SW_RESET | APB_SW_RESET | AXI_SW_RESET | \
  34 + RW_SW_RESET | PHY_SW_RESET | PHYAHB_SW_RESET)
  35 +#define OC_DISABLE (1 << 9)
  36 +#define MDCTRL_CLK_SEL (1 << 7)
  37 +#define MODE_STRAP_MASK (0x7)
  38 +#define DEV_MODE (1 << 2)
  39 +#define HOST_MODE (1 << 1)
  40 +#define OTG_MODE (1 << 0)
  41 +
  42 +/* USB3_INT_REG */
  43 +#define CLK_125_REQ (1 << 29)
  44 +#define LPM_CLK_REQ (1 << 28)
  45 +#define DEVU3_WAEKUP_EN (1 << 14)
  46 +#define OTG_WAKEUP_EN (1 << 12)
  47 +#define DEV_INT_EN (3 << 8) /* DEV INT b9:8 */
  48 +#define HOST_INT1_EN (1 << 0) /* HOST INT b7:0 */
  49 +
  50 +/* USB3_CORE_STATUS */
  51 +#define MDCTRL_CLK_STATUS (1 << 15)
  52 +#define DEV_POWER_ON_READY (1 << 13)
  53 +#define HOST_POWER_ON_READY (1 << 12)
  54 +
  55 +/* USB3_SSPHY_STATUS */
  56 +#define PHY_REFCLK_REQ (1 << 0)
  57 +
  58 +
  59 +/* PHY register definition */
  60 +#define PHY_PMA_CMN_CTRL1 (0xC800 * 4)
  61 +#define TB_ADDR_CMN_DIAG_HSCLK_SEL (0x01e0 * 4)
  62 +#define TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR (0x0084 * 4)
  63 +#define TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR (0x0085 * 4)
  64 +#define TB_ADDR_CMN_PLL0_INTDIV (0x0094 * 4)
  65 +#define TB_ADDR_CMN_PLL0_FRACDIV (0x0095 * 4)
  66 +#define TB_ADDR_CMN_PLL0_HIGH_THR (0x0096 * 4)
  67 +#define TB_ADDR_CMN_PLL0_SS_CTRL1 (0x0098 * 4)
  68 +#define TB_ADDR_CMN_PLL0_SS_CTRL2 (0x0099 * 4)
  69 +#define TB_ADDR_CMN_PLL0_DSM_DIAG (0x0097 * 4)
  70 +#define TB_ADDR_CMN_DIAG_PLL0_OVRD (0x01c2 * 4)
  71 +#define TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD (0x01c0 * 4)
  72 +#define TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD (0x01c1 * 4)
  73 +#define TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE (0x01C5 * 4)
  74 +#define TB_ADDR_CMN_DIAG_PLL0_CP_TUNE (0x01C6 * 4)
  75 +#define TB_ADDR_CMN_DIAG_PLL0_LF_PROG (0x01C7 * 4)
  76 +#define TB_ADDR_CMN_DIAG_PLL0_TEST_MODE (0x01c4 * 4)
  77 +#define TB_ADDR_CMN_PSM_CLK_CTRL (0x0061 * 4)
  78 +#define TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR (0x40ea * 4)
  79 +#define TB_ADDR_XCVR_PSM_RCTRL (0x4001 * 4)
  80 +#define TB_ADDR_TX_PSC_A0 (0x4100 * 4)
  81 +#define TB_ADDR_TX_PSC_A1 (0x4101 * 4)
  82 +#define TB_ADDR_TX_PSC_A2 (0x4102 * 4)
  83 +#define TB_ADDR_TX_PSC_A3 (0x4103 * 4)
  84 +#define TB_ADDR_TX_DIAG_ECTRL_OVRD (0x41f5 * 4)
  85 +#define TB_ADDR_TX_PSC_CAL (0x4106 * 4)
  86 +#define TB_ADDR_TX_PSC_RDY (0x4107 * 4)
  87 +#define TB_ADDR_RX_PSC_A0 (0x8000 * 4)
  88 +#define TB_ADDR_RX_PSC_A1 (0x8001 * 4)
  89 +#define TB_ADDR_RX_PSC_A2 (0x8002 * 4)
  90 +#define TB_ADDR_RX_PSC_A3 (0x8003 * 4)
  91 +#define TB_ADDR_RX_PSC_CAL (0x8006 * 4)
  92 +#define TB_ADDR_RX_PSC_RDY (0x8007 * 4)
  93 +#define TB_ADDR_TX_TXCC_MGNLS_MULT_000 (0x4058 * 4)
  94 +#define TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY (0x41e7 * 4)
  95 +#define TB_ADDR_RX_SLC_CU_ITER_TMR (0x80e3 * 4)
  96 +#define TB_ADDR_RX_SIGDET_HL_FILT_TMR (0x8090 * 4)
  97 +#define TB_ADDR_RX_SAMP_DAC_CTRL (0x8058 * 4)
  98 +#define TB_ADDR_RX_DIAG_SIGDET_TUNE (0x81dc * 4)
  99 +#define TB_ADDR_RX_DIAG_LFPSDET_TUNE2 (0x81df * 4)
  100 +#define TB_ADDR_RX_DIAG_BS_TM (0x81f5 * 4)
  101 +#define TB_ADDR_RX_DIAG_DFE_CTRL1 (0x81d3 * 4)
  102 +#define TB_ADDR_RX_DIAG_ILL_IQE_TRIM4 (0x81c7 * 4)
  103 +#define TB_ADDR_RX_DIAG_ILL_E_TRIM0 (0x81c2 * 4)
  104 +#define TB_ADDR_RX_DIAG_ILL_IQ_TRIM0 (0x81c1 * 4)
  105 +#define TB_ADDR_RX_DIAG_ILL_IQE_TRIM6 (0x81c9 * 4)
  106 +#define TB_ADDR_RX_DIAG_RXFE_TM3 (0x81f8 * 4)
  107 +#define TB_ADDR_RX_DIAG_RXFE_TM4 (0x81f9 * 4)
  108 +#define TB_ADDR_RX_DIAG_LFPSDET_TUNE (0x81dd * 4)
  109 +#define TB_ADDR_RX_DIAG_DFE_CTRL3 (0x81d5 * 4)
  110 +#define TB_ADDR_RX_DIAG_SC2C_DELAY (0x81e1 * 4)
  111 +#define TB_ADDR_RX_REE_VGA_GAIN_NODFE (0x81bf * 4)
  112 +#define TB_ADDR_XCVR_PSM_CAL_TMR (0x4002 * 4)
  113 +#define TB_ADDR_XCVR_PSM_A0BYP_TMR (0x4004 * 4)
  114 +#define TB_ADDR_XCVR_PSM_A0IN_TMR (0x4003 * 4)
  115 +#define TB_ADDR_XCVR_PSM_A1IN_TMR (0x4005 * 4)
  116 +#define TB_ADDR_XCVR_PSM_A2IN_TMR (0x4006 * 4)
  117 +#define TB_ADDR_XCVR_PSM_A3IN_TMR (0x4007 * 4)
  118 +#define TB_ADDR_XCVR_PSM_A4IN_TMR (0x4008 * 4)
  119 +#define TB_ADDR_XCVR_PSM_A5IN_TMR (0x4009 * 4)
  120 +#define TB_ADDR_XCVR_PSM_A0OUT_TMR (0x400a * 4)
  121 +#define TB_ADDR_XCVR_PSM_A1OUT_TMR (0x400b * 4)
  122 +#define TB_ADDR_XCVR_PSM_A2OUT_TMR (0x400c * 4)
  123 +#define TB_ADDR_XCVR_PSM_A3OUT_TMR (0x400d * 4)
  124 +#define TB_ADDR_XCVR_PSM_A4OUT_TMR (0x400e * 4)
  125 +#define TB_ADDR_XCVR_PSM_A5OUT_TMR (0x400f * 4)
  126 +#define TB_ADDR_TX_RCVDET_EN_TMR (0x4122 * 4)
  127 +#define TB_ADDR_TX_RCVDET_ST_TMR (0x4123 * 4)
  128 +#define TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR (0x40f2 * 4)
  129 +#define TB_ADDR_TX_RCVDETSC_CTRL (0x4124 * 4)
  130 +
  131 +/* Register bits definition */
  132 +
  133 +/* TB_ADDR_TX_RCVDETSC_CTRL */
  134 +#define RXDET_IN_P3_32KHZ (1 << 0)
  135 +
  136 +/* OTG registers definition */
  137 +#define OTGSTS 0x4
  138 +#define OTGREFCLK 0xc
  139 +
  140 +/* Register bits definition */
  141 +/* OTGSTS */
  142 +#define OTG_NRDY (1 << 11)
  143 +/* OTGREFCLK */
  144 +#define OTG_STB_CLK_SWITCH_EN (1 << 31)
  145 +
  146 +/* xHCI registers definition */
  147 +#define XECP_PORT_CAP_REG 0x8000
  148 +#define XECP_PM_PMCSR 0x8018
  149 +#define XECP_AUX_CTRL_REG1 0x8120
  150 +
  151 +/* Register bits definition */
  152 +/* XECP_PORT_CAP_REG */
  153 +#define LPM_2_STB_SWITCH_EN (1 << 25)
  154 +
  155 +/* XECP_AUX_CTRL_REG1 */
  156 +#define CFG_RXDET_P3_EN (1 << 15)
  157 +
  158 +/* XECP_PM_PMCSR */
  159 +#define PS_D0 (1 << 0)
  160 +#endif /* __DRIVERS_USB_CDNS3_NXP_H */
drivers/usb/cdns3/core.c
Diff comments   View file @ db2cc87
  1 +/*
  2 + * Copyright (C) 2016 Cadence Design Systems - https://www.cadence.com/
  3 + * Copyright 2018 NXP
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0
  6 + */
  7 +#include <common.h>
  8 +#include <malloc.h>
  9 +#include <asm/dma-mapping.h>
  10 +#include <asm/io.h>
  11 +#include <linux/bug.h>
  12 +#include <linux/list.h>
  13 +#include <linux/compat.h>
  14 +#include <cdns3-uboot.h>
  15 +
  16 +#include "linux-compat.h"
  17 +#include "cdns3-nxp-reg-def.h"
  18 +#include "core.h"
  19 +#include "gadget-export.h"
  20 +
  21 +static LIST_HEAD(cdns3_list);
  22 +
  23 +/* Need SoC level to implement the clock */
  24 +__weak int cdns3_enable_clks(int index)
  25 +{
  26 + return 0;
  27 +}
  28 +
  29 +__weak int cdns3_disable_clks(int index)
  30 +{
  31 + return 0;
  32 +}
  33 +
  34 +static void cdns3_usb_phy_init(void __iomem *regs)
  35 +{
  36 + u32 value;
  37 +
  38 + pr_debug("begin of %s\n", __func__);
  39 +
  40 + writel(0x0830, regs + PHY_PMA_CMN_CTRL1);
  41 + writel(0x10, regs + TB_ADDR_CMN_DIAG_HSCLK_SEL);
  42 + writel(0x00F0, regs + TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR);
  43 + writel(0x0018, regs + TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR);
  44 + writel(0x00D0, regs + TB_ADDR_CMN_PLL0_INTDIV);
  45 + writel(0x4aaa, regs + TB_ADDR_CMN_PLL0_FRACDIV);
  46 + writel(0x0034, regs + TB_ADDR_CMN_PLL0_HIGH_THR);
  47 + writel(0x1ee, regs + TB_ADDR_CMN_PLL0_SS_CTRL1);
  48 + writel(0x7F03, regs + TB_ADDR_CMN_PLL0_SS_CTRL2);
  49 + writel(0x0020, regs + TB_ADDR_CMN_PLL0_DSM_DIAG);
  50 + writel(0x0000, regs + TB_ADDR_CMN_DIAG_PLL0_OVRD);
  51 + writel(0x0000, regs + TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD);
  52 + writel(0x0000, regs + TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD);
  53 + writel(0x0007, regs + TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE);
  54 + writel(0x0027, regs + TB_ADDR_CMN_DIAG_PLL0_CP_TUNE);
  55 + writel(0x0008, regs + TB_ADDR_CMN_DIAG_PLL0_LF_PROG);
  56 + writel(0x0022, regs + TB_ADDR_CMN_DIAG_PLL0_TEST_MODE);
  57 + writel(0x000a, regs + TB_ADDR_CMN_PSM_CLK_CTRL);
  58 + writel(0x139, regs + TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR);
  59 + writel(0xbefc, regs + TB_ADDR_XCVR_PSM_RCTRL);
  60 +
  61 + writel(0x7799, regs + TB_ADDR_TX_PSC_A0);
  62 + writel(0x7798, regs + TB_ADDR_TX_PSC_A1);
  63 + writel(0x509b, regs + TB_ADDR_TX_PSC_A2);
  64 + writel(0x3, regs + TB_ADDR_TX_DIAG_ECTRL_OVRD);
  65 + writel(0x509b, regs + TB_ADDR_TX_PSC_A3);
  66 + writel(0x2090, regs + TB_ADDR_TX_PSC_CAL);
  67 + writel(0x2090, regs + TB_ADDR_TX_PSC_RDY);
  68 +
  69 + writel(0xA6FD, regs + TB_ADDR_RX_PSC_A0);
  70 + writel(0xA6FD, regs + TB_ADDR_RX_PSC_A1);
  71 + writel(0xA410, regs + TB_ADDR_RX_PSC_A2);
  72 + writel(0x2410, regs + TB_ADDR_RX_PSC_A3);
  73 +
  74 + writel(0x23FF, regs + TB_ADDR_RX_PSC_CAL);
  75 + writel(0x2010, regs + TB_ADDR_RX_PSC_RDY);
  76 +
  77 + writel(0x0020, regs + TB_ADDR_TX_TXCC_MGNLS_MULT_000);
  78 + writel(0x00ff, regs + TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY);
  79 + writel(0x0002, regs + TB_ADDR_RX_SLC_CU_ITER_TMR);
  80 + writel(0x0013, regs + TB_ADDR_RX_SIGDET_HL_FILT_TMR);
  81 + writel(0x0000, regs + TB_ADDR_RX_SAMP_DAC_CTRL);
  82 + writel(0x1004, regs + TB_ADDR_RX_DIAG_SIGDET_TUNE);
  83 + writel(0x4041, regs + TB_ADDR_RX_DIAG_LFPSDET_TUNE2);
  84 + writel(0x0480, regs + TB_ADDR_RX_DIAG_BS_TM);
  85 + writel(0x8006, regs + TB_ADDR_RX_DIAG_DFE_CTRL1);
  86 + writel(0x003f, regs + TB_ADDR_RX_DIAG_ILL_IQE_TRIM4);
  87 + writel(0x543f, regs + TB_ADDR_RX_DIAG_ILL_E_TRIM0);
  88 + writel(0x543f, regs + TB_ADDR_RX_DIAG_ILL_IQ_TRIM0);
  89 + writel(0x0000, regs + TB_ADDR_RX_DIAG_ILL_IQE_TRIM6);
  90 + writel(0x8000, regs + TB_ADDR_RX_DIAG_RXFE_TM3);
  91 + writel(0x0003, regs + TB_ADDR_RX_DIAG_RXFE_TM4);
  92 + writel(0x2408, regs + TB_ADDR_RX_DIAG_LFPSDET_TUNE);
  93 + writel(0x05ca, regs + TB_ADDR_RX_DIAG_DFE_CTRL3);
  94 + writel(0x0258, regs + TB_ADDR_RX_DIAG_SC2C_DELAY);
  95 + writel(0x1fff, regs + TB_ADDR_RX_REE_VGA_GAIN_NODFE);
  96 +
  97 + writel(0x02c6, regs + TB_ADDR_XCVR_PSM_CAL_TMR);
  98 + writel(0x0002, regs + TB_ADDR_XCVR_PSM_A0BYP_TMR);
  99 + writel(0x02c6, regs + TB_ADDR_XCVR_PSM_A0IN_TMR);
  100 + writel(0x0010, regs + TB_ADDR_XCVR_PSM_A1IN_TMR);
  101 + writel(0x0010, regs + TB_ADDR_XCVR_PSM_A2IN_TMR);
  102 + writel(0x0010, regs + TB_ADDR_XCVR_PSM_A3IN_TMR);
  103 + writel(0x0010, regs + TB_ADDR_XCVR_PSM_A4IN_TMR);
  104 + writel(0x0010, regs + TB_ADDR_XCVR_PSM_A5IN_TMR);
  105 +
  106 + writel(0x0002, regs + TB_ADDR_XCVR_PSM_A0OUT_TMR);
  107 + writel(0x0002, regs + TB_ADDR_XCVR_PSM_A1OUT_TMR);
  108 + writel(0x0002, regs + TB_ADDR_XCVR_PSM_A2OUT_TMR);
  109 + writel(0x0002, regs + TB_ADDR_XCVR_PSM_A3OUT_TMR);
  110 + writel(0x0002, regs + TB_ADDR_XCVR_PSM_A4OUT_TMR);
  111 + writel(0x0002, regs + TB_ADDR_XCVR_PSM_A5OUT_TMR);
  112 +
  113 + /* Change rx detect parameter */
  114 + writel(0x960, regs + TB_ADDR_TX_RCVDET_EN_TMR);
  115 + writel(0x01e0, regs + TB_ADDR_TX_RCVDET_ST_TMR);
  116 + writel(0x0090, regs + TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR);
  117 +
  118 + /* RXDET_IN_P3_32KHZ, Receiver detect slow clock enable */
  119 + value = readl(regs + TB_ADDR_TX_RCVDETSC_CTRL);
  120 + value |= RXDET_IN_P3_32KHZ;
  121 + writel(value, regs + TB_ADDR_TX_RCVDETSC_CTRL);
  122 +
  123 + udelay(10);
  124 +
  125 + pr_debug("end of %s\n", __func__);
  126 +}
  127 +
  128 +static void cdns3_reset_core(struct cdns3 *cdns)
  129 +{
  130 + u32 value;
  131 +
  132 + value = readl(cdns->none_core_regs + USB3_CORE_CTRL1);
  133 + value |= ALL_SW_RESET;
  134 + writel(value, cdns->none_core_regs + USB3_CORE_CTRL1);
  135 + udelay(1);
  136 +}
  137 +
  138 +static void cdns3_set_role(struct cdns3 *cdns, enum cdns3_roles role)
  139 +{
  140 + u32 value;
  141 + int timeout_us = 100000;
  142 +
  143 + if (role == CDNS3_ROLE_END)
  144 + return;
  145 +
  146 + /* Wait clk value */
  147 + value = readl(cdns->none_core_regs + USB3_SSPHY_STATUS);
  148 + writel(value, cdns->none_core_regs + USB3_SSPHY_STATUS);
  149 + udelay(1);
  150 + value = readl(cdns->none_core_regs + USB3_SSPHY_STATUS);
  151 + while ((value & 0xf0000000) != 0xf0000000 && timeout_us-- > 0) {
  152 + value = readl(cdns->none_core_regs + USB3_SSPHY_STATUS);
  153 + dev_dbg(cdns->dev, "clkvld:0x%x\n", value);
  154 + udelay(1);
  155 + }
  156 +
  157 + if (timeout_us <= 0)
  158 + dev_err(cdns->dev, "wait clkvld timeout\n");
  159 +
  160 + /* Set all Reset bits */
  161 + value = readl(cdns->none_core_regs + USB3_CORE_CTRL1);
  162 + value |= ALL_SW_RESET;
  163 + writel(value, cdns->none_core_regs + USB3_CORE_CTRL1);
  164 + udelay(1);
  165 +
  166 + if (role == CDNS3_ROLE_HOST) {
  167 + value = readl(cdns->none_core_regs + USB3_CORE_CTRL1);
  168 + value = (value & ~MODE_STRAP_MASK) | HOST_MODE | OC_DISABLE;
  169 + writel(value, cdns->none_core_regs + USB3_CORE_CTRL1);
  170 + value &= ~PHYAHB_SW_RESET;
  171 + writel(value, cdns->none_core_regs + USB3_CORE_CTRL1);
  172 + mdelay(1);
  173 + cdns3_usb_phy_init(cdns->phy_regs);
  174 + /* Force B Session Valid as 1 */
  175 + writel(0x0060, cdns->phy_regs + 0x380a4);
  176 + mdelay(1);
  177 +
  178 + value = readl(cdns->none_core_regs + USB3_INT_REG);
  179 + value |= HOST_INT1_EN;
  180 + writel(value, cdns->none_core_regs + USB3_INT_REG);
  181 +
  182 + value = readl(cdns->none_core_regs + USB3_CORE_CTRL1);
  183 + value &= ~ALL_SW_RESET;
  184 + writel(value, cdns->none_core_regs + USB3_CORE_CTRL1);
  185 +
  186 + dev_dbg(cdns->dev, "wait xhci_power_on_ready\n");
  187 +
  188 + value = readl(cdns->none_core_regs + USB3_CORE_STATUS);
  189 + timeout_us = 100000;
  190 + while (!(value & HOST_POWER_ON_READY) && timeout_us-- > 0) {
  191 + value = readl(cdns->none_core_regs + USB3_CORE_STATUS);
  192 + udelay(1);
  193 + }
  194 +
  195 + if (timeout_us <= 0)
  196 + dev_err(cdns->dev, "wait xhci_power_on_ready timeout\n");
  197 +
  198 + mdelay(1);
  199 +
  200 + dev_dbg(cdns->dev, "switch to host role successfully\n");
  201 + } else { /* gadget mode */
  202 + value = readl(cdns->none_core_regs + USB3_CORE_CTRL1);
  203 + value = (value & ~MODE_STRAP_MASK) | DEV_MODE;
  204 + writel(value, cdns->none_core_regs + USB3_CORE_CTRL1);
  205 + value &= ~PHYAHB_SW_RESET;
  206 + writel(value, cdns->none_core_regs + USB3_CORE_CTRL1);
  207 +
  208 + cdns3_usb_phy_init(cdns->phy_regs);
  209 + /* Force B Session Valid as 1 */
  210 + writel(0x0060, cdns->phy_regs + 0x380a4);
  211 + value = readl(cdns->none_core_regs + USB3_INT_REG);
  212 + value |= DEV_INT_EN;
  213 + writel(value, cdns->none_core_regs + USB3_INT_REG);
  214 +
  215 + value = readl(cdns->none_core_regs + USB3_CORE_CTRL1);
  216 + value &= ~ALL_SW_RESET;
  217 + writel(value, cdns->none_core_regs + USB3_CORE_CTRL1);
  218 +
  219 + dev_dbg(cdns->dev, "wait gadget_power_on_ready\n");
  220 +
  221 + value = readl(cdns->none_core_regs + USB3_CORE_STATUS);
  222 + timeout_us = 100000;
  223 + while (!(value & DEV_POWER_ON_READY) && timeout_us-- > 0) {
  224 + value = readl(cdns->none_core_regs + USB3_CORE_STATUS);
  225 + udelay(1);
  226 + }
  227 +
  228 + if (timeout_us <= 0)
  229 + dev_err(cdns->dev,
  230 + "wait gadget_power_on_ready timeout\n");
  231 +
  232 + mdelay(1);
  233 +
  234 + dev_dbg(cdns->dev, "switch to gadget role successfully\n");
  235 + }
  236 +}
  237 +
  238 +static enum cdns3_roles cdns3_get_role(struct cdns3 *cdns)
  239 +{
  240 + return cdns->roles[CDNS3_ROLE_HOST]
  241 + ? CDNS3_ROLE_HOST
  242 + : CDNS3_ROLE_GADGET;
  243 +}
  244 +
  245 +/**
  246 + * cdns3_core_init_role - initialize role of operation
  247 + * @cdns: Pointer to cdns3 structure
  248 + *
  249 + * Returns 0 on success otherwise negative errno
  250 + */
  251 +static int cdns3_core_init_role(struct cdns3 *cdns, enum usb_dr_mode dr_mode)
  252 +{
  253 + cdns->role = CDNS3_ROLE_END;
  254 + if (dr_mode == USB_DR_MODE_UNKNOWN)
  255 + dr_mode = USB_DR_MODE_OTG;
  256 +
  257 + /* Currently, only support gadget mode */
  258 + if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
  259 + dev_err(cdns->dev, "doesn't support host and OTG, only for gadget\n");
  260 + return -EPERM;
  261 + }
  262 +
  263 + if (dr_mode == USB_DR_MODE_PERIPHERAL) {
  264 + if (cdns3_gadget_init(cdns))
  265 + dev_info(cdns->dev, "doesn't support gadget\n");
  266 + }
  267 +
  268 + if (!cdns->roles[CDNS3_ROLE_HOST] && !cdns->roles[CDNS3_ROLE_GADGET]) {
  269 + dev_err(cdns->dev, "no supported roles\n");
  270 + return -ENODEV;
  271 + }
  272 +
  273 + return 0;
  274 +}
  275 +
  276 +static void cdns3_remove_roles(struct cdns3 *cdns)
  277 +{
  278 + /* Only support gadget */
  279 + cdns3_gadget_remove(cdns);
  280 +}
  281 +
  282 +int cdns3_uboot_init(struct cdns3_device *cdns3_dev)
  283 +{
  284 + struct device *dev = NULL;
  285 + struct cdns3 *cdns;
  286 + int ret;
  287 +
  288 + cdns = devm_kzalloc(dev, sizeof(*cdns), GFP_KERNEL);
  289 + if (!cdns)
  290 + return -ENOMEM;
  291 +
  292 + cdns->dev = dev;
  293 +
  294 + /*
  295 + * Request memory region
  296 + * region-0: nxp wrap registers
  297 + * region-1: xHCI
  298 + * region-2: Peripheral
  299 + * region-3: PHY registers
  300 + * region-4: OTG registers
  301 + */
  302 + cdns->none_core_regs = (void __iomem *)cdns3_dev->none_core_base;
  303 + cdns->xhci_regs = (void __iomem *)cdns3_dev->xhci_base;
  304 + cdns->dev_regs = (void __iomem *)cdns3_dev->dev_base;
  305 + cdns->phy_regs = (void __iomem *)cdns3_dev->phy_base;
  306 + cdns->otg_regs = (void __iomem *)cdns3_dev->otg_base;
  307 + cdns->index = cdns3_dev->index;
  308 +
  309 + ret = cdns3_enable_clks(cdns->index);
  310 + if (ret)
  311 + return ret;
  312 +
  313 + ret = cdns3_core_init_role(cdns, cdns3_dev->dr_mode);
  314 + if (ret)
  315 + goto err1;
  316 +
  317 + cdns->role = cdns3_get_role(cdns);
  318 + dev_dbg(dev, "the init role is %d\n", cdns->role);
  319 + cdns3_set_role(cdns, cdns->role);
  320 + ret = cdns3_role_start(cdns, cdns->role);
  321 + if (ret) {
  322 + dev_err(dev, "can't start %s role\n", cdns3_role(cdns)->name);
  323 + goto err2;
  324 + }
  325 +
  326 + dev_dbg(dev, "Cadence USB3 core: probe succeed\n");
  327 +
  328 + list_add_tail(&cdns->list, &cdns3_list);
  329 +
  330 + return 0;
  331 +
  332 +err2:
  333 + cdns3_remove_roles(cdns);
  334 +err1:
  335 + cdns3_disable_clks(cdns->index);
  336 + return ret;
  337 +}
  338 +
  339 +void cdns3_uboot_exit(int index)
  340 +{
  341 + struct cdns3 *cdns;
  342 +
  343 + list_for_each_entry(cdns, &cdns3_list, list) {
  344 + if (cdns->index != index)
  345 + continue;
  346 +
  347 + cdns3_role_stop(cdns);
  348 + cdns3_remove_roles(cdns);
  349 + cdns3_reset_core(cdns);
  350 + cdns3_disable_clks(index);
  351 +
  352 + list_del(&cdns->list);
  353 + kfree(cdns);
  354 + break;
  355 + }
  356 +}
  357 +
  358 +void cdns3_uboot_handle_interrupt(int index)
  359 +{
  360 + struct cdns3 *cdns = NULL;
  361 +
  362 + list_for_each_entry(cdns, &cdns3_list, list) {
  363 + if (cdns->index != index)
  364 + continue;
  365 +
  366 + cdns3_role_irq_handler(cdns);
  367 + break;
  368 + }
  369 +}
drivers/usb/cdns3/core.h
Diff comments   View file @ db2cc87
  1 +/*
  2 + * Copyright 2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __DRIVERS_USB_CDNS3_CORE_H
  8 +#define __DRIVERS_USB_CDNS3_CORE_H
  9 +
  10 +struct cdns3;
  11 +enum cdns3_roles {
  12 + CDNS3_ROLE_HOST = 0,
  13 + CDNS3_ROLE_GADGET,
  14 + CDNS3_ROLE_END,
  15 +};
  16 +
  17 +/**
  18 + * struct cdns3_role_driver - host/gadget role driver
  19 + * @start: start this role
  20 + * @stop: stop this role
  21 + * @suspend: suspend callback for this role
  22 + * @resume: resume callback for this role
  23 + * @irq: irq handler for this role
  24 + * @name: role name string (host/gadget)
  25 + */
  26 +struct cdns3_role_driver {
  27 + int (*start)(struct cdns3 *);
  28 + void (*stop)(struct cdns3 *);
  29 + int (*suspend)(struct cdns3 *, bool do_wakeup);
  30 + int (*resume)(struct cdns3 *, bool hibernated);
  31 + int (*irq)(struct cdns3 *);
  32 + const char *name;
  33 +};
  34 +
  35 +#define CDNS3_NUM_OF_CLKS 5
  36 +/**
  37 + * struct cdns3 - Representation of Cadence USB3 DRD controller.
  38 + * @dev: pointer to Cadence device struct
  39 + * @xhci_regs: pointer to base of xhci registers
  40 + * @xhci_res: the resource for xhci
  41 + * @dev_regs: pointer to base of dev registers
  42 + * @none_core_regs: pointer to base of nxp wrapper registers
  43 + * @phy_regs: pointer to base of phy registers
  44 + * @otg_regs: pointer to base of otg registers
  45 + * @irq: irq number for controller
  46 + * @roles: array of supported roles for this controller
  47 + * @role: current role
  48 + * @host_dev: the child host device pointer for cdns3 core
  49 + * @gadget_dev: the child gadget device pointer for cdns3 core
  50 + * @usbphy: usbphy for this controller
  51 + * @cdns3_clks: Clock pointer array for cdns3 core
  52 + * @extcon: Type-C extern connector
  53 + * @extcon_nb: notifier block for Type-C extern connector
  54 + * @role_switch_wq: work queue item for role switch
  55 + * @in_lpm: the controller in low power mode
  56 + * @wakeup_int: the wakeup interrupt
  57 + */
  58 +struct cdns3 {
  59 + struct device *dev;
  60 + void __iomem *xhci_regs;
  61 + struct resource *xhci_res;
  62 + struct usbss_dev_register_block_type __iomem *dev_regs;
  63 + void __iomem *none_core_regs;
  64 + void __iomem *phy_regs;
  65 + void __iomem *otg_regs;
  66 + int irq;
  67 + struct cdns3_role_driver *roles[CDNS3_ROLE_END];
  68 + enum cdns3_roles role;
  69 + struct device *host_dev;
  70 + struct device *gadget_dev;
  71 + struct clk *cdns3_clks[CDNS3_NUM_OF_CLKS];
  72 +
  73 + int index;
  74 + struct list_head list;
  75 +};
  76 +
  77 +static inline struct cdns3_role_driver *cdns3_role(struct cdns3 *cdns)
  78 +{
  79 + WARN_ON(cdns->role >= CDNS3_ROLE_END || !cdns->roles[cdns->role]);
  80 + return cdns->roles[cdns->role];
  81 +}
  82 +
  83 +static inline int cdns3_role_start(struct cdns3 *cdns, enum cdns3_roles role)
  84 +{
  85 + if (role >= CDNS3_ROLE_END)
  86 + return 0;
  87 +
  88 + if (!cdns->roles[role])
  89 + return -ENXIO;
  90 +
  91 + cdns->role = role;
  92 + return cdns->roles[role]->start(cdns);
  93 +}
  94 +
  95 +static inline void cdns3_role_stop(struct cdns3 *cdns)
  96 +{
  97 + enum cdns3_roles role = cdns->role;
  98 +
  99 + if (role == CDNS3_ROLE_END)
  100 + return;
  101 +
  102 + cdns->roles[role]->stop(cdns);
  103 + cdns->role = CDNS3_ROLE_END;
  104 +}
  105 +
  106 +static inline void cdns3_role_irq_handler(struct cdns3 *cdns)
  107 +{
  108 + enum cdns3_roles role = cdns->role;
  109 +
  110 + if (role == CDNS3_ROLE_END)
  111 + return;
  112 +
  113 + cdns->roles[role]->irq(cdns);
  114 +}
  115 +
  116 +
  117 +#endif /* __DRIVERS_USB_CDNS3_CORE_H */
drivers/usb/cdns3/dev-regs-macro.h
Diff comments   View file @ db2cc87
  1 +/*
  2 + * Copyright (C) 2016 Cadence Design Systems - http://www.cadence.com
  3 + * Copyright 2018 NXP
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef __REG_USBSS_DEV_ADDR_MAP_MACRO_H__
  9 +#define __REG_USBSS_DEV_ADDR_MAP_MACRO_H__
  10 +
  11 +
  12 +/* macros for BlueprintGlobalNameSpace::USB_CONF */
  13 +#ifndef __USB_CONF_MACRO__
  14 +#define __USB_CONF_MACRO__
  15 +
  16 +/* macros for field CFGRST */
  17 +#define USB_CONF__CFGRST__MASK 0x00000001U
  18 +#define USB_CONF__CFGSET__MASK 0x00000002U
  19 +#define USB_CONF__USB3DIS__MASK 0x00000008U
  20 +#define USB_CONF__DEVEN__MASK 0x00004000U
  21 +#define USB_CONF__DEVDS__MASK 0x00008000U
  22 +#define USB_CONF__L1EN__MASK 0x00010000U
  23 +#define USB_CONF__L1DS__MASK 0x00020000U
  24 +#define USB_CONF__CLK2OFFDS__MASK 0x00080000U
  25 +#define USB_CONF__U1EN__MASK 0x01000000U
  26 +#define USB_CONF__U1DS__MASK 0x02000000U
  27 +#define USB_CONF__U2EN__MASK 0x04000000U
  28 +#define USB_CONF__U2DS__MASK 0x08000000U
  29 +#endif /* __USB_CONF_MACRO__ */
  30 +
  31 +
  32 +/* macros for usbss_dev_register_block.usb_conf */
  33 +#ifndef __USB_STS_MACRO__
  34 +#define __USB_STS_MACRO__
  35 +
  36 +/* macros for field CFGSTS */
  37 +#define USB_STS__CFGSTS__MASK 0x00000001U
  38 +#define USB_STS__USBSPEED__READ(src) (((uint32_t)(src) & 0x00000070U) >> 4)
  39 +
  40 +/* macros for field ENDIAN_MIRROR */
  41 +#define USB_STS__LPMST__READ(src) (((uint32_t)(src) & 0x000c0000U) >> 18)
  42 +
  43 +/* macros for field USB2CONS */
  44 +#define USB_STS__U1ENS__MASK 0x01000000U
  45 +#define USB_STS__U2ENS__MASK 0x02000000U
  46 +#define USB_STS__LST__READ(src) (((uint32_t)(src) & 0x3c000000U) >> 26)
  47 +
  48 +/* macros for field DMAOFF */
  49 +#endif /* __USB_STS_MACRO__ */
  50 +
  51 +
  52 +/* macros for usbss_dev_register_block.usb_sts */
  53 +#ifndef __USB_CMD_MACRO__
  54 +#define __USB_CMD_MACRO__
  55 +
  56 +/* macros for field SET_ADDR */
  57 +#define USB_CMD__SET_ADDR__MASK 0x00000001U
  58 +#define USB_CMD__STMODE 0x00000200U
  59 +#define USB_CMD__TMODE_SEL(x) (x << 10)
  60 +#define USB_CMD__FADDR__WRITE(src) (((uint32_t)(src) << 1) & 0x000000feU)
  61 +#endif /* __USB_CMD_MACRO__ */
  62 +
  63 +
  64 +/* macros for usbss_dev_register_block.usb_cmd */
  65 +#ifndef __USB_ITPN_MACRO__
  66 +#define __USB_ITPN_MACRO__
  67 +
  68 +/* macros for field ITPN */
  69 +#endif /* __USB_ITPN_MACRO__ */
  70 +
  71 +
  72 +/* macros for usbss_dev_register_block.usb_iptn */
  73 +#ifndef __USB_LPM_MACRO__
  74 +#define __USB_LPM_MACRO__
  75 +
  76 +/* macros for field HIRD */
  77 +#endif /* __USB_LPM_MACRO__ */
  78 +
  79 +
  80 +/* macros for usbss_dev_register_block.usb_lpm */
  81 +#ifndef __USB_IEN_MACRO__
  82 +#define __USB_IEN_MACRO__
  83 +
  84 +/* macros for field CONIEN */
  85 +#define USB_IEN__CONIEN__MASK 0x00000001U
  86 +#define USB_IEN__DISIEN__MASK 0x00000002U
  87 +#define USB_IEN__UWRESIEN__MASK 0x00000004U
  88 +#define USB_IEN__UHRESIEN__MASK 0x00000008U
  89 +#define USB_IEN__U3EXTIEN__MASK 0x00000020U
  90 +#define USB_IEN__CON2IEN__MASK 0x00010000U
  91 +#define USB_IEN__U2RESIEN__MASK 0x00040000U
  92 +#define USB_IEN__L2ENTIEN__MASK 0x00100000U
  93 +#define USB_IEN__L2EXTIEN__MASK 0x00200000U
  94 +#endif /* __USB_IEN_MACRO__ */
  95 +
  96 +
  97 +/* macros for usbss_dev_register_block.usb_ien */
  98 +#ifndef __USB_ISTS_MACRO__
  99 +#define __USB_ISTS_MACRO__
  100 +
  101 +/* macros for field CONI */
  102 +#define USB_ISTS__CONI__SHIFT 0
  103 +#define USB_ISTS__DISI__SHIFT 1
  104 +#define USB_ISTS__UWRESI__SHIFT 2
  105 +#define USB_ISTS__UHRESI__SHIFT 3
  106 +#define USB_ISTS__U3EXTI__SHIFT 5
  107 +#define USB_ISTS__CON2I__SHIFT 16
  108 +#define USB_ISTS__DIS2I__SHIFT 17
  109 +#define USB_ISTS__DIS2I__MASK 0x00020000U
  110 +#define USB_ISTS__U2RESI__SHIFT 18
  111 +#define USB_ISTS__L2ENTI__SHIFT 20
  112 +#define USB_ISTS__L2EXTI__SHIFT 21
  113 +#endif /* __USB_ISTS_MACRO__ */
  114 +
  115 +
  116 +/* macros for usbss_dev_register_block.usb_ists */
  117 +#ifndef __EP_SEL_MACRO__
  118 +#define __EP_SEL_MACRO__
  119 +
  120 +/* macros for field EPNO */
  121 +#endif /* __EP_SEL_MACRO__ */
  122 +
  123 +
  124 +/* macros for usbss_dev_register_block.ep_sel */
  125 +#ifndef __EP_TRADDR_MACRO__
  126 +#define __EP_TRADDR_MACRO__
  127 +
  128 +/* macros for field TRADDR */
  129 +#define EP_TRADDR__TRADDR__WRITE(src) ((uint32_t)(src) & 0xffffffffU)
  130 +#endif /* __EP_TRADDR_MACRO__ */
  131 +
  132 +
  133 +/* macros for usbss_dev_register_block.ep_traddr */
  134 +#ifndef __EP_CFG_MACRO__
  135 +#define __EP_CFG_MACRO__
  136 +
  137 +/* macros for field ENABLE */
  138 +#define EP_CFG__ENABLE__MASK 0x00000001U
  139 +#define EP_CFG__EPTYPE__WRITE(src) (((uint32_t)(src) << 1) & 0x00000006U)
  140 +#define EP_CFG__MAXBURST__WRITE(src) (((uint32_t)(src) << 8) & 0x00000f00U)
  141 +#define EP_CFG__MAXPKTSIZE__WRITE(src) (((uint32_t)(src) << 16) & 0x07ff0000U)
  142 +#define EP_CFG__BUFFERING__WRITE(src) (((uint32_t)(src) << 27) & 0xf8000000U)
  143 +#endif /* __EP_CFG_MACRO__ */
  144 +
  145 +
  146 +/* macros for usbss_dev_register_block.ep_cfg */
  147 +#ifndef __EP_CMD_MACRO__
  148 +#define __EP_CMD_MACRO__
  149 +
  150 +/* macros for field EPRST */
  151 +#define EP_CMD__EPRST__MASK 0x00000001U
  152 +#define EP_CMD__SSTALL__MASK 0x00000002U
  153 +#define EP_CMD__CSTALL__MASK 0x00000004U
  154 +#define EP_CMD__ERDY__MASK 0x00000008U
  155 +#define EP_CMD__REQ_CMPL__MASK 0x00000020U
  156 +#define EP_CMD__DRDY__MASK 0x00000040U
  157 +#define EP_CMD__DFLUSH__MASK 0x00000080U
  158 +#endif /* __EP_CMD_MACRO__ */
  159 +
  160 +
  161 +/* macros for usbss_dev_register_block.ep_cmd */
  162 +#ifndef __EP_STS_MACRO__
  163 +#define __EP_STS_MACRO__
  164 +
  165 +/* macros for field SETUP */
  166 +#define EP_STS__SETUP__MASK 0x00000001U
  167 +#define EP_STS__STALL__MASK 0x00000002U
  168 +#define EP_STS__IOC__MASK 0x00000004U
  169 +#define EP_STS__ISP__MASK 0x00000008U
  170 +#define EP_STS__DESCMIS__MASK 0x00000010U
  171 +#define EP_STS__TRBERR__MASK 0x00000080U
  172 +#define EP_STS__NRDY__MASK 0x00000100U
  173 +#define EP_STS__DBUSY__MASK 0x00000200U
  174 +#define EP_STS__OUTSMM__MASK 0x00004000U
  175 +#define EP_STS__ISOERR__MASK 0x00008000U
  176 +#endif /* __EP_STS_MACRO__ */
  177 +
  178 +
  179 +/* macros for usbss_dev_register_block.ep_sts */
  180 +#ifndef __EP_STS_SID_MACRO__
  181 +#define __EP_STS_SID_MACRO__
  182 +
  183 +/* macros for field SID */
  184 +#endif /* __EP_STS_SID_MACRO__ */
  185 +
  186 +
  187 +/* macros for usbss_dev_register_block.ep_sts_sid */
  188 +#ifndef __EP_STS_EN_MACRO__
  189 +#define __EP_STS_EN_MACRO__
  190 +
  191 +/* macros for field SETUPEN */
  192 +#define EP_STS_EN__SETUPEN__MASK 0x00000001U
  193 +#define EP_STS_EN__DESCMISEN__MASK 0x00000010U
  194 +#define EP_STS_EN__TRBERREN__MASK 0x00000080U
  195 +#endif /* __EP_STS_EN_MACRO__ */
  196 +
  197 +
  198 +/* macros for usbss_dev_register_block.ep_sts_en */
  199 +#ifndef __DRBL_MACRO__
  200 +#define __DRBL_MACRO__
  201 +
  202 +/* macros for field DRBL0O */
  203 +#endif /* __DRBL_MACRO__ */
  204 +
  205 +
  206 +/* macros for usbss_dev_register_block.drbl */
  207 +#ifndef __EP_IEN_MACRO__
  208 +#define __EP_IEN_MACRO__
  209 +
  210 +/* macros for field EOUTEN0 */
  211 +#define EP_IEN__EOUTEN0__MASK 0x00000001U
  212 +#define EP_IEN__EINEN0__MASK 0x00010000U
  213 +#endif /* __EP_IEN_MACRO__ */
  214 +
  215 +
  216 +/* macros for usbss_dev_register_block.ep_ien */
  217 +#ifndef __EP_ISTS_MACRO__
  218 +#define __EP_ISTS_MACRO__
  219 +
  220 +/* macros for field EOUT0 */
  221 +#define EP_ISTS__EOUT0__MASK 0x00000001U
  222 +#define EP_ISTS__EIN0__MASK 0x00010000U
  223 +#endif /* __EP_ISTS_MACRO__ */
  224 +
  225 +
  226 +/* macros for usbss_dev_register_block.ep_ists */
  227 +#ifndef __USB_PWR_MACRO__
  228 +#define __USB_PWR_MACRO__
  229 +
  230 +/* macros for field PSO_EN */
  231 +#endif /* __USB_PWR_MACRO__ */
  232 +
  233 +
  234 +/* macros for usbss_dev_register_block.usb_pwr */
  235 +#ifndef __USB_CONF2_MACRO__
  236 +#define __USB_CONF2_MACRO__
  237 +
  238 +/* macros for field AHB_RETRY_EN */
  239 +#endif /* __USB_CONF2_MACRO__ */
  240 +
  241 +
  242 +/* macros for usbss_dev_register_block.usb_conf2 */
  243 +#ifndef __USB_CAP1_MACRO__
  244 +#define __USB_CAP1_MACRO__
  245 +
  246 +/* macros for field SFR_TYPE */
  247 +#endif /* __USB_CAP1_MACRO__ */
  248 +
  249 +
  250 +/* macros for usbss_dev_register_block.usb_cap1 */
  251 +#ifndef __USB_CAP2_MACRO__
  252 +#define __USB_CAP2_MACRO__
  253 +
  254 +/* macros for field ACTUAL_MEM_SIZE */
  255 +#endif /* __USB_CAP2_MACRO__ */
  256 +
  257 +
  258 +/* macros for usbss_dev_register_block.usb_cap2 */
  259 +#ifndef __USB_CAP3_MACRO__
  260 +#define __USB_CAP3_MACRO__
  261 +
  262 +/* macros for field EPOUT_N */
  263 +#endif /* __USB_CAP3_MACRO__ */
  264 +
  265 +
  266 +/* macros for usbss_dev_register_block.usb_cap3 */
  267 +#ifndef __USB_CAP4_MACRO__
  268 +#define __USB_CAP4_MACRO__
  269 +
  270 +/* macros for field EPOUTI_N */
  271 +#endif /* __USB_CAP4_MACRO__ */
  272 +
  273 +
  274 +/* macros for usbss_dev_register_block.usb_cap4 */
  275 +#ifndef __USB_CAP5_MACRO__
  276 +#define __USB_CAP5_MACRO__
  277 +
  278 +/* macros for field EPOUTI_N */
  279 +#endif /* __USB_CAP5_MACRO__ */
  280 +
  281 +
  282 +/* macros for usbss_dev_register_block.usb_cap5 */
  283 +#ifndef __USB_CAP6_MACRO__
  284 +#define __USB_CAP6_MACRO__
  285 +
  286 +/* macros for field VERSION */
  287 +#endif /* __USB_CAP6_MACRO__ */
  288 +
  289 +
  290 +/* macros for usbss_dev_register_block.usb_cap6 */
  291 +#ifndef __USB_CPKT1_MACRO__
  292 +#define __USB_CPKT1_MACRO__
  293 +
  294 +/* macros for field CPKT1 */
  295 +#endif /* __USB_CPKT1_MACRO__ */
  296 +
  297 +
  298 +/* macros for usbss_dev_register_block.usb_cpkt1 */
  299 +#ifndef __USB_CPKT2_MACRO__
  300 +#define __USB_CPKT2_MACRO__
  301 +
  302 +/* macros for field CPKT2 */
  303 +#endif /* __USB_CPKT2_MACRO__ */
  304 +
  305 +
  306 +/* macros for usbss_dev_register_block.usb_cpkt2 */
  307 +#ifndef __USB_CPKT3_MACRO__
  308 +#define __USB_CPKT3_MACRO__
  309 +
  310 +/* macros for field CPKT3 */
  311 +#endif /* __USB_CPKT3_MACRO__ */
  312 +
  313 +
  314 +/* macros for usbss_dev_register_block.usb_cpkt3 */
  315 +#ifndef __CFG_REG1_MACRO__
  316 +#define __CFG_REG1_MACRO__
  317 +
  318 +/* macros for field DEBOUNCER_CNT */
  319 +#endif /* __CFG_REG1_MACRO__ */
  320 +
  321 +
  322 +/* macros for usbss_dev_register_block.cfg_reg1 */
  323 +#ifndef __DBG_LINK1_MACRO__
  324 +#define __DBG_LINK1_MACRO__
  325 +
  326 +/* macros for field LFPS_MIN_DET_U1_EXIT */
  327 +#define DBG_LINK1__LFPS_MIN_GEN_U1_EXIT__WRITE(src) \
  328 + (((uint32_t)(src)\
  329 + << 8) & 0x0000ff00U)
  330 +#define DBG_LINK1__LFPS_MIN_GEN_U1_EXIT_SET__MASK 0x02000000U
  331 +#endif /* __DBG_LINK1_MACRO__ */
  332 +
  333 +
  334 +/* macros for usbss_dev_register_block.dbg_link1 */
  335 +#ifndef __DBG_LINK2_MACRO__
  336 +#define __DBG_LINK2_MACRO__
  337 +
  338 +/* macros for field RXEQTR_AVAL */
  339 +#endif /* __DBG_LINK2_MACRO__ */
  340 +
  341 +
  342 +/* macros for usbss_dev_register_block.dbg_link2 */
  343 +#ifndef __CFG_REG4_MACRO__
  344 +#define __CFG_REG4_MACRO__
  345 +
  346 +/* macros for field RXDETECT_QUIET_TIMEOUT */
  347 +#endif /* __CFG_REG4_MACRO__ */
  348 +
  349 +
  350 +/* macros for usbss_dev_register_block.cfg_reg4 */
  351 +#ifndef __CFG_REG5_MACRO__
  352 +#define __CFG_REG5_MACRO__
  353 +
  354 +/* macros for field U3_HDSK_FAIL_TIMEOUT */
  355 +#endif /* __CFG_REG5_MACRO__ */
  356 +
  357 +
  358 +/* macros for usbss_dev_register_block.cfg_reg5 */
  359 +#ifndef __CFG_REG6_MACRO__
  360 +#define __CFG_REG6_MACRO__
  361 +
  362 +/* macros for field SSINACTIVE_QUIET_TIMEOUT */
  363 +#endif /* __CFG_REG6_MACRO__ */
  364 +
  365 +
  366 +/* macros for usbss_dev_register_block.cfg_reg6 */
  367 +#ifndef __CFG_REG7_MACRO__
  368 +#define __CFG_REG7_MACRO__
  369 +
  370 +/* macros for field POLLING_LFPS_TIMEOUT */
  371 +#endif /* __CFG_REG7_MACRO__ */
  372 +
  373 +
  374 +/* macros for usbss_dev_register_block.cfg_reg7 */
  375 +#ifndef __CFG_REG8_MACRO__
  376 +#define __CFG_REG8_MACRO__
  377 +
  378 +/* macros for field POLLING_ACTIVE_TIMEOUT */
  379 +#endif /* __CFG_REG8_MACRO__ */
  380 +
  381 +
  382 +/* macros for usbss_dev_register_block.cfg_reg8 */
  383 +#ifndef __CFG_REG9_MACRO__
  384 +#define __CFG_REG9_MACRO__
  385 +
  386 +/* macros for field POLLING_IDLE_TIMEOUT */
  387 +#endif /* __CFG_REG9_MACRO__ */
  388 +
  389 +
  390 +/* macros for usbss_dev_register_block.cfg_reg9 */
  391 +#ifndef __CFG_REG10_MACRO__
  392 +#define __CFG_REG10_MACRO__
  393 +
  394 +/* macros for field POLLING_CONF_TIMEOUT */
  395 +#endif /* __CFG_REG10_MACRO__ */
  396 +
  397 +
  398 +/* macros for usbss_dev_register_block.cfg_reg10 */
  399 +#ifndef __CFG_REG11_MACRO__
  400 +#define __CFG_REG11_MACRO__
  401 +
  402 +/* macros for field RECOVERY_ACTIVE_TIMEOUT */
  403 +#endif /* __CFG_REG11_MACRO__ */
  404 +
  405 +
  406 +/* macros for usbss_dev_register_block.cfg_reg11 */
  407 +#ifndef __CFG_REG12_MACRO__
  408 +#define __CFG_REG12_MACRO__
  409 +
  410 +/* macros for field RECOVERY_CONF_TIMEOUT */
  411 +#endif /* __CFG_REG12_MACRO__ */
  412 +
  413 +
  414 +/* macros for usbss_dev_register_block.cfg_reg12 */
  415 +#ifndef __CFG_REG13_MACRO__
  416 +#define __CFG_REG13_MACRO__
  417 +
  418 +/* macros for field RECOVERY_IDLE_TIMEOUT */
  419 +#endif /* __CFG_REG13_MACRO__ */
  420 +
  421 +
  422 +/* macros for usbss_dev_register_block.cfg_reg13 */
  423 +#ifndef __CFG_REG14_MACRO__
  424 +#define __CFG_REG14_MACRO__
  425 +
  426 +/* macros for field HOTRESET_ACTIVE_TIMEOUT */
  427 +#endif /* __CFG_REG14_MACRO__ */
  428 +
  429 +
  430 +/* macros for usbss_dev_register_block.cfg_reg14 */
  431 +#ifndef __CFG_REG15_MACRO__
  432 +#define __CFG_REG15_MACRO__
  433 +
  434 +/* macros for field HOTRESET_EXIT_TIMEOUT */
  435 +#endif /* __CFG_REG15_MACRO__ */
  436 +
  437 +
  438 +/* macros for usbss_dev_register_block.cfg_reg15 */
  439 +#ifndef __CFG_REG16_MACRO__
  440 +#define __CFG_REG16_MACRO__
  441 +
  442 +/* macros for field LFPS_PING_REPEAT */
  443 +#endif /* __CFG_REG16_MACRO__ */
  444 +
  445 +
  446 +/* macros for usbss_dev_register_block.cfg_reg16 */
  447 +#ifndef __CFG_REG17_MACRO__
  448 +#define __CFG_REG17_MACRO__
  449 +
  450 +/* macros for field PENDING_HP_TIMEOUT */
  451 +#endif /* __CFG_REG17_MACRO__ */
  452 +
  453 +
  454 +/* macros for usbss_dev_register_block.cfg_reg17 */
  455 +#ifndef __CFG_REG18_MACRO__
  456 +#define __CFG_REG18_MACRO__
  457 +
  458 +/* macros for field CREDIT_HP_TIMEOUT */
  459 +#endif /* __CFG_REG18_MACRO__ */
  460 +
  461 +
  462 +/* macros for usbss_dev_register_block.cfg_reg18 */
  463 +#ifndef __CFG_REG19_MACRO__
  464 +#define __CFG_REG19_MACRO__
  465 +
  466 +/* macros for field LUP_TIMEOUT */
  467 +#endif /* __CFG_REG19_MACRO__ */
  468 +
  469 +
  470 +/* macros for usbss_dev_register_block.cfg_reg19 */
  471 +#ifndef __CFG_REG20_MACRO__
  472 +#define __CFG_REG20_MACRO__
  473 +
  474 +/* macros for field LDN_TIMEOUT */
  475 +#endif /* __CFG_REG20_MACRO__ */
  476 +
  477 +
  478 +/* macros for usbss_dev_register_block.cfg_reg20 */
  479 +#ifndef __CFG_REG21_MACRO__
  480 +#define __CFG_REG21_MACRO__
  481 +
  482 +/* macros for field PM_LC_TIMEOUT */
  483 +#endif /* __CFG_REG21_MACRO__ */
  484 +
  485 +
  486 +/* macros for usbss_dev_register_block.cfg_reg21 */
  487 +#ifndef __CFG_REG22_MACRO__
  488 +#define __CFG_REG22_MACRO__
  489 +
  490 +/* macros for field PM_ENTRY_TIMEOUT */
  491 +#endif /* __CFG_REG22_MACRO__ */
  492 +
  493 +
  494 +/* macros for usbss_dev_register_block.cfg_reg22 */
  495 +#ifndef __CFG_REG23_MACRO__
  496 +#define __CFG_REG23_MACRO__
  497 +
  498 +/* macros for field UX_EXIT_TIMEOUT */
  499 +#endif /* __CFG_REG23_MACRO__ */
  500 +
  501 +
  502 +/* macros for usbss_dev_register_block.cfg_reg23 */
  503 +#ifndef __CFG_REG24_MACRO__
  504 +#define __CFG_REG24_MACRO__
  505 +
  506 +/* macros for field LFPS_DET_RESET_MIN */
  507 +#endif /* __CFG_REG24_MACRO__ */
  508 +
  509 +
  510 +/* macros for usbss_dev_register_block.cfg_reg24 */
  511 +#ifndef __CFG_REG25_MACRO__
  512 +#define __CFG_REG25_MACRO__
  513 +
  514 +/* macros for field LFPS_DET_RESET_MAX */
  515 +#endif /* __CFG_REG25_MACRO__ */
  516 +
  517 +
  518 +/* macros for usbss_dev_register_block.cfg_reg25 */
  519 +#ifndef __CFG_REG26_MACRO__
  520 +#define __CFG_REG26_MACRO__
  521 +
  522 +/* macros for field LFPS_DET_POLLING_MIN */
  523 +#endif /* __CFG_REG26_MACRO__ */
  524 +
  525 +
  526 +/* macros for usbss_dev_register_block.cfg_reg26 */
  527 +#ifndef __CFG_REG27_MACRO__
  528 +#define __CFG_REG27_MACRO__
  529 +
  530 +/* macros for field LFPS_DET_POLLING_MAX */
  531 +#endif /* __CFG_REG27_MACRO__ */
  532 +
  533 +
  534 +/* macros for usbss_dev_register_block.cfg_reg27 */
  535 +#ifndef __CFG_REG28_MACRO__
  536 +#define __CFG_REG28_MACRO__
  537 +
  538 +/* macros for field LFPS_DET_PING_MIN */
  539 +#endif /* __CFG_REG28_MACRO__ */
  540 +
  541 +
  542 +/* macros for usbss_dev_register_block.cfg_reg28 */
  543 +#ifndef __CFG_REG29_MACRO__
  544 +#define __CFG_REG29_MACRO__
  545 +
  546 +/* macros for field LFPS_DET_PING_MAX */
  547 +#endif /* __CFG_REG29_MACRO__ */
  548 +
  549 +
  550 +/* macros for usbss_dev_register_block.cfg_reg29 */
  551 +#ifndef __CFG_REG30_MACRO__
  552 +#define __CFG_REG30_MACRO__
  553 +
  554 +/* macros for field LFPS_DET_U1EXIT_MIN */
  555 +#endif /* __CFG_REG30_MACRO__ */
  556 +
  557 +
  558 +/* macros for usbss_dev_register_block.cfg_reg30 */
  559 +#ifndef __CFG_REG31_MACRO__
  560 +#define __CFG_REG31_MACRO__
  561 +
  562 +/* macros for field LFPS_DET_U1EXIT_MAX */
  563 +#endif /* __CFG_REG31_MACRO__ */
  564 +
  565 +
  566 +/* macros for usbss_dev_register_block.cfg_reg31 */
  567 +#ifndef __CFG_REG32_MACRO__
  568 +#define __CFG_REG32_MACRO__
  569 +
  570 +/* macros for field LFPS_DET_U2EXIT_MIN */
  571 +#endif /* __CFG_REG32_MACRO__ */
  572 +
  573 +
  574 +/* macros for usbss_dev_register_block.cfg_reg32 */
  575 +#ifndef __CFG_REG33_MACRO__
  576 +#define __CFG_REG33_MACRO__
  577 +
  578 +/* macros for field LFPS_DET_U2EXIT_MAX */
  579 +#endif /* __CFG_REG33_MACRO__ */
  580 +
  581 +
  582 +/* macros for usbss_dev_register_block.cfg_reg33 */
  583 +#ifndef __CFG_REG34_MACRO__
  584 +#define __CFG_REG34_MACRO__
  585 +
  586 +/* macros for field LFPS_DET_U3EXIT_MIN */
  587 +#endif /* __CFG_REG34_MACRO__ */
  588 +
  589 +
  590 +/* macros for usbss_dev_register_block.cfg_reg34 */
  591 +#ifndef __CFG_REG35_MACRO__
  592 +#define __CFG_REG35_MACRO__
  593 +
  594 +/* macros for field LFPS_DET_U3EXIT_MAX */
  595 +#endif /* __CFG_REG35_MACRO__ */
  596 +
  597 +
  598 +/* macros for usbss_dev_register_block.cfg_reg35 */
  599 +#ifndef __CFG_REG36_MACRO__
  600 +#define __CFG_REG36_MACRO__
  601 +
  602 +/* macros for field LFPS_GEN_PING */
  603 +#endif /* __CFG_REG36_MACRO__ */
  604 +
  605 +
  606 +/* macros for usbss_dev_register_block.cfg_reg36 */
  607 +#ifndef __CFG_REG37_MACRO__
  608 +#define __CFG_REG37_MACRO__
  609 +
  610 +/* macros for field LFPS_GEN_POLLING */
  611 +#endif /* __CFG_REG37_MACRO__ */
  612 +
  613 +
  614 +/* macros for usbss_dev_register_block.cfg_reg37 */
  615 +#ifndef __CFG_REG38_MACRO__
  616 +#define __CFG_REG38_MACRO__
  617 +
  618 +/* macros for field LFPS_GEN_U1EXIT */
  619 +#endif /* __CFG_REG38_MACRO__ */
  620 +
  621 +
  622 +/* macros for usbss_dev_register_block.cfg_reg38 */
  623 +#ifndef __CFG_REG39_MACRO__
  624 +#define __CFG_REG39_MACRO__
  625 +
  626 +/* macros for field LFPS_GEN_U3EXIT */
  627 +#endif /* __CFG_REG39_MACRO__ */
  628 +
  629 +
  630 +/* macros for usbss_dev_register_block.cfg_reg39 */
  631 +#ifndef __CFG_REG40_MACRO__
  632 +#define __CFG_REG40_MACRO__
  633 +
  634 +/* macros for field LFPS_MIN_GEN_U1EXIT */
  635 +#endif /* __CFG_REG40_MACRO__ */
  636 +
  637 +
  638 +/* macros for usbss_dev_register_block.cfg_reg40 */
  639 +#ifndef __CFG_REG41_MACRO__
  640 +#define __CFG_REG41_MACRO__
  641 +
  642 +/* macros for field LFPS_MIN_GEN_U2EXIT */
  643 +#endif /* __CFG_REG41_MACRO__ */
  644 +
  645 +
  646 +/* macros for usbss_dev_register_block.cfg_reg41 */
  647 +#ifndef __CFG_REG42_MACRO__
  648 +#define __CFG_REG42_MACRO__
  649 +
  650 +/* macros for field LFPS_POLLING_REPEAT */
  651 +#endif /* __CFG_REG42_MACRO__ */
  652 +
  653 +
  654 +/* macros for usbss_dev_register_block.cfg_reg42 */
  655 +#ifndef __CFG_REG43_MACRO__
  656 +#define __CFG_REG43_MACRO__
  657 +
  658 +/* macros for field LFPS_POLLING_MAX_TREPEAT */
  659 +#endif /* __CFG_REG43_MACRO__ */
  660 +
  661 +
  662 +/* macros for usbss_dev_register_block.cfg_reg43 */
  663 +#ifndef __CFG_REG44_MACRO__
  664 +#define __CFG_REG44_MACRO__
  665 +
  666 +/* macros for field LFPS_POLLING_MIN_TREPEAT */
  667 +#endif /* __CFG_REG44_MACRO__ */
  668 +
  669 +
  670 +/* macros for usbss_dev_register_block.cfg_reg44 */
  671 +#ifndef __CFG_REG45_MACRO__
  672 +#define __CFG_REG45_MACRO__
  673 +
  674 +/* macros for field ITP_WAKEUP_TIMEOUT */
  675 +#endif /* __CFG_REG45_MACRO__ */
  676 +
  677 +
  678 +/* macros for usbss_dev_register_block.cfg_reg45 */
  679 +#ifndef __CFG_REG46_MACRO__
  680 +#define __CFG_REG46_MACRO__
  681 +
  682 +/* macros for field TSEQ_QUANTITY */
  683 +#endif /* __CFG_REG46_MACRO__ */
  684 +
  685 +
  686 +/* macros for usbss_dev_register_block.cfg_reg46 */
  687 +#ifndef __CFG_REG47_MACRO__
  688 +#define __CFG_REG47_MACRO__
  689 +
  690 +/* macros for field ERDY_TIMEOUT_CNT */
  691 +#endif /* __CFG_REG47_MACRO__ */
  692 +
  693 +
  694 +/* macros for usbss_dev_register_block.cfg_reg47 */
  695 +#ifndef __CFG_REG48_MACRO__
  696 +#define __CFG_REG48_MACRO__
  697 +
  698 +/* macros for field TWTRSTFS_J_CNT */
  699 +#endif /* __CFG_REG48_MACRO__ */
  700 +
  701 +
  702 +/* macros for usbss_dev_register_block.cfg_reg48 */
  703 +#ifndef __CFG_REG49_MACRO__
  704 +#define __CFG_REG49_MACRO__
  705 +
  706 +/* macros for field TUCH_CNT */
  707 +#endif /* __CFG_REG49_MACRO__ */
  708 +
  709 +
  710 +/* macros for usbss_dev_register_block.cfg_reg49 */
  711 +#ifndef __CFG_REG50_MACRO__
  712 +#define __CFG_REG50_MACRO__
  713 +
  714 +/* macros for field TWAITCHK_CNT */
  715 +#endif /* __CFG_REG50_MACRO__ */
  716 +
  717 +
  718 +/* macros for usbss_dev_register_block.cfg_reg50 */
  719 +#ifndef __CFG_REG51_MACRO__
  720 +#define __CFG_REG51_MACRO__
  721 +
  722 +/* macros for field TWTFS_CNT */
  723 +#endif /* __CFG_REG51_MACRO__ */
  724 +
  725 +
  726 +/* macros for usbss_dev_register_block.cfg_reg51 */
  727 +#ifndef __CFG_REG52_MACRO__
  728 +#define __CFG_REG52_MACRO__
  729 +
  730 +/* macros for field TWTREV_CNT */
  731 +#endif /* __CFG_REG52_MACRO__ */
  732 +
  733 +
  734 +/* macros for usbss_dev_register_block.cfg_reg52 */
  735 +#ifndef __CFG_REG53_MACRO__
  736 +#define __CFG_REG53_MACRO__
  737 +
  738 +/* macros for field TWTRSTHS_CNT */
  739 +#endif /* __CFG_REG53_MACRO__ */
  740 +
  741 +
  742 +/* macros for usbss_dev_register_block.cfg_reg53 */
  743 +#ifndef __CFG_REG54_MACRO__
  744 +#define __CFG_REG54_MACRO__
  745 +
  746 +/* macros for field TWTRSM_CNT */
  747 +#endif /* __CFG_REG54_MACRO__ */
  748 +
  749 +
  750 +/* macros for usbss_dev_register_block.cfg_reg54 */
  751 +#ifndef __CFG_REG55_MACRO__
  752 +#define __CFG_REG55_MACRO__
  753 +
  754 +/* macros for field TDRSMUP_CNT */
  755 +#endif /* __CFG_REG55_MACRO__ */
  756 +
  757 +
  758 +/* macros for usbss_dev_register_block.cfg_reg55 */
  759 +#ifndef __CFG_REG56_MACRO__
  760 +#define __CFG_REG56_MACRO__
  761 +
  762 +/* macros for field TOUTHS_CNT */
  763 +#endif /* __CFG_REG56_MACRO__ */
  764 +
  765 +
  766 +/* macros for usbss_dev_register_block.cfg_reg56 */
  767 +#ifndef __CFG_REG57_MACRO__
  768 +#define __CFG_REG57_MACRO__
  769 +
  770 +/* macros for field LFPS_DEB_WIDTH */
  771 +#endif /* __CFG_REG57_MACRO__ */
  772 +
  773 +
  774 +/* macros for usbss_dev_register_block.cfg_reg57 */
  775 +#ifndef __CFG_REG58_MACRO__
  776 +#define __CFG_REG58_MACRO__
  777 +
  778 +/* macros for field LFPS_GEN_U2EXIT */
  779 +#endif /* __CFG_REG58_MACRO__ */
  780 +
  781 +
  782 +/* macros for usbss_dev_register_block.cfg_reg58 */
  783 +#ifndef __CFG_REG59_MACRO__
  784 +#define __CFG_REG59_MACRO__
  785 +
  786 +/* macros for field LFPS_MIN_GEN_U3EXIT */
  787 +#endif /* __CFG_REG59_MACRO__ */
  788 +
  789 +
  790 +/* macros for usbss_dev_register_block.cfg_reg59 */
  791 +#ifndef __CFG_REG60_MACRO__
  792 +#define __CFG_REG60_MACRO__
  793 +
  794 +/* macros for field PORT_CONFIG_TIMEOUT */
  795 +#endif /* __CFG_REG60_MACRO__ */
  796 +
  797 +
  798 +/* macros for usbss_dev_register_block.cfg_reg60 */
  799 +#ifndef __CFG_REG61_MACRO__
  800 +#define __CFG_REG61_MACRO__
  801 +
  802 +/* macros for field LFPS_POL_LFPS_TO_RXEQ */
  803 +#endif /* __CFG_REG61_MACRO__ */
  804 +
  805 +
  806 +/* macros for usbss_dev_register_block.cfg_reg61 */
  807 +#ifndef __CFG_REG62_MACRO__
  808 +#define __CFG_REG62_MACRO__
  809 +
  810 +/* macros for field PHY_TX_LATENCY */
  811 +#endif /* __CFG_REG62_MACRO__ */
  812 +
  813 +
  814 +/* macros for usbss_dev_register_block.cfg_reg62 */
  815 +#ifndef __CFG_REG63_MACRO__
  816 +#define __CFG_REG63_MACRO__
  817 +
  818 +/* macros for field U2_INACTIVITY_TMOUT */
  819 +#endif /* __CFG_REG63_MACRO__ */
  820 +
  821 +
  822 +/* macros for usbss_dev_register_block.cfg_reg63 */
  823 +#ifndef __CFG_REG64_MACRO__
  824 +#define __CFG_REG64_MACRO__
  825 +
  826 +/* macros for field TFILTSE0 */
  827 +#endif /* __CFG_REG64_MACRO__ */
  828 +
  829 +
  830 +/* macros for usbss_dev_register_block.cfg_reg64 */
  831 +#ifndef __CFG_REG65_MACRO__
  832 +#define __CFG_REG65_MACRO__
  833 +
  834 +/* macros for field TFILT */
  835 +#endif /* __CFG_REG65_MACRO__ */
  836 +
  837 +
  838 +/* macros for usbss_dev_register_block.cfg_reg65 */
  839 +#ifndef __CFG_REG66_MACRO__
  840 +#define __CFG_REG66_MACRO__
  841 +
  842 +/* macros for field TWTRSTFS_SE0 */
  843 +#endif /* __CFG_REG66_MACRO__ */
  844 +
  845 +
  846 +/* macros for usbss_dev_register_block.cfg_reg66 */
  847 +#ifndef __DMA_AXI_CTRL_MACRO__
  848 +#define __DMA_AXI_CTRL_MACRO__
  849 +
  850 +/* macros for field MAWPROT */
  851 +#endif /* __DMA_AXI_CTRL_MACRO__ */
  852 +
  853 +
  854 +/* macros for usbss_dev_register_block.dma_axi_ctrl */
  855 +#ifndef __DMA_AXI_ID_MACRO__
  856 +#define __DMA_AXI_ID_MACRO__
  857 +
  858 +/* macros for field MAW_ID */
  859 +#endif /* __DMA_AXI_ID_MACRO__ */
  860 +
  861 +
  862 +/* macros for usbss_dev_register_block.dma_axi_id */
  863 +#ifndef __DMA_AXI_CAP_MACRO__
  864 +#define __DMA_AXI_CAP_MACRO__
  865 +
  866 +/* macros for field RESERVED0 */
  867 +#endif /* __DMA_AXI_CAP_MACRO__ */
  868 +
  869 +
  870 +/* macros for usbss_dev_register_block.dma_axi_cap */
  871 +#ifndef __DMA_AXI_CTRL0_MACRO__
  872 +#define __DMA_AXI_CTRL0_MACRO__
  873 +
  874 +/* macros for field B_MAX */
  875 +#endif /* __DMA_AXI_CTRL0_MACRO__ */
  876 +
  877 +
  878 +/* macros for usbss_dev_register_block.dma_axi_ctrl0 */
  879 +#ifndef __DMA_AXI_CTRL1_MACRO__
  880 +#define __DMA_AXI_CTRL1_MACRO__
  881 +
  882 +/* macros for field ROT */
  883 +#endif /* __DMA_AXI_CTRL1_MACRO__ */
  884 +
  885 +
  886 +/* macros for usbss_dev_register_block.dma_axi_ctrl1 */
  887 +#endif /* __REG_USBSS_DEV_ADDR_MAP_MACRO_H__ */
drivers/usb/cdns3/dev-regs-map.h
Diff comments   View file @ db2cc87
  1 +/*
  2 + * Copyright (C) 2016 Cadence Design Systems - http://www.cadence.com
  3 + * Copyright 2018 NXP
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +
  9 +#ifndef __REG_USBSS_DEV_ADDR_MAP_H__
  10 +#define __REG_USBSS_DEV_ADDR_MAP_H__
  11 +
  12 +#include "dev-regs-macro.h"
  13 +
  14 +struct usbss_dev_register_block_type {
  15 + uint32_t usb_conf; /* 0x0 - 0x4 */
  16 + uint32_t usb_sts; /* 0x4 - 0x8 */
  17 + uint32_t usb_cmd; /* 0x8 - 0xc */
  18 + uint32_t usb_iptn; /* 0xc - 0x10 */
  19 + uint32_t usb_lpm; /* 0x10 - 0x14 */
  20 + uint32_t usb_ien; /* 0x14 - 0x18 */
  21 + uint32_t usb_ists; /* 0x18 - 0x1c */
  22 + uint32_t ep_sel; /* 0x1c - 0x20 */
  23 + uint32_t ep_traddr; /* 0x20 - 0x24 */
  24 + uint32_t ep_cfg; /* 0x24 - 0x28 */
  25 + uint32_t ep_cmd; /* 0x28 - 0x2c */
  26 + uint32_t ep_sts; /* 0x2c - 0x30 */
  27 + uint32_t ep_sts_sid; /* 0x30 - 0x34 */
  28 + uint32_t ep_sts_en; /* 0x34 - 0x38 */
  29 + uint32_t drbl; /* 0x38 - 0x3c */
  30 + uint32_t ep_ien; /* 0x3c - 0x40 */
  31 + uint32_t ep_ists; /* 0x40 - 0x44 */
  32 + uint32_t usb_pwr; /* 0x44 - 0x48 */
  33 + uint32_t usb_conf2; /* 0x48 - 0x4c */
  34 + uint32_t usb_cap1; /* 0x4c - 0x50 */
  35 + uint32_t usb_cap2; /* 0x50 - 0x54 */
  36 + uint32_t usb_cap3; /* 0x54 - 0x58 */
  37 + uint32_t usb_cap4; /* 0x58 - 0x5c */
  38 + uint32_t usb_cap5; /* 0x5c - 0x60 */
  39 + uint32_t PAD2_73; /* 0x60 - 0x64 */
  40 + uint32_t usb_cpkt1; /* 0x64 - 0x68 */
  41 + uint32_t usb_cpkt2; /* 0x68 - 0x6c */
  42 + uint32_t usb_cpkt3; /* 0x6c - 0x70 */
  43 + char pad__0[0x90]; /* 0x70 - 0x100 */
  44 + uint32_t PAD2_78; /* 0x100 - 0x104 */
  45 + uint32_t dbg_link1; /* 0x104 - 0x108 */
  46 + uint32_t PAD2_80; /* 0x108 - 0x10c */
  47 + uint32_t PAD2_81; /* 0x10c - 0x110 */
  48 + uint32_t PAD2_82; /* 0x110 - 0x114 */
  49 + uint32_t PAD2_83; /* 0x114 - 0x118 */
  50 + uint32_t PAD2_84; /* 0x118 - 0x11c */
  51 + uint32_t PAD2_85; /* 0x11c - 0x120 */
  52 + uint32_t PAD2_86; /* 0x120 - 0x124 */
  53 + uint32_t PAD2_87; /* 0x124 - 0x128 */
  54 + uint32_t PAD2_88; /* 0x128 - 0x12c */
  55 + uint32_t PAD2_89; /* 0x12c - 0x130 */
  56 + uint32_t PAD2_90; /* 0x130 - 0x134 */
  57 + uint32_t PAD2_91; /* 0x134 - 0x138 */
  58 + uint32_t PAD2_92; /* 0x138 - 0x13c */
  59 + uint32_t PAD2_93; /* 0x13c - 0x140 */
  60 + uint32_t PAD2_94; /* 0x140 - 0x144 */
  61 + uint32_t PAD2_95; /* 0x144 - 0x148 */
  62 + uint32_t PAD2_96; /* 0x148 - 0x14c */
  63 + uint32_t PAD2_97; /* 0x14c - 0x150 */
  64 + uint32_t PAD2_98; /* 0x150 - 0x154 */
  65 + uint32_t PAD2_99; /* 0x154 - 0x158 */
  66 + uint32_t PAD2_100; /* 0x158 - 0x15c */
  67 + uint32_t PAD2_101; /* 0x15c - 0x160 */
  68 + uint32_t PAD2_102; /* 0x160 - 0x164 */
  69 + uint32_t PAD2_103; /* 0x164 - 0x168 */
  70 + uint32_t PAD2_104; /* 0x168 - 0x16c */
  71 + uint32_t PAD2_105; /* 0x16c - 0x170 */
  72 + uint32_t PAD2_106; /* 0x170 - 0x174 */
  73 + uint32_t PAD2_107; /* 0x174 - 0x178 */
  74 + uint32_t PAD2_108; /* 0x178 - 0x17c */
  75 + uint32_t PAD2_109; /* 0x17c - 0x180 */
  76 + uint32_t PAD2_110; /* 0x180 - 0x184 */
  77 + uint32_t PAD2_111; /* 0x184 - 0x188 */
  78 + uint32_t PAD2_112; /* 0x188 - 0x18c */
  79 + char pad__1[0x20]; /* 0x18c - 0x1ac */
  80 + uint32_t PAD2_114; /* 0x1ac - 0x1b0 */
  81 + uint32_t PAD2_115; /* 0x1b0 - 0x1b4 */
  82 + uint32_t PAD2_116; /* 0x1b4 - 0x1b8 */
  83 + uint32_t PAD2_117; /* 0x1b8 - 0x1bc */
  84 + uint32_t PAD2_118; /* 0x1bc - 0x1c0 */
  85 + uint32_t PAD2_119; /* 0x1c0 - 0x1c4 */
  86 + uint32_t PAD2_120; /* 0x1c4 - 0x1c8 */
  87 + uint32_t PAD2_121; /* 0x1c8 - 0x1cc */
  88 + uint32_t PAD2_122; /* 0x1cc - 0x1d0 */
  89 + uint32_t PAD2_123; /* 0x1d0 - 0x1d4 */
  90 + uint32_t PAD2_124; /* 0x1d4 - 0x1d8 */
  91 + uint32_t PAD2_125; /* 0x1d8 - 0x1dc */
  92 + uint32_t PAD2_126; /* 0x1dc - 0x1e0 */
  93 + uint32_t PAD2_127; /* 0x1e0 - 0x1e4 */
  94 + uint32_t PAD2_128; /* 0x1e4 - 0x1e8 */
  95 + uint32_t PAD2_129; /* 0x1e8 - 0x1ec */
  96 + uint32_t PAD2_130; /* 0x1ec - 0x1f0 */
  97 + uint32_t PAD2_131; /* 0x1f0 - 0x1f4 */
  98 + uint32_t PAD2_132; /* 0x1f4 - 0x1f8 */
  99 + uint32_t PAD2_133; /* 0x1f8 - 0x1fc */
  100 + uint32_t PAD2_134; /* 0x1fc - 0x200 */
  101 + uint32_t PAD2_135; /* 0x200 - 0x204 */
  102 + uint32_t PAD2_136; /* 0x204 - 0x208 */
  103 + uint32_t PAD2_137; /* 0x208 - 0x20c */
  104 + uint32_t PAD2_138; /* 0x20c - 0x210 */
  105 + uint32_t PAD2_139; /* 0x210 - 0x214 */
  106 + uint32_t PAD2_140; /* 0x214 - 0x218 */
  107 + uint32_t PAD2_141; /* 0x218 - 0x21c */
  108 + uint32_t PAD2_142; /* 0x21c - 0x220 */
  109 + uint32_t PAD2_143; /* 0x220 - 0x224 */
  110 + uint32_t PAD2_144; /* 0x224 - 0x228 */
  111 + char pad__2[0xd8]; /* 0x228 - 0x300 */
  112 + uint32_t dma_axi_ctrl; /* 0x300 - 0x304 */
  113 + uint32_t PAD2_147; /* 0x304 - 0x308 */
  114 + uint32_t PAD2_148; /* 0x308 - 0x30c */
  115 + uint32_t PAD2_149; /* 0x30c - 0x310 */
  116 + uint32_t PAD2_150; /* 0x310 - 0x314 */
  117 +};
  118 +
  119 +#endif /* __REG_USBSS_DEV_ADDR_MAP_H__ */
drivers/usb/cdns3/gadget-export.h
Diff comments   View file @ db2cc87
  1 +/*
  2 + * Copyright 2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __CDNS3_GADGET_EXPORT_H
  8 +#define __CDNS3_GADGET_EXPORT_H
  9 +
  10 +#ifdef CONFIG_USB_CDNS3_GADGET
  11 +
  12 +int cdns3_gadget_init(struct cdns3 *cdns);
  13 +void cdns3_gadget_remove(struct cdns3 *cdns);
  14 +#else
  15 +
  16 +static inline int cdns3_gadget_init(struct cdns3 *cdns)
  17 +{
  18 + return -ENXIO;
  19 +}
  20 +
  21 +static inline void cdns3_gadget_remove(struct cdns3 *cdns)
  22 +{
  23 +}
  24 +
  25 +#endif
  26 +
  27 +#endif /* __CDNS3_GADGET_EXPORT_H */
drivers/usb/cdns3/gadget.c
Diff comments   View file @ db2cc87
Changes suppressed. Click to show
  1 +/*
  2 + * Copyright (C) 2016 Cadence Design Systems - https://www.cadence.com/
  3 + * Copyright 2018 NXP
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0
  6 + */
  7 +#include <common.h>
  8 +#include <malloc.h>
  9 +#include <asm/dma-mapping.h>
  10 +#include <asm/io.h>
  11 +#include <usb/lin_gadget_compat.h>
  12 +#include <linux/bug.h>
  13 +#include <linux/list.h>
  14 +#include <linux/compat.h>
  15 +
  16 +#include <linux/usb/ch9.h>
  17 +#include <linux/usb/gadget.h>
  18 +#include <linux/usb/composite.h>
  19 +
  20 +#include "linux-compat.h"
  21 +#include "core.h"
  22 +#include "gadget-export.h"
  23 +#include "gadget.h"
  24 +#include "io.h"
  25 +
  26 +/*-------------------------------------------------------------------------*/
  27 +/* Function declarations */
  28 +
  29 +static void select_ep(struct usb_ss_dev *usb_ss, u32 ep);
  30 +static int usb_ss_allocate_trb_pool(struct usb_ss_endpoint *usb_ss_ep);
  31 +static void cdns_ep_stall_flush(struct usb_ss_endpoint *usb_ss_ep);
  32 +static void cdns_ep0_config(struct usb_ss_dev *usb_ss);
  33 +static void cdns_gadget_unconfig(struct usb_ss_dev *usb_ss);
  34 +static void cdns_ep0_run_transfer(struct usb_ss_dev *usb_ss,
  35 + dma_addr_t dma_addr, unsigned int length, int erdy);
  36 +static int cdns_ep_run_transfer(struct usb_ss_endpoint *usb_ss_ep);
  37 +static int cdns_get_setup_ret(struct usb_ss_dev *usb_ss,
  38 + struct usb_ctrlrequest *ctrl_req);
  39 +static int cdns_req_ep0_set_address(struct usb_ss_dev *usb_ss,
  40 + struct usb_ctrlrequest *ctrl_req);
  41 +static int cdns_req_ep0_get_status(struct usb_ss_dev *usb_ss,
  42 + struct usb_ctrlrequest *ctrl_req);
  43 +static int cdns_req_ep0_handle_feature(struct usb_ss_dev *usb_ss,
  44 + struct usb_ctrlrequest *ctrl_req, int set);
  45 +static int cdns_req_ep0_set_sel(struct usb_ss_dev *usb_ss,
  46 + struct usb_ctrlrequest *ctrl_req);
  47 +static int cdns_req_ep0_set_isoch_delay(struct usb_ss_dev *usb_ss,
  48 + struct usb_ctrlrequest *ctrl_req);
  49 +static int cdns_req_ep0_set_configuration(struct usb_ss_dev *usb_ss,
  50 + struct usb_ctrlrequest *ctrl_req);
  51 +static int cdns_ep0_standard_request(struct usb_ss_dev *usb_ss,
  52 + struct usb_ctrlrequest *ctrl_req);
  53 +static void cdns_ep0_setup_phase(struct usb_ss_dev *usb_ss);
  54 +static int cdns_check_ep_interrupt_proceed(struct usb_ss_endpoint *usb_ss_ep);
  55 +static void cdns_check_ep0_interrupt_proceed(struct usb_ss_dev *usb_ss,
  56 + int dir);
  57 +static void cdns_check_usb_interrupt_proceed(struct usb_ss_dev *usb_ss,
  58 + u32 usb_ists);
  59 +#ifdef CDNS_THREADED_IRQ_HANDLING
  60 +static irqreturn_t cdns_irq_handler(int irq, void *_usb_ss);
  61 +#endif
  62 +static int usb_ss_gadget_ep0_enable(struct usb_ep *ep,
  63 + const struct usb_endpoint_descriptor *desc);
  64 +static int usb_ss_gadget_ep0_disable(struct usb_ep *ep);
  65 +static int usb_ss_gadget_ep0_set_halt(struct usb_ep *ep, int value);
  66 +static int usb_ss_gadget_ep0_queue(struct usb_ep *ep,
  67 + struct usb_request *request, gfp_t gfp_flags);
  68 +static int usb_ss_gadget_ep_enable(struct usb_ep *ep,
  69 + const struct usb_endpoint_descriptor *desc);
  70 +static int usb_ss_gadget_ep_disable(struct usb_ep *ep);
  71 +static struct usb_request *usb_ss_gadget_ep_alloc_request(struct usb_ep *ep,
  72 + gfp_t gfp_flags);
  73 +static void usb_ss_gadget_ep_free_request(struct usb_ep *ep,
  74 + struct usb_request *request);
  75 +static int usb_ss_gadget_ep_queue(struct usb_ep *ep,
  76 + struct usb_request *request, gfp_t gfp_flags);
  77 +static int usb_ss_gadget_ep_dequeue(struct usb_ep *ep,
  78 + struct usb_request *request);
  79 +static int usb_ss_gadget_ep_set_halt(struct usb_ep *ep, int value);
  80 +static int usb_ss_gadget_ep_set_wedge(struct usb_ep *ep);
  81 +static int usb_ss_gadget_get_frame(struct usb_gadget *gadget);
  82 +static int usb_ss_gadget_wakeup(struct usb_gadget *gadget);
  83 +static int usb_ss_gadget_set_selfpowered(struct usb_gadget *gadget,
  84 + int is_selfpowered);
  85 +static int usb_ss_gadget_pullup(struct usb_gadget *gadget, int is_on);
  86 +static int usb_ss_gadget_udc_start(struct usb_gadget *gadget,
  87 + struct usb_gadget_driver *driver);
  88 +static int usb_ss_gadget_udc_stop(struct usb_gadget *gadget);
  89 +static int usb_ss_init_ep(struct usb_ss_dev *usb_ss);
  90 +static int usb_ss_init_ep0(struct usb_ss_dev *usb_ss);
  91 +static void __cdns3_gadget_start(struct usb_ss_dev *usb_ss);
  92 +static void cdns_prepare_setup_packet(struct usb_ss_dev *usb_ss);
  93 +static void cdns_ep_config(struct usb_ss_endpoint *usb_ss_ep);
  94 +
  95 +static const char *const speed_names[] = {
  96 + [USB_SPEED_UNKNOWN] = "UNKNOWN",
  97 + [USB_SPEED_LOW] = "low-speed",
  98 + [USB_SPEED_FULL] = "full-speed",
  99 + [USB_SPEED_HIGH] = "high-speed",
  100 + [USB_SPEED_WIRELESS] = "wireless",
  101 + [USB_SPEED_SUPER] = "super-speed",
  102 +};
  103 +
  104 +const char *usb_speed_string(enum usb_device_speed speed)
  105 +{
  106 + if (speed < 0 || speed >= ARRAY_SIZE(speed_names))
  107 + speed = USB_SPEED_UNKNOWN;
  108 + return speed_names[speed];
  109 +}
  110 +
  111 +static struct usb_endpoint_descriptor cdns3_gadget_ep0_desc = {
  112 + .bLength = USB_DT_ENDPOINT_SIZE,
  113 + .bDescriptorType = USB_DT_ENDPOINT,
  114 + .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  115 +};
  116 +
  117 +static u32 gadget_readl(struct usb_ss_dev *usb_ss, uint32_t __iomem *reg)
  118 +{
  119 + return cdns_readl(reg);
  120 +}
  121 +
  122 +static void gadget_writel(struct usb_ss_dev *usb_ss,
  123 + uint32_t __iomem *reg, u32 value)
  124 +{
  125 + cdns_writel(reg, value);
  126 +}
  127 +
  128 +/**
  129 + * next_request - returns next request from list
  130 + * @list: list containing requests
  131 + *
  132 + * Returns request or NULL if no requests in list
  133 + */
  134 +static struct usb_request *next_request(struct list_head *list)
  135 +{
  136 + if (list_empty(list))
  137 + return NULL;
  138 + return list_first_entry(list, struct usb_request, list);
  139 +}
  140 +
  141 +/**
  142 + * select_ep - selects endpoint
  143 + * @usb_ss: extended gadget object
  144 + * @ep: endpoint address
  145 + */
  146 +static void select_ep(struct usb_ss_dev *usb_ss, u32 ep)
  147 +{
  148 + if (!usb_ss || !usb_ss->regs) {
  149 + dev_err(&usb_ss->dev, "Failed to select endpoint!\n");
  150 + return;
  151 + }
  152 +
  153 + gadget_writel(usb_ss, &usb_ss->regs->ep_sel, ep);
  154 +}
  155 +
  156 +/**
  157 + * usb_ss_allocate_trb_pool - Allocates TRB's pool for selected endpoint
  158 + * @usb_ss_ep: extended endpoint object
  159 + *
  160 + * Function will return 0 on success or -ENOMEM on allocation error
  161 + */
  162 +static int usb_ss_allocate_trb_pool(struct usb_ss_endpoint *usb_ss_ep)
  163 +{
  164 + if (usb_ss_ep->trb_pool)
  165 + return 0;
  166 +
  167 + usb_ss_ep->trb_pool = dma_alloc_coherent(
  168 + sizeof(struct usb_ss_trb) * USB_SS_TRBS_NUM,
  169 + (unsigned long *)&usb_ss_ep->trb_pool_dma);
  170 +
  171 + if (!usb_ss_ep->trb_pool) {
  172 + dev_err(&(usb_ss_ep->usb_ss->dev),
  173 + "Failed to allocate TRB pool for endpoint %s\n",
  174 + usb_ss_ep->name);
  175 + return -ENOMEM;
  176 + }
  177 +
  178 + memset(usb_ss_ep->trb_pool, 0, sizeof(struct usb_ss_trb) * USB_SS_TRBS_NUM);
  179 +
  180 + return 0;
  181 +}
  182 +
  183 +/**
  184 + * cdns_ep_stall_flush - Stalls and flushes selected endpoint
  185 + * @usb_ss_ep: extended endpoint object
  186 + *
  187 + * Endpoint must be selected before call to this function
  188 + */
  189 +static void cdns_ep_stall_flush(struct usb_ss_endpoint *usb_ss_ep)
  190 +{
  191 + struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss;
  192 +
  193 + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd,
  194 + EP_CMD__DFLUSH__MASK | EP_CMD__ERDY__MASK |
  195 + EP_CMD__SSTALL__MASK);
  196 +
  197 + /* wait for DFLUSH cleared */
  198 + while (gadget_readl(usb_ss,
  199 + &usb_ss->regs->ep_cmd) & EP_CMD__DFLUSH__MASK)
  200 + ;
  201 +
  202 + usb_ss_ep->stalled_flag = 1;
  203 +}
  204 +
  205 +/**
  206 + * cdns_ep0_config - Configures default endpoint
  207 + * @usb_ss: extended gadget object
  208 + *
  209 + * Functions sets parameters: maximal packet size and enables interrupts
  210 + */
  211 +static void cdns_ep0_config(struct usb_ss_dev *usb_ss)
  212 +{
  213 + u32 max_packet_size = 0;
  214 +
  215 + switch (usb_ss->gadget.speed) {
  216 + case USB_SPEED_UNKNOWN:
  217 + max_packet_size = ENDPOINT_MAX_PACKET_SIZE_0;
  218 + usb_ss->gadget.ep0->maxpacket = ENDPOINT_MAX_PACKET_SIZE_0;
  219 + cdns3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(0);
  220 + break;
  221 +
  222 + case USB_SPEED_LOW:
  223 + max_packet_size = ENDPOINT_MAX_PACKET_SIZE_8;
  224 + usb_ss->gadget.ep0->maxpacket = ENDPOINT_MAX_PACKET_SIZE_8;
  225 + cdns3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
  226 + break;
  227 +
  228 + case USB_SPEED_FULL:
  229 + max_packet_size = ENDPOINT_MAX_PACKET_SIZE_64;
  230 + usb_ss->gadget.ep0->maxpacket = ENDPOINT_MAX_PACKET_SIZE_64;
  231 + cdns3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
  232 + break;
  233 +
  234 + case USB_SPEED_HIGH:
  235 + max_packet_size = ENDPOINT_MAX_PACKET_SIZE_64;
  236 + usb_ss->gadget.ep0->maxpacket = ENDPOINT_MAX_PACKET_SIZE_64;
  237 + cdns3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
  238 + break;
  239 +
  240 + case USB_SPEED_WIRELESS:
  241 + max_packet_size = ENDPOINT_MAX_PACKET_SIZE_64;
  242 + usb_ss->gadget.ep0->maxpacket = ENDPOINT_MAX_PACKET_SIZE_64;
  243 + cdns3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
  244 + break;
  245 +
  246 + case USB_SPEED_SUPER:
  247 + max_packet_size = ENDPOINT_MAX_PACKET_SIZE_512;
  248 + usb_ss->gadget.ep0->maxpacket = ENDPOINT_MAX_PACKET_SIZE_512;
  249 + cdns3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
  250 + break;
  251 + }
  252 +
  253 + /* init ep out */
  254 + select_ep(usb_ss, USB_DIR_OUT);
  255 +
  256 + gadget_writel(usb_ss, &usb_ss->regs->ep_cfg,
  257 + EP_CFG__ENABLE__MASK |
  258 + EP_CFG__MAXPKTSIZE__WRITE(max_packet_size));
  259 + gadget_writel(usb_ss, &usb_ss->regs->ep_sts_en,
  260 + EP_STS_EN__SETUPEN__MASK |
  261 + EP_STS_EN__DESCMISEN__MASK |
  262 + EP_STS_EN__TRBERREN__MASK);
  263 +
  264 + /* init ep in */
  265 + select_ep(usb_ss, USB_DIR_IN);
  266 +
  267 + gadget_writel(usb_ss, &usb_ss->regs->ep_cfg,
  268 + EP_CFG__ENABLE__MASK |
  269 + EP_CFG__MAXPKTSIZE__WRITE(max_packet_size));
  270 + gadget_writel(usb_ss, &usb_ss->regs->ep_sts_en,
  271 + EP_STS_EN__SETUPEN__MASK |
  272 + EP_STS_EN__TRBERREN__MASK);
  273 +
  274 + cdns_prepare_setup_packet(usb_ss);
  275 +}
  276 +
  277 +/**
  278 + * cdns_gadget_unconfig - Unconfigures device controller
  279 + * @usb_ss: extended gadget object
  280 + */
  281 +static void cdns_gadget_unconfig(struct usb_ss_dev *usb_ss)
  282 +{
  283 + /* RESET CONFIGURATION */
  284 + gadget_writel(usb_ss, &usb_ss->regs->usb_conf,
  285 + USB_CONF__CFGRST__MASK);
  286 +
  287 + usb_ss->hw_configured_flag = 0;
  288 +}
  289 +
  290 +/**
  291 + * cdns_ep0_run_transfer - Do transfer on default endpoint hardware
  292 + * @usb_ss: extended gadget object
  293 + * @dma_addr: physical address where data is/will be stored
  294 + * @length: data length
  295 + * @erdy: set it to 1 when ERDY packet should be sent -
  296 + * exit from flow control state
  297 + */
  298 +static void cdns_ep0_run_transfer(struct usb_ss_dev *usb_ss,
  299 + dma_addr_t dma_addr, unsigned int length, int erdy)
  300 +{
  301 + usb_ss->trb_ep0[0] = TRB_SET_DATA_BUFFER_POINTER(dma_addr);
  302 + usb_ss->trb_ep0[1] = TRB_SET_TRANSFER_LENGTH((u32)length);
  303 + usb_ss->trb_ep0[2] = TRB_SET_CYCLE_BIT |
  304 + TRB_SET_INT_ON_COMPLETION | TRB_TYPE_NORMAL;
  305 +
  306 + cdns_flush_cache((uintptr_t)usb_ss->trb_ep0, 20);
  307 + cdns_flush_cache((uintptr_t)dma_addr, length);
  308 +
  309 + dev_dbg(&usb_ss->dev, "DRBL(%02X)\n",
  310 + usb_ss->ep0_data_dir ? USB_DIR_IN : USB_DIR_OUT);
  311 +
  312 + select_ep(usb_ss, usb_ss->ep0_data_dir
  313 + ? USB_DIR_IN : USB_DIR_OUT);
  314 +
  315 + gadget_writel(usb_ss, &usb_ss->regs->ep_traddr,
  316 + EP_TRADDR__TRADDR__WRITE(usb_ss->trb_ep0_dma));
  317 + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd,
  318 + EP_CMD__DRDY__MASK); /* drbl */
  319 +
  320 + if (erdy)
  321 + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd,
  322 + EP_CMD__ERDY__MASK);
  323 +}
  324 +
  325 +/**
  326 + * cdns_ep_run_transfer - Do transfer on no-default endpoint hardware
  327 + * @usb_ss_ep: extended endpoint object
  328 + *
  329 + * Returns zero on success or negative value on failure
  330 + */
  331 +static int cdns_ep_run_transfer(struct usb_ss_endpoint *usb_ss_ep)
  332 +{
  333 + dma_addr_t trb_dma;
  334 + struct usb_request *request = next_request(&usb_ss_ep->request_list);
  335 + struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss;
  336 + struct usb_ss_trb *trb;
  337 +
  338 + if (request == NULL)
  339 + return -EINVAL;
  340 +
  341 + dev_dbg(&usb_ss->dev, "DRBL(%02X)\n",
  342 + usb_ss_ep->endpoint.desc->bEndpointAddress);
  343 +
  344 + usb_ss_ep->hw_pending_flag = 1;
  345 + trb_dma = request->dma;
  346 +
  347 + /* must allocate buffer aligned to 8 */
  348 + if (request->dma % ADDR_MODULO_8) {
  349 + memcpy(usb_ss_ep->cpu_addr, request->buf, request->length);
  350 + trb_dma = usb_ss_ep->dma_addr;
  351 + }
  352 +
  353 + cdns_flush_cache((uintptr_t)trb_dma, request->length);
  354 +
  355 + trb = usb_ss_ep->trb_pool;
  356 +
  357 + /* fill TRB */
  358 + trb->offset0 = trb_dma;
  359 +
  360 + trb->offset4 = TRB_SET_BURST_LENGTH(16) |
  361 + TRB_SET_TRANSFER_LENGTH(request->length);
  362 +
  363 + trb->offset8 = TRB_SET_CYCLE_BIT
  364 + | TRB_SET_INT_ON_COMPLETION
  365 + | TRB_SET_INT_ON_SHORT_PACKET
  366 + | TRB_TYPE_NORMAL;
  367 +
  368 + cdns_flush_cache((uintptr_t)trb, sizeof(struct usb_ss_trb));
  369 +
  370 + /* arm transfer on selected endpoint */
  371 + select_ep(usb_ss_ep->usb_ss,
  372 + usb_ss_ep->endpoint.desc->bEndpointAddress);
  373 +
  374 + gadget_writel(usb_ss, &usb_ss->regs->ep_traddr,
  375 + EP_TRADDR__TRADDR__WRITE(usb_ss_ep->trb_pool_dma));
  376 + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd,
  377 + EP_CMD__DRDY__MASK); /* DRDY */
  378 + return 0;
  379 +}
  380 +
  381 +/**
  382 + * cdns_get_setup_ret - Returns status of handling setup packet
  383 + * Setup is handled by gadget driver
  384 + * @usb_ss: extended gadget object
  385 + * @ctrl_req: pointer to received setup packet
  386 + *
  387 + * Returns zero on success or negative value on failure
  388 + */
  389 +static int cdns_get_setup_ret(struct usb_ss_dev *usb_ss,
  390 + struct usb_ctrlrequest *ctrl_req)
  391 +{
  392 + int ret;
  393 +
  394 + spin_unlock(&usb_ss->lock);
  395 + usb_ss->setup_pending = 1;
  396 + ret = usb_ss->gadget_driver->setup(&usb_ss->gadget, ctrl_req);
  397 + usb_ss->setup_pending = 0;
  398 + spin_lock(&usb_ss->lock);
  399 + return ret;
  400 +}
  401 +
  402 +static void cdns_prepare_setup_packet(struct usb_ss_dev *usb_ss)
  403 +{
  404 + usb_ss->ep0_data_dir = 0;
  405 + cdns_ep0_run_transfer(usb_ss, usb_ss->setup_dma, 8, 0);
  406 +}
  407 +
  408 +/**
  409 + * cdns_req_ep0_set_address - Handling of SET_ADDRESS standard USB request
  410 + * @usb_ss: extended gadget object
  411 + * @ctrl_req: pointer to received setup packet
  412 + *
  413 + * Returns 0 if success, error code on error
  414 + */
  415 +static int cdns_req_ep0_set_address(struct usb_ss_dev *usb_ss,
  416 + struct usb_ctrlrequest *ctrl_req)
  417 +{
  418 + enum usb_device_state device_state = usb_ss->gadget.state;
  419 + u32 reg;
  420 + u32 addr;
  421 +
  422 + addr = le16_to_cpu(ctrl_req->wValue);
  423 +
  424 + if (addr > DEVICE_ADDRESS_MAX) {
  425 + dev_err(&usb_ss->dev,
  426 + "Device address (%d) cannot be greater than %d\n",
  427 + addr, DEVICE_ADDRESS_MAX);
  428 + return -EINVAL;
  429 + }
  430 +
  431 + if (device_state == USB_STATE_CONFIGURED) {
  432 + dev_err(&usb_ss->dev, "USB device already configured\n");
  433 + return -EINVAL;
  434 + }
  435 +
  436 + reg = gadget_readl(usb_ss, &usb_ss->regs->usb_cmd);
  437 +
  438 + gadget_writel(usb_ss, &usb_ss->regs->usb_cmd, reg
  439 + | USB_CMD__FADDR__WRITE(addr)
  440 + | USB_CMD__SET_ADDR__MASK);
  441 +
  442 + usb_gadget_set_state(&usb_ss->gadget,
  443 + (addr ? USB_STATE_ADDRESS : USB_STATE_DEFAULT));
  444 +
  445 + cdns_prepare_setup_packet(usb_ss);
  446 +
  447 + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd,
  448 + EP_CMD__ERDY__MASK | EP_CMD__REQ_CMPL__MASK);
  449 + return 0;
  450 +}
  451 +
  452 +/**
  453 + * cdns_req_ep0_get_status - Handling of GET_STATUS standard USB request
  454 + * @usb_ss: extended gadget object
  455 + * @ctrl_req: pointer to received setup packet
  456 + *
  457 + * Returns 0 if success, error code on error
  458 + */
  459 +static int cdns_req_ep0_get_status(struct usb_ss_dev *usb_ss,
  460 + struct usb_ctrlrequest *ctrl_req)
  461 +{
  462 + u16 usb_status = 0;
  463 + unsigned int length = 2;
  464 + u32 recip = ctrl_req->bRequestType & USB_RECIP_MASK;
  465 + u32 reg;
  466 +
  467 + switch (recip) {
  468 + case USB_RECIP_DEVICE:
  469 + reg = gadget_readl(usb_ss, &usb_ss->regs->usb_sts);
  470 +
  471 + if (reg & USB_STS__U1ENS__MASK)
  472 + usb_status |= 1uL << USB_DEV_STAT_U1_ENABLED;
  473 +
  474 + if (reg & USB_STS__U2ENS__MASK)
  475 + usb_status |= 1uL << USB_DEV_STAT_U2_ENABLED;
  476 +
  477 + if (usb_ss->wake_up_flag)
  478 + usb_status |= 1uL << USB_DEVICE_REMOTE_WAKEUP;
  479 +
  480 + /* self powered */
  481 + usb_status |= 1uL << USB_DEVICE_SELF_POWERED;
  482 + break;
  483 +
  484 + case USB_RECIP_INTERFACE:
  485 + return cdns_get_setup_ret(usb_ss, ctrl_req);
  486 +
  487 + case USB_RECIP_ENDPOINT:
  488 + /* check if endpoint is stalled */
  489 + select_ep(usb_ss, ctrl_req->wIndex);
  490 + if (gadget_readl(usb_ss, &usb_ss->regs->ep_sts)
  491 + & EP_STS__STALL__MASK)
  492 + usb_status = 1;
  493 + break;
  494 +
  495 + default:
  496 + return -EINVAL;
  497 + }
  498 +
  499 + *(u16 *)usb_ss->setup = cpu_to_le16(usb_status);
  500 +
  501 + usb_ss->actual_ep0_request = NULL;
  502 + cdns_ep0_run_transfer(usb_ss, usb_ss->setup_dma, length, 1);
  503 + return 0;
  504 +}
  505 +
  506 +/**
  507 + * cdns_req_ep0_handle_feature -
  508 + * Handling of GET/SET_FEATURE standard USB request
  509 + *
  510 + * @usb_ss: extended gadget object
  511 + * @ctrl_req: pointer to received setup packet
  512 + * @set: must be set to 1 for SET_FEATURE request
  513 + *
  514 + * Returns 0 if success, error code on error
  515 + */
  516 +static int cdns_req_ep0_handle_feature(struct usb_ss_dev *usb_ss,
  517 + struct usb_ctrlrequest *ctrl_req, int set)
  518 +{
  519 + u32 recip = ctrl_req->bRequestType & USB_RECIP_MASK;
  520 + struct usb_ss_endpoint *usb_ss_ep;
  521 + u32 reg;
  522 + u8 tmode = 0;
  523 +
  524 + switch (recip) {
  525 + case USB_RECIP_DEVICE:
  526 +
  527 + switch (ctrl_req->wValue) {
  528 + case USB_DEVICE_U1_ENABLE:
  529 + if (usb_ss->gadget.state != USB_STATE_CONFIGURED)
  530 + return -EINVAL;
  531 + if (usb_ss->gadget.speed != USB_SPEED_SUPER)
  532 + return -EINVAL;
  533 +
  534 + reg = gadget_readl(usb_ss, &usb_ss->regs->usb_conf);
  535 + if (set)
  536 + /* set U1EN */
  537 + reg |= USB_CONF__U1EN__MASK;
  538 + else
  539 + /* set U1 disable */
  540 + reg |= USB_CONF__U1DS__MASK;
  541 + gadget_writel(usb_ss, &usb_ss->regs->usb_conf, reg);
  542 + break;
  543 +
  544 + case USB_DEVICE_U2_ENABLE:
  545 + if (usb_ss->gadget.state != USB_STATE_CONFIGURED)
  546 + return -EINVAL;
  547 + if (usb_ss->gadget.speed != USB_SPEED_SUPER)
  548 + return -EINVAL;
  549 +
  550 + reg = gadget_readl(usb_ss, &usb_ss->regs->usb_conf);
  551 + if (set)
  552 + /* set U2EN */
  553 + reg |= USB_CONF__U2EN__MASK;
  554 + else
  555 + /* set U2 disable */
  556 + reg |= USB_CONF__U2DS__MASK;
  557 + gadget_writel(usb_ss, &usb_ss->regs->usb_conf, reg);
  558 + break;
  559 +
  560 + case USB_DEVICE_A_ALT_HNP_SUPPORT:
  561 + break;
  562 +
  563 + case USB_DEVICE_A_HNP_SUPPORT:
  564 + break;
  565 +
  566 + case USB_DEVICE_B_HNP_ENABLE:
  567 + if (!usb_ss->gadget.b_hnp_enable && set)
  568 + usb_ss->gadget.b_hnp_enable = 1;
  569 + break;
  570 +
  571 + case USB_DEVICE_REMOTE_WAKEUP:
  572 + usb_ss->wake_up_flag = !!set;
  573 + break;
  574 +
  575 + case USB_DEVICE_TEST_MODE:
  576 + if (usb_ss->gadget.state != USB_STATE_CONFIGURED)
  577 + return -EINVAL;
  578 + if (usb_ss->gadget.speed != USB_SPEED_HIGH &&
  579 + usb_ss->gadget.speed != USB_SPEED_FULL)
  580 + return -EINVAL;
  581 + if (ctrl_req->wLength != 0 ||
  582 + ctrl_req->bRequestType & USB_DIR_IN) {
  583 + dev_err(&usb_ss->dev, "req is error\n");
  584 + return -EINVAL;
  585 + }
  586 + tmode = le16_to_cpu(ctrl_req->wIndex) >> 8;
  587 + switch (tmode) {
  588 + case TEST_J:
  589 + case TEST_K:
  590 + case TEST_SE0_NAK:
  591 + case TEST_PACKET:
  592 + reg = gadget_readl(usb_ss,
  593 + &usb_ss->regs->usb_cmd);
  594 + tmode -= 1;
  595 + reg |= USB_CMD__STMODE |
  596 + USB_CMD__TMODE_SEL(tmode);
  597 + gadget_writel(usb_ss, &usb_ss->regs->usb_cmd,
  598 + reg);
  599 + dev_info(&usb_ss->dev,
  600 + "set test mode, val=0x%x", reg);
  601 + break;
  602 + default:
  603 + return -EINVAL;
  604 + }
  605 + break;
  606 +
  607 + default:
  608 + return -EINVAL;
  609 + }
  610 + break;
  611 +
  612 + case USB_RECIP_INTERFACE:
  613 + return cdns_get_setup_ret(usb_ss, ctrl_req);
  614 +
  615 + case USB_RECIP_ENDPOINT:
  616 + select_ep(usb_ss, ctrl_req->wIndex);
  617 +
  618 + if (set) {
  619 + /* set stall */
  620 + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd,
  621 + EP_CMD__SSTALL__MASK);
  622 +
  623 + /* handle non zero endpoint software endpoint */
  624 + if (ctrl_req->wIndex & 0x7F) {
  625 + usb_ss_ep = usb_ss->eps[CAST_EP_ADDR_TO_INDEX(
  626 + ctrl_req->wIndex)];
  627 + usb_ss_ep->stalled_flag = 1;
  628 + }
  629 + } else {
  630 + struct usb_request *request;
  631 +
  632 + if (ctrl_req->wIndex & 0x7F) {
  633 + if (usb_ss->eps[CAST_EP_ADDR_TO_INDEX(
  634 + ctrl_req->wIndex)]->wedge_flag)
  635 + goto jmp_wedge;
  636 + }
  637 +
  638 + /* clear stall */
  639 + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd,
  640 + EP_CMD__CSTALL__MASK | EP_CMD__EPRST__MASK);
  641 + /* wait for EPRST cleared */
  642 + while (gadget_readl(usb_ss, &usb_ss->regs->ep_cmd)
  643 + & EP_CMD__EPRST__MASK)
  644 + ;
  645 +
  646 + /* handle non zero endpoint software endpoint */
  647 + if (ctrl_req->wIndex & 0x7F) {
  648 + usb_ss_ep = usb_ss->eps[CAST_EP_ADDR_TO_INDEX(
  649 + ctrl_req->wIndex)];
  650 + usb_ss_ep->stalled_flag = 0;
  651 +
  652 + request = next_request(
  653 + &usb_ss_ep->request_list);
  654 + if (request)
  655 + cdns_ep_run_transfer(usb_ss_ep);
  656 + }
  657 + }
  658 +jmp_wedge:
  659 + select_ep(usb_ss, 0x00);
  660 + break;
  661 +
  662 + default:
  663 + return -EINVAL;
  664 + }
  665 +
  666 + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd,
  667 + EP_CMD__ERDY__MASK | EP_CMD__REQ_CMPL__MASK);
  668 +
  669 + return 0;
  670 +}
  671 +
  672 +/**
  673 + * cdns_req_ep0_set_sel - Handling of SET_SEL standard USB request
  674 + * @usb_ss: extended gadget object
  675 + * @ctrl_req: pointer to received setup packet
  676 + *
  677 + * Returns 0 if success, error code on error
  678 + */
  679 +static int cdns_req_ep0_set_sel(struct usb_ss_dev *usb_ss,
  680 + struct usb_ctrlrequest *ctrl_req)
  681 +{
  682 + if (usb_ss->gadget.state < USB_STATE_ADDRESS)
  683 + return -EINVAL;
  684 +
  685 + if (ctrl_req->wLength != 6) {
  686 + dev_err(&usb_ss->dev, "Set SEL should be 6 bytes, got %d\n",
  687 + ctrl_req->wLength);
  688 + return -EINVAL;
  689 + }
  690 +
  691 + usb_ss->ep0_data_dir = 0;
  692 + usb_ss->actual_ep0_request = NULL;
  693 + cdns_ep0_run_transfer(usb_ss, usb_ss->setup_dma, 6, 1);
  694 +
  695 + return 0;
  696 +}
  697 +
  698 +/**
  699 + * cdns_req_ep0_set_isoch_delay -
  700 + * Handling of GET_ISOCH_DELAY standard USB request
  701 + * @usb_ss: extended gadget object
  702 + * @ctrl_req: pointer to received setup packet
  703 + *
  704 + * Returns 0 if success, error code on error
  705 + */
  706 +static int cdns_req_ep0_set_isoch_delay(struct usb_ss_dev *usb_ss,
  707 + struct usb_ctrlrequest *ctrl_req)
  708 +{
  709 + if (ctrl_req->wIndex || ctrl_req->wLength)
  710 + return -EINVAL;
  711 +
  712 + usb_ss->isoch_delay = ctrl_req->wValue;
  713 + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd,
  714 + EP_CMD__ERDY__MASK | EP_CMD__REQ_CMPL__MASK);
  715 + return 0;
  716 +}
  717 +
  718 +/**
  719 + * cdns_req_ep0_set_configuration - Handling of SET_CONFIG standard USB request
  720 + * @usb_ss: extended gadget object
  721 + * @ctrl_req: pointer to received setup packet
  722 + *
  723 + * Returns 0 if success, 0x7FFF on deferred status stage, error code on error
  724 + */
  725 +static int cdns_req_ep0_set_configuration(struct usb_ss_dev *usb_ss,
  726 + struct usb_ctrlrequest *ctrl_req)
  727 +{
  728 + enum usb_device_state device_state = usb_ss->gadget.state;
  729 + u32 config = le16_to_cpu(ctrl_req->wValue);
  730 + struct usb_ep *ep;
  731 + struct usb_ss_endpoint *usb_ss_ep, *temp_ss_ep;
  732 + int i, result = 0;
  733 +
  734 + switch (device_state) {
  735 + case USB_STATE_ADDRESS:
  736 + /* Configure non-control EPs */
  737 + list_for_each_entry_safe(usb_ss_ep, temp_ss_ep,
  738 + &usb_ss->ep_match_list, ep_match_pending_list) {
  739 + cdns_ep_config(usb_ss_ep);
  740 + list_del(&usb_ss_ep->ep_match_pending_list);
  741 + }
  742 +
  743 + list_for_each_entry(ep, &(usb_ss->gadget.ep_list), ep_list) {
  744 + usb_ss_ep = to_usb_ss_ep(ep);
  745 + if (usb_ss_ep->used)
  746 + cdns_ep_config(usb_ss_ep);
  747 + }
  748 +
  749 +#ifdef CDNS_THREADED_IRQ_HANDLING
  750 + usb_ss->ep_ien = gadget_readl(usb_ss, &usb_ss->regs->ep_ien)
  751 + | EP_IEN__EOUTEN0__MASK | EP_IEN__EINEN0__MASK;
  752 +#endif
  753 + result = cdns_get_setup_ret(usb_ss, ctrl_req);
  754 +
  755 + if (result != 0)
  756 + return result;
  757 +
  758 + if (config) {
  759 + if (!usb_ss->hw_configured_flag) {
  760 + /* SET CONFIGURATION */
  761 + gadget_writel(usb_ss, &usb_ss->regs->usb_conf,
  762 + USB_CONF__CFGSET__MASK);
  763 + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd,
  764 + EP_CMD__ERDY__MASK |
  765 + EP_CMD__REQ_CMPL__MASK);
  766 + /* wait until configuration set */
  767 + while (!(gadget_readl(usb_ss,
  768 + &usb_ss->regs->usb_sts)
  769 + & USB_STS__CFGSTS__MASK))
  770 + ;
  771 + usb_ss->hw_configured_flag = 1;
  772 +
  773 + list_for_each_entry(ep,
  774 + &usb_ss->gadget.ep_list,
  775 + ep_list) {
  776 + if (to_usb_ss_ep(ep)->enabled)
  777 + cdns_ep_run_transfer(
  778 + to_usb_ss_ep(ep));
  779 + }
  780 + }
  781 +
  782 + usb_gadget_set_state(&usb_ss->gadget,
  783 + USB_STATE_CONFIGURED);
  784 +
  785 + } else {
  786 + cdns_gadget_unconfig(usb_ss);
  787 + for (i = 0; i < usb_ss->ep_nums; i++)
  788 + usb_ss->eps[i]->enabled = 0;
  789 + usb_gadget_set_state(&usb_ss->gadget,
  790 + USB_STATE_ADDRESS);
  791 + }
  792 + break;
  793 +
  794 + case USB_STATE_CONFIGURED:
  795 + result = cdns_get_setup_ret(usb_ss, ctrl_req);
  796 + if (!config && !result) {
  797 + cdns_gadget_unconfig(usb_ss);
  798 + for (i = 0; i < usb_ss->ep_nums; i++)
  799 + usb_ss->eps[i]->enabled = 0;
  800 + usb_gadget_set_state(&usb_ss->gadget,
  801 + USB_STATE_ADDRESS);
  802 + }
  803 + break;
  804 +
  805 + default:
  806 + result = -EINVAL;
  807 + }
  808 +
  809 + return result;
  810 +}
  811 +
  812 +/**
  813 + * cdns_ep0_standard_request - Handling standard USB requests
  814 + * @usb_ss: extended gadget object
  815 + * @ctrl_req: pointer to received setup packet
  816 + *
  817 + * Returns 0 if success, error code on error
  818 + */
  819 +static int cdns_ep0_standard_request(struct usb_ss_dev *usb_ss,
  820 + struct usb_ctrlrequest *ctrl_req)
  821 +{
  822 + switch (ctrl_req->bRequest) {
  823 + case USB_REQ_SET_ADDRESS:
  824 + return cdns_req_ep0_set_address(usb_ss, ctrl_req);
  825 + case USB_REQ_SET_CONFIGURATION:
  826 + return cdns_req_ep0_set_configuration(usb_ss, ctrl_req);
  827 + case USB_REQ_GET_STATUS:
  828 + return cdns_req_ep0_get_status(usb_ss, ctrl_req);
  829 + case USB_REQ_CLEAR_FEATURE:
  830 + return cdns_req_ep0_handle_feature(usb_ss, ctrl_req, 0);
  831 + case USB_REQ_SET_FEATURE:
  832 + return cdns_req_ep0_handle_feature(usb_ss, ctrl_req, 1);
  833 + case USB_REQ_SET_SEL:
  834 + return cdns_req_ep0_set_sel(usb_ss, ctrl_req);
  835 + case USB_REQ_SET_ISOCH_DELAY:
  836 + return cdns_req_ep0_set_isoch_delay(usb_ss, ctrl_req);
  837 + default:
  838 + return cdns_get_setup_ret(usb_ss, ctrl_req);
  839 + }
  840 +}
  841 +
  842 +/**
  843 + * cdns_ep0_setup_phase - Handling setup USB requests
  844 + * @usb_ss: extended gadget object
  845 + */
  846 +static void cdns_ep0_setup_phase(struct usb_ss_dev *usb_ss)
  847 +{
  848 + int result;
  849 + struct usb_ctrlrequest *ctrl_req =
  850 + (struct usb_ctrlrequest *)usb_ss->setup;
  851 +
  852 + if ((ctrl_req->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
  853 + result = cdns_ep0_standard_request(usb_ss, ctrl_req);
  854 + else
  855 + result = cdns_get_setup_ret(usb_ss, ctrl_req);
  856 +
  857 + if (result != 0 && result != USB_GADGET_DELAYED_STATUS) {
  858 + dev_dbg(&usb_ss->dev, "STALL(00) %d\n", result);
  859 +
  860 + /* set_stall on ep0 */
  861 + select_ep(usb_ss, 0x00);
  862 + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd,
  863 + EP_CMD__SSTALL__MASK);
  864 + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd,
  865 + EP_CMD__ERDY__MASK | EP_CMD__REQ_CMPL__MASK);
  866 + return;
  867 + }
  868 +}
  869 +
  870 +/**
  871 + * cdns_check_ep_interrupt_proceed - Processes interrupt related to endpoint
  872 + * @usb_ss_ep: extended endpoint object
  873 + *
  874 + * Returns 0
  875 + */
  876 +static int cdns_check_ep_interrupt_proceed(struct usb_ss_endpoint *usb_ss_ep)
  877 +{
  878 + struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss;
  879 + struct usb_request *request;
  880 + u32 ep_sts_reg;
  881 +
  882 + select_ep(usb_ss, usb_ss_ep->address);
  883 + ep_sts_reg = gadget_readl(usb_ss, &usb_ss->regs->ep_sts);
  884 +
  885 + dev_dbg(&usb_ss->dev, "EP_STS: %08X\n", ep_sts_reg);
  886 +
  887 + if (ep_sts_reg & EP_STS__TRBERR__MASK) {
  888 + gadget_writel(usb_ss,
  889 + &usb_ss->regs->ep_sts, EP_STS__TRBERR__MASK);
  890 +
  891 + dev_dbg(&usb_ss->dev, "TRBERR(%02X)\n",
  892 + usb_ss_ep->endpoint.desc->bEndpointAddress);
  893 + }
  894 +
  895 + if (ep_sts_reg & EP_STS__ISOERR__MASK) {
  896 + gadget_writel(usb_ss,
  897 + &usb_ss->regs->ep_sts, EP_STS__ISOERR__MASK);
  898 + dev_dbg(&usb_ss->dev, "ISOERR(%02X)\n",
  899 + usb_ss_ep->endpoint.desc->bEndpointAddress);
  900 + }
  901 +
  902 + if (ep_sts_reg & EP_STS__OUTSMM__MASK) {
  903 + gadget_writel(usb_ss, &usb_ss->regs->ep_sts,
  904 + EP_STS__OUTSMM__MASK);
  905 + dev_dbg(&usb_ss->dev, "OUTSMM(%02X)\n",
  906 + usb_ss_ep->endpoint.desc->bEndpointAddress);
  907 + }
  908 +
  909 + if (ep_sts_reg & EP_STS__NRDY__MASK) {
  910 + gadget_writel(usb_ss,
  911 + &usb_ss->regs->ep_sts, EP_STS__NRDY__MASK);
  912 + dev_dbg(&usb_ss->dev, "NRDY(%02X)\n",
  913 + usb_ss_ep->endpoint.desc->bEndpointAddress);
  914 + }
  915 +
  916 + if ((ep_sts_reg & EP_STS__IOC__MASK)
  917 + || (ep_sts_reg & EP_STS__ISP__MASK)) {
  918 + cdns_flush_cache((uintptr_t)usb_ss_ep->trb_pool, sizeof(struct usb_ss_trb));
  919 +
  920 + gadget_writel(usb_ss, &usb_ss->regs->ep_sts,
  921 + EP_STS__IOC__MASK | EP_STS__ISP__MASK);
  922 +
  923 + /* get just completed request */
  924 + request = next_request(&usb_ss_ep->request_list);
  925 + usb_gadget_unmap_request(&usb_ss->gadget, request,
  926 + usb_ss_ep->endpoint.desc->bEndpointAddress
  927 + & ENDPOINT_DIR_MASK);
  928 +
  929 + request->status = 0;
  930 + request->actual =
  931 + le32_to_cpu(((u32 *)usb_ss_ep->trb_pool)[1])
  932 + & ACTUAL_TRANSFERRED_BYTES_MASK;
  933 +
  934 + dev_dbg(&usb_ss->dev, "IOC(%02X) %d\n",
  935 + usb_ss_ep->endpoint.desc->bEndpointAddress,
  936 + request->actual);
  937 +
  938 + list_del(&request->list);
  939 +
  940 + usb_ss_ep->hw_pending_flag = 0;
  941 + if (request->complete) {
  942 + spin_unlock(&usb_ss->lock);
  943 + usb_gadget_giveback_request(&usb_ss_ep->endpoint,
  944 + request);
  945 + spin_lock(&usb_ss->lock);
  946 + }
  947 +
  948 + /* handle deferred STALL */
  949 + if (usb_ss_ep->stalled_flag) {
  950 + cdns_ep_stall_flush(usb_ss_ep);
  951 + return 0;
  952 + }
  953 +
  954 + /* exit if hardware transfer already started */
  955 + if (usb_ss_ep->hw_pending_flag)
  956 + return 0;
  957 +
  958 + /* if any request queued run it! */
  959 + if (!list_empty(&usb_ss_ep->request_list))
  960 + cdns_ep_run_transfer(usb_ss_ep);
  961 + }
  962 +
  963 + if (ep_sts_reg & EP_STS__DESCMIS__MASK) {
  964 + gadget_writel(usb_ss,
  965 + &usb_ss->regs->ep_sts, EP_STS__DESCMIS__MASK);
  966 + dev_dbg(&usb_ss->dev, "DESCMIS(%02X)\n",
  967 + usb_ss_ep->endpoint.desc->bEndpointAddress);
  968 + }
  969 +
  970 + return 0;
  971 +}
  972 +
  973 +/**
  974 + * cdns_check_ep0_interrupt_proceed - Processes interrupt related to endpoint 0
  975 + * @usb_ss: extended gadget object
  976 + * @dir: 1 for IN direction, 0 for OUT direction
  977 + */
  978 +static void cdns_check_ep0_interrupt_proceed(struct usb_ss_dev *usb_ss, int dir)
  979 +{
  980 + u32 ep_sts_reg;
  981 + int i;
  982 +
  983 + select_ep(usb_ss, 0 | (dir ? USB_DIR_IN : USB_DIR_OUT));
  984 + ep_sts_reg = gadget_readl(usb_ss, &usb_ss->regs->ep_sts);
  985 +
  986 + dev_dbg(&usb_ss->dev, "EP_STS: %08X\n", ep_sts_reg);
  987 +
  988 + if ((ep_sts_reg & EP_STS__SETUP__MASK) && (dir == 0)) {
  989 + cdns_flush_cache((uintptr_t)usb_ss->setup, 8);
  990 +
  991 + dev_dbg(&usb_ss->dev, "SETUP(%02X)\n", 0x00);
  992 +
  993 + gadget_writel(usb_ss, &usb_ss->regs->ep_sts,
  994 + EP_STS__SETUP__MASK |
  995 + EP_STS__IOC__MASK | EP_STS__ISP__MASK);
  996 +
  997 + dev_dbg(&usb_ss->dev, "SETUP: ");
  998 + for (i = 0; i < 8; i++)
  999 + dev_dbg(&usb_ss->dev, "%02X ", usb_ss->setup[i]);
  1000 + dev_dbg(&usb_ss->dev, "\nSTATE: %d\n", usb_ss->gadget.state);
  1001 + usb_ss->ep0_data_dir = usb_ss->setup[0] & USB_DIR_IN;
  1002 + cdns_ep0_setup_phase(usb_ss);
  1003 + ep_sts_reg &= ~(EP_STS__SETUP__MASK |
  1004 + EP_STS__IOC__MASK |
  1005 + EP_STS__ISP__MASK);
  1006 + }
  1007 +
  1008 + if (ep_sts_reg & EP_STS__TRBERR__MASK) {
  1009 + gadget_writel(usb_ss,
  1010 + &usb_ss->regs->ep_sts, EP_STS__TRBERR__MASK);
  1011 + dev_dbg(&usb_ss->dev, "TRBERR(%02X)\n",
  1012 + dir ? USB_DIR_IN : USB_DIR_OUT);
  1013 + }
  1014 +
  1015 + if (ep_sts_reg & EP_STS__DESCMIS__MASK) {
  1016 + gadget_writel(usb_ss,
  1017 + &usb_ss->regs->ep_sts, EP_STS__DESCMIS__MASK);
  1018 +
  1019 + dev_dbg(&usb_ss->dev, "DESCMIS(%02X)\n",
  1020 + dir ? USB_DIR_IN : USB_DIR_OUT);
  1021 +
  1022 + if (dir == 0 && !usb_ss->setup_pending) {
  1023 + usb_ss->ep0_data_dir = 0;
  1024 + cdns_ep0_run_transfer(usb_ss,
  1025 + usb_ss->setup_dma, 8, 0);
  1026 + }
  1027 + }
  1028 +
  1029 + if ((ep_sts_reg & EP_STS__IOC__MASK) ||
  1030 + (ep_sts_reg & EP_STS__ISP__MASK)) {
  1031 + cdns_flush_cache((uintptr_t)usb_ss->trb_ep0, 20);
  1032 +
  1033 + gadget_writel(usb_ss,
  1034 + &usb_ss->regs->ep_sts, EP_STS__IOC__MASK);
  1035 + if (usb_ss->actual_ep0_request) {
  1036 + usb_gadget_unmap_request(&usb_ss->gadget,
  1037 + usb_ss->actual_ep0_request,
  1038 + usb_ss->ep0_data_dir);
  1039 +
  1040 + usb_ss->actual_ep0_request->actual =
  1041 + le32_to_cpu((usb_ss->trb_ep0)[1])
  1042 + & ACTUAL_TRANSFERRED_BYTES_MASK;
  1043 +
  1044 + dev_dbg(&usb_ss->dev, "IOC(%02X) %d\n",
  1045 + dir ? USB_DIR_IN : USB_DIR_OUT,
  1046 + usb_ss->actual_ep0_request->actual);
  1047 + }
  1048 +
  1049 + if (usb_ss->actual_ep0_request &&
  1050 + usb_ss->actual_ep0_request->complete) {
  1051 + spin_unlock(&usb_ss->lock);
  1052 + usb_ss->actual_ep0_request->complete(usb_ss->gadget.ep0,
  1053 + usb_ss->actual_ep0_request);
  1054 + spin_lock(&usb_ss->lock);
  1055 + }
  1056 + cdns_prepare_setup_packet(usb_ss);
  1057 + gadget_writel(usb_ss,
  1058 + &usb_ss->regs->ep_cmd, EP_CMD__REQ_CMPL__MASK);
  1059 + }
  1060 +}
  1061 +
  1062 +/**
  1063 + * cdns_check_usb_interrupt_proceed - Processes interrupt related to device
  1064 + * @usb_ss: extended gadget object
  1065 + * @usb_ists: bitmap representation of device's reported interrupts
  1066 + * (usb_ists register value)
  1067 + */
  1068 +static void cdns_check_usb_interrupt_proceed(struct usb_ss_dev *usb_ss,
  1069 + u32 usb_ists)
  1070 +{
  1071 + int interrupt_bit = ffs(usb_ists) - 1;
  1072 + int speed;
  1073 + u32 val;
  1074 +
  1075 + dev_dbg(&usb_ss->dev, "USB interrupt detected\n");
  1076 +
  1077 + switch (interrupt_bit) {
  1078 + case USB_ISTS__CON2I__SHIFT:
  1079 + /* FS/HS Connection detected */
  1080 + dev_dbg(&usb_ss->dev,
  1081 + "[Interrupt] FS/HS Connection detected\n");
  1082 + val = gadget_readl(usb_ss, &usb_ss->regs->usb_sts);
  1083 + speed = USB_STS__USBSPEED__READ(val);
  1084 + if (speed == USB_SPEED_WIRELESS)
  1085 + speed = USB_SPEED_SUPER;
  1086 + dev_dbg(&usb_ss->dev, "Speed value: %s (%d), usbsts:0x%x\n",
  1087 + usb_speed_string(speed), speed, val);
  1088 + usb_ss->gadget.speed = speed;
  1089 + usb_ss->is_connected = 1;
  1090 + usb_gadget_set_state(&usb_ss->gadget, USB_STATE_POWERED);
  1091 + cdns_ep0_config(usb_ss);
  1092 + break;
  1093 +
  1094 + case USB_ISTS__CONI__SHIFT:
  1095 + /* SS Connection detected */
  1096 + dev_dbg(&usb_ss->dev, "[Interrupt] SS Connection detected\n");
  1097 + val = gadget_readl(usb_ss, &usb_ss->regs->usb_sts);
  1098 + speed = USB_STS__USBSPEED__READ(val);
  1099 + if (speed == USB_SPEED_WIRELESS)
  1100 + speed = USB_SPEED_SUPER;
  1101 + dev_dbg(&usb_ss->dev, "Speed value: %s (%d), usbsts:0x%x\n",
  1102 + usb_speed_string(speed), speed, val);
  1103 + usb_ss->gadget.speed = speed;
  1104 + usb_ss->is_connected = 1;
  1105 + usb_gadget_set_state(&usb_ss->gadget, USB_STATE_POWERED);
  1106 + cdns_ep0_config(usb_ss);
  1107 + break;
  1108 +
  1109 + case USB_ISTS__DIS2I__SHIFT:
  1110 + case USB_ISTS__DISI__SHIFT:
  1111 + /* SS Disconnection detected */
  1112 + val = gadget_readl(usb_ss, &usb_ss->regs->usb_sts);
  1113 + dev_dbg(&usb_ss->dev,
  1114 + "[Interrupt] Disconnection detected: usbsts:0x%x\n",
  1115 + val);
  1116 + if (usb_ss->gadget_driver &&
  1117 + usb_ss->gadget_driver->disconnect) {
  1118 + spin_unlock(&usb_ss->lock);
  1119 + usb_ss->gadget_driver->disconnect(&usb_ss->gadget);
  1120 + spin_lock(&usb_ss->lock);
  1121 + }
  1122 + usb_ss->gadget.speed = USB_SPEED_UNKNOWN;
  1123 + usb_gadget_set_state(&usb_ss->gadget, USB_STATE_NOTATTACHED);
  1124 + usb_ss->is_connected = 0;
  1125 + cdns_gadget_unconfig(usb_ss);
  1126 + break;
  1127 +
  1128 + case USB_ISTS__L2ENTI__SHIFT:
  1129 + dev_dbg(&usb_ss->dev,
  1130 + "[Interrupt] Device suspended\n");
  1131 + break;
  1132 +
  1133 + case USB_ISTS__L2EXTI__SHIFT:
  1134 + dev_dbg(&usb_ss->dev, "[Interrupt] L2 exit detected\n");
  1135 + /*
  1136 + * Exit from standby mode
  1137 + * on L2 exit (Suspend in HS/FS or SS)
  1138 + */
  1139 + break;
  1140 + case USB_ISTS__U3EXTI__SHIFT:
  1141 + /*
  1142 + * Exit from standby mode
  1143 + * on U3 exit (Suspend in HS/FS or SS)
  1144 + */
  1145 + dev_dbg(&usb_ss->dev, "[Interrupt] U3 exit detected\n");
  1146 + break;
  1147 +
  1148 + /* resets cases */
  1149 + case USB_ISTS__UWRESI__SHIFT:
  1150 + case USB_ISTS__UHRESI__SHIFT:
  1151 + case USB_ISTS__U2RESI__SHIFT:
  1152 + dev_dbg(&usb_ss->dev, "[Interrupt] Reset detected\n");
  1153 + speed = USB_STS__USBSPEED__READ(
  1154 + gadget_readl(usb_ss, &usb_ss->regs->usb_sts));
  1155 + if (speed == USB_SPEED_WIRELESS)
  1156 + speed = USB_SPEED_SUPER;
  1157 + usb_gadget_set_state(&usb_ss->gadget, USB_STATE_DEFAULT);
  1158 + usb_ss->gadget.speed = speed;
  1159 + cdns_gadget_unconfig(usb_ss);
  1160 + cdns_ep0_config(usb_ss);
  1161 + break;
  1162 + default:
  1163 + break;
  1164 + }
  1165 +
  1166 + /* Clear interrupt bit */
  1167 + gadget_writel(usb_ss, &usb_ss->regs->usb_ists, (1uL << interrupt_bit));
  1168 +}
  1169 +
  1170 +#ifdef CDNS_THREADED_IRQ_HANDLING
  1171 +static irqreturn_t cdns_irq_handler(int irq, void *_usb_ss)
  1172 +{
  1173 + struct usb_ss_dev *usb_ss = _usb_ss;
  1174 +
  1175 + usb_ss->usb_ien = gadget_readl(usb_ss, &usb_ss->regs->usb_ien);
  1176 + usb_ss->ep_ien = gadget_readl(usb_ss, &usb_ss->regs->ep_ien);
  1177 +
  1178 + if (!gadget_readl(usb_ss, &usb_ss->regs->usb_ists) &&
  1179 + !gadget_readl(usb_ss, &usb_ss->regs->ep_ists)) {
  1180 + dev_dbg(&usb_ss->dev, "--BUBBLE INTERRUPT 0 !!!\n");
  1181 + if (gadget_readl(usb_ss, &usb_ss->regs->usb_sts) &
  1182 + USB_STS__CFGSTS__MASK)
  1183 + return IRQ_HANDLED;
  1184 + return IRQ_NONE;
  1185 + }
  1186 +
  1187 + gadget_writel(usb_ss, &usb_ss->regs->usb_ien, 0);
  1188 + gadget_writel(usb_ss, &usb_ss->regs->ep_ien, 0);
  1189 +
  1190 + gadget_readl(usb_ss, &usb_ss->regs->dma_axi_ctrl);
  1191 + return IRQ_WAKE_THREAD;
  1192 +}
  1193 +#endif
  1194 +
  1195 +/**
  1196 + * cdns_irq_handler - irq line interrupt handler
  1197 + * @cdns: cdns3 instance
  1198 + *
  1199 + * Returns IRQ_HANDLED when interrupt raised by USBSS_DEV,
  1200 + * IRQ_NONE when interrupt raised by other device connected
  1201 + * to the irq line
  1202 + */
  1203 +static int cdns_irq_handler_thread(struct cdns3 *cdns)
  1204 +{
  1205 + struct usb_ss_dev *usb_ss =
  1206 + container_of(cdns->gadget_dev, struct usb_ss_dev, dev);
  1207 + u32 reg;
  1208 + int ret = IRQ_NONE;
  1209 + unsigned long flags;
  1210 +
  1211 + spin_lock_irqsave(&usb_ss->lock, flags);
  1212 +
  1213 + /* check USB device interrupt */
  1214 + reg = gadget_readl(usb_ss, &usb_ss->regs->usb_ists);
  1215 + if (reg) {
  1216 + dev_dbg(&usb_ss->dev, "usb_ists: %08X\n", reg);
  1217 + cdns_check_usb_interrupt_proceed(usb_ss, reg);
  1218 + ret = IRQ_HANDLED;
  1219 + }
  1220 +
  1221 + /* check endpoint interrupt */
  1222 + reg = gadget_readl(usb_ss, &usb_ss->regs->ep_ists);
  1223 + if (reg != 0) {
  1224 + dev_dbg(&usb_ss->dev, "ep_ists: %08X\n", reg);
  1225 + } else {
  1226 + if (gadget_readl(usb_ss, &usb_ss->regs->usb_sts) &
  1227 + USB_STS__CFGSTS__MASK)
  1228 + ret = IRQ_HANDLED;
  1229 + goto irqend;
  1230 + }
  1231 +
  1232 + /* handle default endpoint OUT */
  1233 + if (reg & EP_ISTS__EOUT0__MASK) {
  1234 + cdns_check_ep0_interrupt_proceed(usb_ss, 0);
  1235 + ret = IRQ_HANDLED;
  1236 + }
  1237 +
  1238 + /* handle default endpoint IN */
  1239 + if (reg & EP_ISTS__EIN0__MASK) {
  1240 + cdns_check_ep0_interrupt_proceed(usb_ss, 1);
  1241 + ret = IRQ_HANDLED;
  1242 + }
  1243 +
  1244 + /* check if interrupt from non default endpoint, if no exit */
  1245 + reg &= ~(EP_ISTS__EOUT0__MASK | EP_ISTS__EIN0__MASK);
  1246 + if (!reg)
  1247 + goto irqend;
  1248 +
  1249 + do {
  1250 + unsigned int bit_pos = ffs(reg);
  1251 + u32 bit_mask = 1 << (bit_pos - 1);
  1252 +
  1253 + dev_dbg(&usb_ss->dev, "Interrupt on index: %d bitmask %08X\n",
  1254 + CAST_EP_REG_POS_TO_INDEX(bit_pos), bit_mask);
  1255 + cdns_check_ep_interrupt_proceed(
  1256 + usb_ss->eps[CAST_EP_REG_POS_TO_INDEX(bit_pos)]);
  1257 + reg &= ~bit_mask;
  1258 + ret = IRQ_HANDLED;
  1259 + } while (reg);
  1260 +
  1261 +irqend:
  1262 +
  1263 + spin_unlock_irqrestore(&usb_ss->lock, flags);
  1264 +#ifdef CDNS_THREADED_IRQ_HANDLING
  1265 + local_irq_save(flags);
  1266 + gadget_writel(usb_ss, &usb_ss->regs->usb_ien, usb_ss->usb_ien);
  1267 + gadget_writel(usb_ss, &usb_ss->regs->ep_ien, usb_ss->ep_ien);
  1268 + local_irq_restore(flags);
  1269 +#endif
  1270 + return ret;
  1271 +}
  1272 +
  1273 +/**
  1274 + * usb_ss_gadget_ep0_enable
  1275 + * Function shouldn't be called by gadget driver,
  1276 + * endpoint 0 is allways active
  1277 + */
  1278 +static int usb_ss_gadget_ep0_enable(struct usb_ep *ep,
  1279 + const struct usb_endpoint_descriptor *desc)
  1280 +{
  1281 + return -EINVAL;
  1282 +}
  1283 +
  1284 +/**
  1285 + * usb_ss_gadget_ep0_disable
  1286 + * Function shouldn't be called by gadget driver,
  1287 + * endpoint 0 is allways active
  1288 + */
  1289 +static int usb_ss_gadget_ep0_disable(struct usb_ep *ep)
  1290 +{
  1291 + return -EINVAL;
  1292 +}
  1293 +
  1294 +/**
  1295 + * usb_ss_gadget_ep0_set_halt
  1296 + * @ep: pointer to endpoint zero object
  1297 + * @value: 1 for set stall, 0 for clear stall
  1298 + *
  1299 + * Returns 0
  1300 + */
  1301 +static int usb_ss_gadget_ep0_set_halt(struct usb_ep *ep, int value)
  1302 +{
  1303 + /* TODO */
  1304 + return 0;
  1305 +}
  1306 +
  1307 +/**
  1308 + * usb_ss_gadget_ep0_queue Transfer data on endpoint zero
  1309 + * @ep: pointer to endpoint zero object
  1310 + * @request: pointer to request object
  1311 + * @gfp_flags: gfp flags
  1312 + *
  1313 + * Returns 0 on success, error code elsewhere
  1314 + */
  1315 +static int usb_ss_gadget_ep0_queue(struct usb_ep *ep,
  1316 + struct usb_request *request, gfp_t gfp_flags)
  1317 +{
  1318 + int ret;
  1319 + unsigned long flags;
  1320 + int erdy_sent = 0;
  1321 + /* get extended endpoint */
  1322 + struct usb_ss_endpoint *usb_ss_ep =
  1323 + to_usb_ss_ep(ep);
  1324 + struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss;
  1325 +
  1326 + dev_dbg(&usb_ss->dev, "QUEUE(%02X) %d\n",
  1327 + usb_ss->ep0_data_dir ? USB_DIR_IN : USB_DIR_OUT,
  1328 + request->length);
  1329 +
  1330 + /* send STATUS stage */
  1331 + if (request->length == 0 && request->zero == 0) {
  1332 + spin_lock_irqsave(&usb_ss->lock, flags);
  1333 + select_ep(usb_ss, 0x00);
  1334 + if (!usb_ss->hw_configured_flag) {
  1335 + gadget_writel(usb_ss, &usb_ss->regs->usb_conf,
  1336 + USB_CONF__CFGSET__MASK); /* SET CONFIGURATION */
  1337 + cdns_prepare_setup_packet(usb_ss);
  1338 + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd,
  1339 + EP_CMD__ERDY__MASK | EP_CMD__REQ_CMPL__MASK);
  1340 + /* wait until configuration set */
  1341 + while (!(gadget_readl(usb_ss, &usb_ss->regs->usb_sts)
  1342 + & USB_STS__CFGSTS__MASK))
  1343 + ;
  1344 + erdy_sent = 1;
  1345 + usb_ss->hw_configured_flag = 1;
  1346 +
  1347 + list_for_each_entry(ep,
  1348 + &usb_ss->gadget.ep_list,
  1349 + ep_list) {
  1350 + if (to_usb_ss_ep(ep)->enabled)
  1351 + cdns_ep_run_transfer(
  1352 + to_usb_ss_ep(ep));
  1353 + }
  1354 + }
  1355 + if (!erdy_sent)
  1356 + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd,
  1357 + EP_CMD__ERDY__MASK | EP_CMD__REQ_CMPL__MASK);
  1358 + if (request->complete)
  1359 + request->complete(usb_ss->gadget.ep0, request);
  1360 + spin_unlock_irqrestore(&usb_ss->lock, flags);
  1361 + return 0;
  1362 + }
  1363 +
  1364 + spin_lock_irqsave(&usb_ss->lock, flags);
  1365 + ret = usb_gadget_map_request(&usb_ss->gadget, request,
  1366 + usb_ss->ep0_data_dir);
  1367 + if (ret) {
  1368 + dev_err(&usb_ss->dev, "failed to map request\n");
  1369 + return -EINVAL;
  1370 + }
  1371 +
  1372 + usb_ss->actual_ep0_request = request;
  1373 + cdns_ep0_run_transfer(usb_ss, request->dma, request->length, 1);
  1374 +
  1375 + spin_unlock_irqrestore(&usb_ss->lock, flags);
  1376 +
  1377 + return 0;
  1378 +}
  1379 +
  1380 +/**
  1381 + * cdns_ep_config Configure hardware endpoint
  1382 + * @usb_ss_ep: extended endpoint object
  1383 + */
  1384 +static void cdns_ep_config(struct usb_ss_endpoint *usb_ss_ep)
  1385 +{
  1386 + struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss;
  1387 + u32 ep_cfg = 0;
  1388 + u32 max_packet_size = 0;
  1389 + u32 bEndpointAddress = usb_ss_ep->num | usb_ss_ep->dir;
  1390 + u32 interrupt_mask = 0;
  1391 + bool is_iso_ep = (usb_ss_ep->type == USB_ENDPOINT_XFER_ISOC);
  1392 +
  1393 + dev_dbg(&usb_ss->dev, "%s: %s addr=0x%x, speed %d, is_iso_ep %d\n", __func__,
  1394 + usb_ss_ep->name, bEndpointAddress, usb_ss->gadget.speed, is_iso_ep);
  1395 +
  1396 + if (is_iso_ep) {
  1397 + ep_cfg = EP_CFG__EPTYPE__WRITE(USB_ENDPOINT_XFER_ISOC);
  1398 + interrupt_mask = INTERRUPT_MASK;
  1399 + } else {
  1400 + ep_cfg = EP_CFG__EPTYPE__WRITE(USB_ENDPOINT_XFER_BULK);
  1401 + }
  1402 +
  1403 + switch (usb_ss->gadget.speed) {
  1404 + case USB_SPEED_UNKNOWN:
  1405 + max_packet_size = ENDPOINT_MAX_PACKET_SIZE_0;
  1406 + break;
  1407 +
  1408 + case USB_SPEED_LOW:
  1409 + max_packet_size = ENDPOINT_MAX_PACKET_SIZE_8;
  1410 + break;
  1411 +
  1412 + case USB_SPEED_FULL:
  1413 + max_packet_size = (is_iso_ep ?
  1414 + ENDPOINT_MAX_PACKET_SIZE_1023 :
  1415 + ENDPOINT_MAX_PACKET_SIZE_64);
  1416 + break;
  1417 +
  1418 + case USB_SPEED_HIGH:
  1419 + max_packet_size = (is_iso_ep ?
  1420 + ENDPOINT_MAX_PACKET_SIZE_1024 :
  1421 + ENDPOINT_MAX_PACKET_SIZE_512);
  1422 + break;
  1423 +
  1424 + case USB_SPEED_WIRELESS:
  1425 + max_packet_size = ENDPOINT_MAX_PACKET_SIZE_512;
  1426 + break;
  1427 +
  1428 + case USB_SPEED_SUPER:
  1429 + max_packet_size = ENDPOINT_MAX_PACKET_SIZE_1024;
  1430 + break;
  1431 + }
  1432 +
  1433 + ep_cfg |= EP_CFG__MAXPKTSIZE__WRITE(max_packet_size);
  1434 +
  1435 + if (is_iso_ep) {
  1436 + ep_cfg |= EP_CFG__BUFFERING__WRITE(1);
  1437 + ep_cfg |= EP_CFG__MAXBURST__WRITE(0);
  1438 + } else {
  1439 + ep_cfg |= EP_CFG__BUFFERING__WRITE(3);
  1440 + ep_cfg |= EP_CFG__MAXBURST__WRITE(15);
  1441 + }
  1442 +
  1443 + select_ep(usb_ss, bEndpointAddress);
  1444 + gadget_writel(usb_ss, &usb_ss->regs->ep_cfg, ep_cfg);
  1445 + gadget_writel(usb_ss, &usb_ss->regs->ep_sts_en,
  1446 + EP_STS_EN__TRBERREN__MASK | interrupt_mask);
  1447 +
  1448 + /* enable interrupt for selected endpoint */
  1449 + ep_cfg = gadget_readl(usb_ss, &usb_ss->regs->ep_ien);
  1450 + ep_cfg |= CAST_EP_ADDR_TO_BIT_POS(bEndpointAddress);
  1451 + gadget_writel(usb_ss, &usb_ss->regs->ep_ien, ep_cfg);
  1452 +}
  1453 +
  1454 +/**
  1455 + * usb_ss_gadget_ep_enable Enable endpoint
  1456 + * @ep: endpoint object
  1457 + * @desc: endpoint descriptor
  1458 + *
  1459 + * Returns 0 on success, error code elsewhere
  1460 + */
  1461 +static int usb_ss_gadget_ep_enable(struct usb_ep *ep,
  1462 + const struct usb_endpoint_descriptor *desc)
  1463 +{
  1464 + struct usb_ss_endpoint *usb_ss_ep;
  1465 + struct usb_ss_dev *usb_ss;
  1466 + unsigned long flags;
  1467 + int ret;
  1468 + u32 ep_cfg;
  1469 +
  1470 + usb_ss_ep = to_usb_ss_ep(ep);
  1471 + usb_ss = usb_ss_ep->usb_ss;
  1472 +
  1473 + if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
  1474 + dev_err(&usb_ss->dev, "usb-ss: invalid parameters\n");
  1475 + return -EINVAL;
  1476 + }
  1477 +
  1478 + if (!desc->wMaxPacketSize) {
  1479 + dev_err(&usb_ss->dev, "usb-ss: missing wMaxPacketSize\n");
  1480 + return -EINVAL;
  1481 + }
  1482 +
  1483 + ret = usb_ss_allocate_trb_pool(usb_ss_ep);
  1484 + if (ret)
  1485 + return ret;
  1486 +
  1487 + if (!usb_ss_ep->cpu_addr) {
  1488 + usb_ss_ep->cpu_addr = dma_alloc_coherent(4096,
  1489 + (unsigned long *)&usb_ss_ep->dma_addr);
  1490 +
  1491 + if (!usb_ss_ep->cpu_addr)
  1492 + return -ENOMEM;
  1493 + }
  1494 +
  1495 + dev_dbg(&usb_ss->dev, "Enabling endpoint: %s, addr=0x%x\n",
  1496 + ep->name, desc->bEndpointAddress);
  1497 + spin_lock_irqsave(&usb_ss->lock, flags);
  1498 + select_ep(usb_ss, desc->bEndpointAddress);
  1499 + ep_cfg = gadget_readl(usb_ss, &usb_ss->regs->ep_cfg);
  1500 + ep_cfg |= EP_CFG__ENABLE__MASK;
  1501 + gadget_writel(usb_ss, &usb_ss->regs->ep_cfg, ep_cfg);
  1502 +
  1503 + usb_ss_ep->enabled = 1;
  1504 + ep->desc = desc;
  1505 + usb_ss_ep->hw_pending_flag = 0;
  1506 + spin_unlock_irqrestore(&usb_ss->lock, flags);
  1507 +
  1508 + return 0;
  1509 +}
  1510 +
  1511 +static int usb_ss_gadget_match_ep(struct usb_gadget *gadget,
  1512 + struct usb_ep *ep,
  1513 + struct usb_endpoint_descriptor *desc)
  1514 +{
  1515 + struct usb_ss_dev __maybe_unused *usb_ss = gadget_to_usb_ss(gadget);
  1516 + struct usb_ss_endpoint *usb_ss_ep;
  1517 + unsigned long flags;
  1518 +
  1519 + usb_ss_ep = to_usb_ss_ep(ep);
  1520 +
  1521 + dev_dbg(&usb_ss->dev, "match endpoint: %s\n", usb_ss_ep->name);
  1522 +
  1523 + u8 num = simple_strtoul(&ep->name[2], NULL, 10);
  1524 +
  1525 + spin_lock_irqsave(&usb_ss->lock, flags);
  1526 + usb_ss_ep->num = num;
  1527 + usb_ss_ep->used = true;
  1528 + usb_ss_ep->endpoint.desc = desc;
  1529 + usb_ss_ep->dir = usb_endpoint_dir_in(desc) ? USB_DIR_IN : USB_DIR_OUT;
  1530 + usb_ss_ep->type = usb_endpoint_type(desc);
  1531 + usb_ss_ep->address = desc->bEndpointAddress;
  1532 + spin_unlock_irqrestore(&usb_ss->lock, flags);
  1533 +
  1534 + return 1;
  1535 +}
  1536 +
  1537 +static void usb_ss_free_trb_pool(struct usb_ss_endpoint *usb_ss_ep)
  1538 +{
  1539 + if (usb_ss_ep->trb_pool) {
  1540 + dma_free_coherent(usb_ss_ep->trb_pool);
  1541 + usb_ss_ep->trb_pool = NULL;
  1542 + }
  1543 +
  1544 + if (usb_ss_ep->cpu_addr) {
  1545 + dma_free_coherent(usb_ss_ep->cpu_addr);
  1546 + usb_ss_ep->cpu_addr = NULL;
  1547 + }
  1548 +}
  1549 +
  1550 +/**
  1551 + * usb_ss_gadget_ep_disable Disable endpoint
  1552 + * @ep: endpoint object
  1553 + *
  1554 + * Returns 0 on success, error code elsewhere
  1555 + */
  1556 +static int usb_ss_gadget_ep_disable(struct usb_ep *ep)
  1557 +{
  1558 + struct usb_ss_endpoint *usb_ss_ep;
  1559 + struct usb_ss_dev *usb_ss;
  1560 + unsigned long flags;
  1561 + int ret = 0;
  1562 + struct usb_request *request;
  1563 + u32 ep_cfg;
  1564 +
  1565 + if (!ep) {
  1566 + pr_debug("usb-ss: invalid parameters\n");
  1567 + return -EINVAL;
  1568 + }
  1569 +
  1570 + usb_ss_ep = to_usb_ss_ep(ep);
  1571 + usb_ss = usb_ss_ep->usb_ss;
  1572 +
  1573 + spin_lock_irqsave(&usb_ss->lock, flags);
  1574 + if (!usb_ss->start_gadget) {
  1575 + dev_dbg(&usb_ss->dev,
  1576 + "Disabling endpoint at disconnection: %s\n", ep->name);
  1577 + spin_unlock_irqrestore(&usb_ss->lock, flags);
  1578 + return 0;
  1579 + }
  1580 +
  1581 + dev_dbg(&usb_ss->dev,
  1582 + "Disabling endpoint: %s\n", ep->name);
  1583 +
  1584 + while (!list_empty(&usb_ss_ep->request_list)) {
  1585 +
  1586 + request = next_request(&usb_ss_ep->request_list);
  1587 + usb_gadget_unmap_request(&usb_ss->gadget, request,
  1588 + ep->desc->bEndpointAddress & USB_DIR_IN);
  1589 + request->status = -ESHUTDOWN;
  1590 + list_del(&request->list);
  1591 + spin_unlock(&usb_ss->lock);
  1592 + usb_gadget_giveback_request(ep, request);
  1593 + spin_lock(&usb_ss->lock);
  1594 + }
  1595 +
  1596 + select_ep(usb_ss, ep->desc->bEndpointAddress);
  1597 + ep_cfg = gadget_readl(usb_ss, &usb_ss->regs->ep_cfg);
  1598 + ep_cfg &= ~EP_CFG__ENABLE__MASK;
  1599 + gadget_writel(usb_ss, &usb_ss->regs->ep_cfg, ep_cfg);
  1600 + ep->desc = NULL;
  1601 + usb_ss_ep->enabled = 0;
  1602 +
  1603 + spin_unlock_irqrestore(&usb_ss->lock, flags);
  1604 +
  1605 + return ret;
  1606 +}
  1607 +
  1608 +/**
  1609 + * usb_ss_gadget_ep_alloc_request Allocates request
  1610 + * @ep: endpoint object associated with request
  1611 + * @gfp_flags: gfp flags
  1612 + *
  1613 + * Returns allocated request address, NULL on allocation error
  1614 + */
  1615 +static struct usb_request *usb_ss_gadget_ep_alloc_request(struct usb_ep *ep,
  1616 + gfp_t gfp_flags)
  1617 +{
  1618 + struct usb_request *request;
  1619 +
  1620 + request = kzalloc(sizeof(struct usb_request), gfp_flags);
  1621 + if (!request)
  1622 + return NULL;
  1623 +
  1624 + return request;
  1625 +}
  1626 +
  1627 +/**
  1628 + * usb_ss_gadget_ep_free_request Free memory occupied by request
  1629 + * @ep: endpoint object associated with request
  1630 + * @request: request to free memory
  1631 + */
  1632 +static void usb_ss_gadget_ep_free_request(struct usb_ep *ep,
  1633 + struct usb_request *request)
  1634 +{
  1635 + kfree(request);
  1636 +}
  1637 +
  1638 +/**
  1639 + * usb_ss_gadget_ep_queue Transfer data on endpoint
  1640 + * @ep: endpoint object
  1641 + * @request: request object
  1642 + * @gfp_flags: gfp flags
  1643 + *
  1644 + * Returns 0 on success, error code elsewhere
  1645 + */
  1646 +static int usb_ss_gadget_ep_queue(struct usb_ep *ep,
  1647 + struct usb_request *request, gfp_t gfp_flags)
  1648 +{
  1649 + struct usb_ss_endpoint *usb_ss_ep =
  1650 + to_usb_ss_ep(ep);
  1651 + struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss;
  1652 + unsigned long flags;
  1653 + int ret = 0;
  1654 + int empty_list = 0;
  1655 +
  1656 + spin_lock_irqsave(&usb_ss->lock, flags);
  1657 +
  1658 + request->actual = 0;
  1659 + request->status = -EINPROGRESS;
  1660 +
  1661 + dev_dbg(&usb_ss->dev,
  1662 + "Queuing endpoint: %s\n", usb_ss_ep->name);
  1663 +
  1664 + dev_dbg(&usb_ss->dev, "QUEUE(%02X) %d\n",
  1665 + ep->desc->bEndpointAddress, request->length);
  1666 +
  1667 + ret = usb_gadget_map_request(&usb_ss->gadget, request,
  1668 + ep->desc->bEndpointAddress & USB_DIR_IN);
  1669 +
  1670 + if (ret) {
  1671 + spin_unlock_irqrestore(&usb_ss->lock, flags);
  1672 + return ret;
  1673 + }
  1674 +
  1675 + empty_list = list_empty(&usb_ss_ep->request_list);
  1676 + list_add_tail(&request->list, &usb_ss_ep->request_list);
  1677 +
  1678 + if (!usb_ss->hw_configured_flag) {
  1679 + spin_unlock_irqrestore(&usb_ss->lock, flags);
  1680 + return 0;
  1681 + }
  1682 +
  1683 + if (empty_list) {
  1684 + if (!usb_ss_ep->stalled_flag)
  1685 + cdns_ep_run_transfer(usb_ss_ep);
  1686 + }
  1687 + spin_unlock_irqrestore(&usb_ss->lock, flags);
  1688 +
  1689 + return ret;
  1690 +}
  1691 +
  1692 +/**
  1693 + * usb_ss_gadget_ep_dequeue Remove request from transfer queue
  1694 + * @ep: endpoint object associated with request
  1695 + * @request: request object
  1696 + *
  1697 + * Returns 0 on success, error code elsewhere
  1698 + */
  1699 +static int usb_ss_gadget_ep_dequeue(struct usb_ep *ep,
  1700 + struct usb_request *request)
  1701 +{
  1702 + struct usb_ss_endpoint *usb_ss_ep =
  1703 + to_usb_ss_ep(ep);
  1704 + struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss;
  1705 + unsigned long flags;
  1706 +
  1707 + spin_lock_irqsave(&usb_ss->lock, flags);
  1708 + if (!usb_ss->start_gadget) {
  1709 + dev_dbg(&usb_ss->dev,
  1710 + "DEQUEUE at disconnection: %s\n", ep->name);
  1711 + spin_unlock_irqrestore(&usb_ss->lock, flags);
  1712 + return 0;
  1713 + }
  1714 + dev_dbg(&usb_ss->dev, "DEQUEUE(%02X) %d\n",
  1715 + usb_ss_ep->address, request->length);
  1716 + usb_gadget_unmap_request(&usb_ss->gadget, request,
  1717 + usb_ss_ep->address & USB_DIR_IN);
  1718 + request->status = -ECONNRESET;
  1719 +
  1720 + if (usb_ss_ep->address)
  1721 + list_del(&request->list);
  1722 +
  1723 + if (request->complete) {
  1724 + spin_unlock(&usb_ss->lock);
  1725 + request->complete(ep, request);
  1726 + spin_lock(&usb_ss->lock);
  1727 + }
  1728 +
  1729 + spin_unlock_irqrestore(&usb_ss->lock, flags);
  1730 + return 0;
  1731 +}
  1732 +
  1733 +/**
  1734 + * usb_ss_gadget_ep_set_halt Sets/clears stall on selected endpoint
  1735 + * @ep: endpoint object to set/clear stall on
  1736 + * @value: 1 for set stall, 0 for clear stall
  1737 + *
  1738 + * Returns 0 on success, error code elsewhere
  1739 + */
  1740 +static int usb_ss_gadget_ep_set_halt(struct usb_ep *ep, int value)
  1741 +{
  1742 + struct usb_ss_endpoint *usb_ss_ep =
  1743 + to_usb_ss_ep(ep);
  1744 + struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss;
  1745 + unsigned long flags;
  1746 +
  1747 + /* return error when endpoint disabled */
  1748 + if (!usb_ss_ep->enabled)
  1749 + return -EPERM;
  1750 +
  1751 + /* if actual transfer is pending defer setting stall on this endpoint */
  1752 + if (usb_ss_ep->hw_pending_flag && value) {
  1753 + usb_ss_ep->stalled_flag = 1;
  1754 + return 0;
  1755 + }
  1756 +
  1757 + dev_dbg(&usb_ss->dev, "HALT(%02X) %d\n", usb_ss_ep->address, value);
  1758 +
  1759 + spin_lock_irqsave(&usb_ss->lock, flags);
  1760 +
  1761 + select_ep(usb_ss, ep->desc->bEndpointAddress);
  1762 + if (value) {
  1763 + cdns_ep_stall_flush(usb_ss_ep);
  1764 + } else {
  1765 + /*
  1766 + * TODO:
  1767 + * epp->wedgeFlag = 0;
  1768 + */
  1769 + usb_ss_ep->wedge_flag = 0;
  1770 + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd,
  1771 + EP_CMD__CSTALL__MASK | EP_CMD__EPRST__MASK);
  1772 + /* wait for EPRST cleared */
  1773 + while (gadget_readl(usb_ss,
  1774 + &usb_ss->regs->ep_cmd) & EP_CMD__EPRST__MASK)
  1775 + ;
  1776 + usb_ss_ep->stalled_flag = 0;
  1777 + }
  1778 + usb_ss_ep->hw_pending_flag = 0;
  1779 +
  1780 + spin_unlock_irqrestore(&usb_ss->lock, flags);
  1781 +
  1782 + return 0;
  1783 +}
  1784 +
  1785 +/**
  1786 + * usb_ss_gadget_ep_set_wedge Set wedge on selected endpoint
  1787 + * @ep: endpoint object
  1788 + *
  1789 + * Returns 0
  1790 + */
  1791 +static int usb_ss_gadget_ep_set_wedge(struct usb_ep *ep)
  1792 +{
  1793 + struct usb_ss_endpoint *usb_ss_ep = to_usb_ss_ep(ep);
  1794 + struct usb_ss_dev __maybe_unused *usb_ss = usb_ss_ep->usb_ss;
  1795 +
  1796 + dev_dbg(&usb_ss->dev, "WEDGE(%02X)\n", usb_ss_ep->address);
  1797 + usb_ss_gadget_ep_set_halt(ep, 1);
  1798 + usb_ss_ep->wedge_flag = 1;
  1799 + return 0;
  1800 +}
  1801 +
  1802 +static const struct usb_ep_ops usb_ss_gadget_ep0_ops = {
  1803 + .enable = usb_ss_gadget_ep0_enable,
  1804 + .disable = usb_ss_gadget_ep0_disable,
  1805 + .alloc_request = usb_ss_gadget_ep_alloc_request,
  1806 + .free_request = usb_ss_gadget_ep_free_request,
  1807 + .queue = usb_ss_gadget_ep0_queue,
  1808 + .dequeue = usb_ss_gadget_ep_dequeue,
  1809 + .set_halt = usb_ss_gadget_ep0_set_halt,
  1810 + .set_wedge = usb_ss_gadget_ep_set_wedge,
  1811 +};
  1812 +
  1813 +static const struct usb_ep_ops usb_ss_gadget_ep_ops = {
  1814 + .enable = usb_ss_gadget_ep_enable,
  1815 + .disable = usb_ss_gadget_ep_disable,
  1816 + .alloc_request = usb_ss_gadget_ep_alloc_request,
  1817 + .free_request = usb_ss_gadget_ep_free_request,
  1818 + .queue = usb_ss_gadget_ep_queue,
  1819 + .dequeue = usb_ss_gadget_ep_dequeue,
  1820 + .set_halt = usb_ss_gadget_ep_set_halt,
  1821 + .set_wedge = usb_ss_gadget_ep_set_wedge,
  1822 +};
  1823 +
  1824 +/**
  1825 + * usb_ss_gadget_get_frame Returns number of actual ITP frame
  1826 + * @gadget: gadget object
  1827 + *
  1828 + * Returns number of actual ITP frame
  1829 + */
  1830 +static int usb_ss_gadget_get_frame(struct usb_gadget *gadget)
  1831 +{
  1832 + struct usb_ss_dev *usb_ss = gadget_to_usb_ss(gadget);
  1833 +
  1834 + dev_dbg(&usb_ss->dev, "usb_ss_gadget_get_frame\n");
  1835 + return gadget_readl(usb_ss, &usb_ss->regs->usb_iptn);
  1836 +}
  1837 +
  1838 +static int usb_ss_gadget_wakeup(struct usb_gadget *gadget)
  1839 +{
  1840 + struct usb_ss_dev __maybe_unused *usb_ss = gadget_to_usb_ss(gadget);
  1841 +
  1842 + dev_dbg(&usb_ss->dev, "usb_ss_gadget_wakeup\n");
  1843 + return 0;
  1844 +}
  1845 +
  1846 +static int usb_ss_gadget_set_selfpowered(struct usb_gadget *gadget,
  1847 + int is_selfpowered)
  1848 +{
  1849 + struct usb_ss_dev __maybe_unused *usb_ss = gadget_to_usb_ss(gadget);
  1850 +
  1851 + dev_dbg(&usb_ss->dev, "usb_ss_gadget_set_selfpowered: %d\n",
  1852 + is_selfpowered);
  1853 + return 0;
  1854 +}
  1855 +
  1856 +static int usb_ss_gadget_pullup(struct usb_gadget *gadget, int is_on)
  1857 +{
  1858 + struct usb_ss_dev *usb_ss = gadget_to_usb_ss(gadget);
  1859 +
  1860 + if (!usb_ss->start_gadget)
  1861 + return 0;
  1862 +
  1863 + dev_dbg(&usb_ss->dev, "usb_ss_gadget_pullup: %d\n", is_on);
  1864 +
  1865 + if (is_on)
  1866 + gadget_writel(usb_ss, &usb_ss->regs->usb_conf,
  1867 + USB_CONF__DEVEN__MASK);
  1868 + else
  1869 + gadget_writel(usb_ss, &usb_ss->regs->usb_conf,
  1870 + USB_CONF__DEVDS__MASK);
  1871 +
  1872 + return 0;
  1873 +}
  1874 +
  1875 +/**
  1876 + * usb_ss_gadget_udc_start Gadget start
  1877 + * @gadget: gadget object
  1878 + * @driver: driver which operates on this gadget
  1879 + *
  1880 + * Returns 0 on success, error code elsewhere
  1881 + */
  1882 +static int usb_ss_gadget_udc_start(struct usb_gadget *gadget,
  1883 + struct usb_gadget_driver *driver)
  1884 +{
  1885 + struct usb_ss_dev *usb_ss = gadget_to_usb_ss(gadget);
  1886 + unsigned long flags;
  1887 +
  1888 + if (usb_ss->gadget_driver) {
  1889 + dev_err(&usb_ss->dev, "%s is already bound\n",
  1890 + usb_ss->gadget.name);
  1891 + return -EBUSY;
  1892 + }
  1893 +
  1894 + dev_dbg(&usb_ss->dev, "%s begins\n", __func__);
  1895 +
  1896 + spin_lock_irqsave(&usb_ss->lock, flags);
  1897 + usb_ss->gadget_driver = driver;
  1898 + if (!usb_ss->start_gadget) {
  1899 + spin_unlock_irqrestore(&usb_ss->lock, flags);
  1900 + return 0;
  1901 + }
  1902 +
  1903 + __cdns3_gadget_start(usb_ss);
  1904 + spin_unlock_irqrestore(&usb_ss->lock, flags);
  1905 + dev_dbg(&usb_ss->dev, "%s ends\n", __func__);
  1906 +
  1907 + return 0;
  1908 +}
  1909 +
  1910 +/**
  1911 + * usb_ss_gadget_udc_stop Stops gadget
  1912 + * @gadget: gadget object
  1913 + *
  1914 + * Returns 0
  1915 + */
  1916 +static int usb_ss_gadget_udc_stop(struct usb_gadget *gadget)
  1917 +{
  1918 + struct usb_ss_dev *usb_ss = gadget_to_usb_ss(gadget);
  1919 + struct usb_ep *ep;
  1920 + struct usb_ss_endpoint *usb_ss_ep;
  1921 + int i;
  1922 + u32 bEndpointAddress;
  1923 +
  1924 + usb_ss->gadget_driver = NULL;
  1925 + if (!usb_ss->start_gadget)
  1926 + return 0;
  1927 +
  1928 + list_for_each_entry(ep, &usb_ss->gadget.ep_list, ep_list) {
  1929 + usb_ss_ep = to_usb_ss_ep(ep);
  1930 + bEndpointAddress = usb_ss_ep->num | usb_ss_ep->dir;
  1931 + usb_ss_ep->used = false;
  1932 + select_ep(usb_ss, bEndpointAddress);
  1933 + gadget_writel(usb_ss, &usb_ss->regs->ep_cmd,
  1934 + EP_CMD__EPRST__MASK);
  1935 + while (gadget_readl(usb_ss, &usb_ss->regs->ep_cmd)
  1936 + & EP_CMD__EPRST__MASK)
  1937 + ;
  1938 + }
  1939 +
  1940 + /* disable interrupt for device */
  1941 + gadget_writel(usb_ss, &usb_ss->regs->usb_ien, 0);
  1942 + gadget_writel(usb_ss, &usb_ss->regs->usb_conf, USB_CONF__DEVDS__MASK);
  1943 +
  1944 + for (i = 0; i < usb_ss->ep_nums ; i++)
  1945 + usb_ss_free_trb_pool(usb_ss->eps[i]);
  1946 +
  1947 + return 0;
  1948 +}
  1949 +
  1950 +static const struct usb_gadget_ops usb_ss_gadget_ops = {
  1951 + .get_frame = usb_ss_gadget_get_frame,
  1952 + .wakeup = usb_ss_gadget_wakeup,
  1953 + .set_selfpowered = usb_ss_gadget_set_selfpowered,
  1954 + .pullup = usb_ss_gadget_pullup,
  1955 + .udc_start = usb_ss_gadget_udc_start,
  1956 + .udc_stop = usb_ss_gadget_udc_stop,
  1957 + .match_ep = usb_ss_gadget_match_ep,
  1958 +
  1959 +};
  1960 +
  1961 +/**
  1962 + * usb_ss_init_ep Initializes software endpoints of gadget
  1963 + * @usb_ss: extended gadget object
  1964 + *
  1965 + * Returns 0 on success, error code elsewhere
  1966 + */
  1967 +static int usb_ss_init_ep(struct usb_ss_dev *usb_ss)
  1968 +{
  1969 + struct usb_ss_endpoint *usb_ss_ep;
  1970 + u32 ep_enabled_reg, iso_ep_reg, bulk_ep_reg;
  1971 + int i;
  1972 + int ep_reg_pos, ep_dir, ep_number;
  1973 + int found_endpoints = 0;
  1974 +
  1975 + /* Read it from USB_CAP3 to USB_CAP5 */
  1976 + ep_enabled_reg = 0x00ff00ff;
  1977 + iso_ep_reg = 0x00fe00fe;
  1978 + bulk_ep_reg = 0x00fe00fe;
  1979 +
  1980 + dev_dbg(&usb_ss->dev, "Initializing non-zero endpoints\n");
  1981 + dev_dbg(&usb_ss->dev,
  1982 + "ep_enabled_reg: 0x%x, iso_ep_reg: 0x%x, bulk_ep_reg:0x%x\n",
  1983 + ep_enabled_reg, iso_ep_reg, bulk_ep_reg);
  1984 +
  1985 + for (i = 0; i < USB_SS_ENDPOINTS_MAX_COUNT; i++) {
  1986 + ep_number = (i / 2) + 1;
  1987 + ep_dir = i % 2;
  1988 + ep_reg_pos = (16 * ep_dir) + ep_number;
  1989 +
  1990 + if (!(ep_enabled_reg & (1uL << ep_reg_pos)))
  1991 + continue;
  1992 +
  1993 + /* create empty endpoint object */
  1994 + usb_ss_ep = devm_kzalloc(&usb_ss->dev, sizeof(*usb_ss_ep),
  1995 + GFP_KERNEL);
  1996 + if (!usb_ss_ep)
  1997 + return -ENOMEM;
  1998 +
  1999 + /* set parent of endpoint object */
  2000 + usb_ss_ep->usb_ss = usb_ss;
  2001 +
  2002 + /* set index of endpoint in endpoints container */
  2003 + usb_ss->eps[found_endpoints++] = usb_ss_ep;
  2004 +
  2005 + /* set name of endpoint */
  2006 + snprintf(usb_ss_ep->name, sizeof(usb_ss_ep->name), "ep%d%s",
  2007 + ep_number, !!ep_dir ? "in" : "out");
  2008 + usb_ss_ep->endpoint.name = usb_ss_ep->name;
  2009 + dev_dbg(&usb_ss->dev, "Initializing endpoint: %s\n",
  2010 + usb_ss_ep->name);
  2011 +
  2012 + usb_ep_set_maxpacket_limit(&usb_ss_ep->endpoint,
  2013 + ENDPOINT_MAX_PACKET_LIMIT);
  2014 + usb_ss_ep->endpoint.max_streams = ENDPOINT_MAX_STREAMS;
  2015 + usb_ss_ep->endpoint.ops = &usb_ss_gadget_ep_ops;
  2016 + if (ep_dir)
  2017 + usb_ss_ep->caps.dir_in = 1;
  2018 + else
  2019 + usb_ss_ep->caps.dir_out = 1;
  2020 +
  2021 + /* check endpoint type */
  2022 + if (iso_ep_reg & (1uL << ep_reg_pos))
  2023 + usb_ss_ep->caps.type_iso = 1;
  2024 +
  2025 + if (bulk_ep_reg & (1uL << ep_reg_pos)) {
  2026 + usb_ss_ep->caps.type_bulk = 1;
  2027 + usb_ss_ep->caps.type_int = 1;
  2028 + usb_ss_ep->endpoint.maxburst = 15;
  2029 + }
  2030 +
  2031 + list_add_tail(&usb_ss_ep->endpoint.ep_list,
  2032 + &usb_ss->gadget.ep_list);
  2033 + INIT_LIST_HEAD(&usb_ss_ep->request_list);
  2034 + INIT_LIST_HEAD(&usb_ss_ep->ep_match_pending_list);
  2035 + }
  2036 + usb_ss->ep_nums = found_endpoints;
  2037 + return 0;
  2038 +}
  2039 +
  2040 +/**
  2041 + * usb_ss_init_ep0 Initializes software endpoint 0 of gadget
  2042 + * @usb_ss: extended gadget object
  2043 + *
  2044 + * Returns 0 on success, error code elsewhere
  2045 + */
  2046 +static int usb_ss_init_ep0(struct usb_ss_dev *usb_ss)
  2047 +{
  2048 + struct usb_ss_endpoint *ep0;
  2049 +
  2050 + dev_dbg(&usb_ss->dev, "Initializing EP0\n");
  2051 + ep0 = devm_kzalloc(&usb_ss->dev, sizeof(struct usb_ss_endpoint),
  2052 + GFP_KERNEL);
  2053 +
  2054 + if (!ep0)
  2055 + return -ENOMEM;
  2056 +
  2057 + /* fill CDNS fields */
  2058 + ep0->usb_ss = usb_ss;
  2059 + sprintf(ep0->name, "ep0");
  2060 +
  2061 + /* fill linux fields */
  2062 + ep0->endpoint.ops = &usb_ss_gadget_ep0_ops;
  2063 + ep0->endpoint.maxburst = 1;
  2064 + usb_ep_set_maxpacket_limit(&ep0->endpoint, ENDPOINT0_MAX_PACKET_LIMIT);
  2065 + ep0->address = 0;
  2066 + ep0->enabled = 1;
  2067 + ep0->caps.type_control = 1;
  2068 + ep0->caps.dir_in = 1;
  2069 + ep0->caps.dir_out = 1;
  2070 + ep0->endpoint.name = ep0->name;
  2071 + ep0->endpoint.desc = &cdns3_gadget_ep0_desc;
  2072 +
  2073 + usb_ss->gadget.ep0 = &ep0->endpoint;
  2074 +
  2075 + return 0;
  2076 +}
  2077 +
  2078 +static void cdns3_gadget_release(struct device *dev)
  2079 +{
  2080 + struct usb_ss_dev *usb_ss = container_of(dev, struct usb_ss_dev, dev);
  2081 +
  2082 + kfree(usb_ss);
  2083 +}
  2084 +
  2085 +static int __cdns3_gadget_init(struct cdns3 *cdns)
  2086 +{
  2087 + struct usb_ss_dev *usb_ss;
  2088 + int ret;
  2089 + struct device *dev;
  2090 +
  2091 + usb_ss = kzalloc(sizeof(*usb_ss), GFP_KERNEL);
  2092 + if (!usb_ss)
  2093 + return -ENOMEM;
  2094 +
  2095 + dev = &usb_ss->dev;
  2096 + dev->release = cdns3_gadget_release;
  2097 + dev->parent = cdns->dev;
  2098 + dev_set_name(dev, "gadget-cdns3-dev");
  2099 + cdns->gadget_dev = dev;
  2100 + usb_ss->sysdev = cdns->dev;
  2101 + ret = device_register(dev);
  2102 + if (ret)
  2103 + goto err1;
  2104 +
  2105 + usb_ss->regs = cdns->dev_regs;
  2106 +
  2107 + /* fill gadget fields */
  2108 + usb_ss->gadget.ops = &usb_ss_gadget_ops;
  2109 + usb_ss->gadget.max_speed = USB_SPEED_SUPER;
  2110 + usb_ss->gadget.speed = USB_SPEED_UNKNOWN;
  2111 + usb_ss->gadget.name = "cdns3-gadget";
  2112 + usb_ss->is_connected = 0;
  2113 + spin_lock_init(&usb_ss->lock);
  2114 +
  2115 + usb_ss->in_standby_mode = 1;
  2116 +
  2117 + /* initialize endpoint container */
  2118 + INIT_LIST_HEAD(&usb_ss->gadget.ep_list);
  2119 + INIT_LIST_HEAD(&usb_ss->ep_match_list);
  2120 + ret = usb_ss_init_ep0(usb_ss);
  2121 + if (ret) {
  2122 + dev_err(dev, "Failed to create endpoint 0\n");
  2123 + ret = -ENOMEM;
  2124 + goto err2;
  2125 + }
  2126 +
  2127 + ret = usb_ss_init_ep(usb_ss);
  2128 + if (ret) {
  2129 + dev_err(dev, "Failed to create non zero endpoints\n");
  2130 + ret = -ENOMEM;
  2131 + goto err2;
  2132 + }
  2133 +
  2134 + /* allocate memory for default endpoint TRB */
  2135 + usb_ss->trb_ep0 = (u32 *)dma_alloc_coherent(20, (unsigned long *)&usb_ss->trb_ep0_dma);
  2136 + if (!usb_ss->trb_ep0) {
  2137 + dev_err(dev, "Failed to allocate memory for ep0 TRB\n");
  2138 + ret = -ENOMEM;
  2139 + goto err2;
  2140 + }
  2141 +
  2142 + /* allocate memory for setup packet buffer */
  2143 + usb_ss->setup = (u8 *)dma_alloc_coherent(8, (unsigned long *)&usb_ss->setup_dma);
  2144 + if (!usb_ss->setup) {
  2145 + dev_err(dev, "Failed to allocate memory for SETUP buffer\n");
  2146 + ret = -ENOMEM;
  2147 + goto err3;
  2148 + }
  2149 +
  2150 + /* add USB gadget device */
  2151 + ret = usb_add_gadget_udc(&usb_ss->dev, &usb_ss->gadget);
  2152 + if (ret < 0) {
  2153 + dev_err(dev, "Failed to register USB device controller\n");
  2154 + goto err4;
  2155 + }
  2156 +
  2157 + return 0;
  2158 +
  2159 +err4:
  2160 + dma_free_coherent(usb_ss->setup);
  2161 +err3:
  2162 + dma_free_coherent(usb_ss->trb_ep0);
  2163 +err2:
  2164 +err1:
  2165 + cdns->gadget_dev = NULL;
  2166 +
  2167 + return ret;
  2168 +}
  2169 +
  2170 +/**
  2171 + * cdns3_gadget_remove: parent must call this to remove UDC
  2172 + *
  2173 + * cdns: cdns3 instance
  2174 + *
  2175 + */
  2176 +void cdns3_gadget_remove(struct cdns3 *cdns)
  2177 +{
  2178 + struct usb_ss_dev *usb_ss;
  2179 +
  2180 + if (!cdns->roles[CDNS3_ROLE_GADGET])
  2181 + return;
  2182 +
  2183 + usb_ss = container_of(cdns->gadget_dev, struct usb_ss_dev, dev);
  2184 + usb_del_gadget_udc(&usb_ss->gadget);
  2185 + dma_free_coherent(usb_ss->setup);
  2186 + dma_free_coherent(usb_ss->trb_ep0);
  2187 + device_unregister(cdns->gadget_dev);
  2188 + cdns->gadget_dev = NULL;
  2189 +}
  2190 +
  2191 +static void __cdns3_gadget_start(struct usb_ss_dev *usb_ss)
  2192 +{
  2193 + /* configure endpoint 0 hardware */
  2194 + cdns_ep0_config(usb_ss);
  2195 +
  2196 + /* enable interrupts for endpoint 0 (in and out) */
  2197 + gadget_writel(usb_ss, &usb_ss->regs->ep_ien,
  2198 + EP_IEN__EOUTEN0__MASK | EP_IEN__EINEN0__MASK);
  2199 +
  2200 + /* enable interrupt for device */
  2201 + gadget_writel(usb_ss, &usb_ss->regs->usb_ien,
  2202 + USB_IEN__U2RESIEN__MASK
  2203 + | USB_ISTS__DIS2I__MASK
  2204 + | USB_IEN__CON2IEN__MASK
  2205 + | USB_IEN__UHRESIEN__MASK
  2206 + | USB_IEN__UWRESIEN__MASK
  2207 + | USB_IEN__DISIEN__MASK
  2208 + | USB_IEN__CONIEN__MASK
  2209 + | USB_IEN__U3EXTIEN__MASK
  2210 + | USB_IEN__L2ENTIEN__MASK
  2211 + | USB_IEN__L2EXTIEN__MASK);
  2212 +
  2213 + gadget_writel(usb_ss, &usb_ss->regs->usb_conf,
  2214 + USB_CONF__CLK2OFFDS__MASK
  2215 +#ifdef CONFIG_USB_CDNS3_GADGET_FORCE_HIGHSPEED
  2216 + | USB_CONF__USB3DIS__MASK
  2217 +#endif
  2218 + | USB_CONF__L1DS__MASK);
  2219 +
  2220 + gadget_writel(usb_ss, &usb_ss->regs->usb_conf,
  2221 + USB_CONF__U1DS__MASK
  2222 + | USB_CONF__U2DS__MASK
  2223 + /*
  2224 + * TODO:
  2225 + * | USB_CONF__L1EN__MASK
  2226 + */
  2227 + );
  2228 +
  2229 + gadget_writel(usb_ss, &usb_ss->regs->usb_conf, USB_CONF__DEVEN__MASK);
  2230 +
  2231 + gadget_writel(usb_ss, &usb_ss->regs->dbg_link1,
  2232 + DBG_LINK1__LFPS_MIN_GEN_U1_EXIT_SET__MASK |
  2233 + DBG_LINK1__LFPS_MIN_GEN_U1_EXIT__WRITE(0x3C));
  2234 +}
  2235 +
  2236 +static int cdns3_gadget_start(struct cdns3 *cdns)
  2237 +{
  2238 + struct usb_ss_dev *usb_ss = container_of(cdns->gadget_dev,
  2239 + struct usb_ss_dev, dev);
  2240 + unsigned long flags;
  2241 +
  2242 + dev_dbg(&usb_ss->dev, "%s begins\n", __func__);
  2243 +
  2244 + pm_runtime_get_sync(cdns->dev);
  2245 + spin_lock_irqsave(&usb_ss->lock, flags);
  2246 + usb_ss->start_gadget = 1;
  2247 + if (!usb_ss->gadget_driver) {
  2248 + spin_unlock_irqrestore(&usb_ss->lock, flags);
  2249 + return 0;
  2250 + }
  2251 +
  2252 + __cdns3_gadget_start(usb_ss);
  2253 + usb_ss->in_standby_mode = 0;
  2254 + spin_unlock_irqrestore(&usb_ss->lock, flags);
  2255 + dev_dbg(&usb_ss->dev, "%s ends\n", __func__);
  2256 +
  2257 + return 0;
  2258 +}
  2259 +
  2260 +static void __cdns3_gadget_stop(struct cdns3 *cdns)
  2261 +{
  2262 + struct usb_ss_dev *usb_ss;
  2263 + unsigned long flags;
  2264 +
  2265 + usb_ss = container_of(cdns->gadget_dev, struct usb_ss_dev, dev);
  2266 + if (usb_ss->gadget_driver)
  2267 + usb_ss->gadget_driver->disconnect(&usb_ss->gadget);
  2268 + usb_gadget_disconnect(&usb_ss->gadget);
  2269 + spin_lock_irqsave(&usb_ss->lock, flags);
  2270 + /* disable interrupt for device */
  2271 + gadget_writel(usb_ss, &usb_ss->regs->usb_ien, 0);
  2272 + gadget_writel(usb_ss, &usb_ss->regs->usb_conf, USB_CONF__DEVDS__MASK);
  2273 + usb_ss->start_gadget = 0;
  2274 + spin_unlock_irqrestore(&usb_ss->lock, flags);
  2275 +}
  2276 +
  2277 +static void cdns3_gadget_stop(struct cdns3 *cdns)
  2278 +{
  2279 + if (cdns->role == CDNS3_ROLE_GADGET)
  2280 + __cdns3_gadget_stop(cdns);
  2281 +}
  2282 +
  2283 +/**
  2284 + * cdns3_gadget_init - initialize device structure
  2285 + *
  2286 + * cdns: cdns3 instance
  2287 + *
  2288 + * This function initializes the gadget.
  2289 + */
  2290 +int cdns3_gadget_init(struct cdns3 *cdns)
  2291 +{
  2292 + struct cdns3_role_driver *rdrv;
  2293 +
  2294 + rdrv = devm_kzalloc(cdns->dev, sizeof(*rdrv), GFP_KERNEL);
  2295 + if (!rdrv)
  2296 + return -ENOMEM;
  2297 +
  2298 + rdrv->start = cdns3_gadget_start;
  2299 + rdrv->stop = cdns3_gadget_stop;
  2300 + rdrv->irq = cdns_irq_handler_thread;
  2301 + rdrv->name = "gadget";
  2302 + cdns->roles[CDNS3_ROLE_GADGET] = rdrv;
  2303 + return __cdns3_gadget_init(cdns);
  2304 +}
drivers/usb/cdns3/gadget.h
Diff comments   View file @ db2cc87
  1 +/*
  2 + * Copyright (C) 2016 Cadence Design Systems - http://www.cadence.com
  3 + * Copyright 2018 NXP
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +#ifndef __DRIVERS_CDNS3_GADGET
  8 +#define __DRIVERS_CDNS3_GADGET
  9 +
  10 +#include "dev-regs-map.h"
  11 +
  12 +#if IS_ENABLED(CONFIG_USB_CDNS_MISC)
  13 +#include "cdns_misc.h"
  14 +#endif
  15 +
  16 +#define gadget_to_usb_ss(g) \
  17 + (container_of(g, struct usb_ss_dev, gadget))
  18 +
  19 +#define to_usb_ss_ep(ep) \
  20 + (container_of(ep, struct usb_ss_endpoint, endpoint))
  21 +
  22 +#define ep_to_usb_ss_ep(ep) \
  23 + (container_of(ep, struct usb_ss_endpoint, endpoint))
  24 +
  25 +/*-------------------------------------------------------------------------*/
  26 +/* TRB macros */
  27 +
  28 +/* Common TRB fields */
  29 +#define TRB_SET_CYCLE_BIT 1uL
  30 +#define TRB_SET_CHAIN_BIT 0x10
  31 +
  32 +/* offset 0 */
  33 +#define TRB_DATA_BUFFER_POINTER_MASK 0xFFFFFFFF
  34 +#define TRB_SET_DATA_BUFFER_POINTER(p) (p & TRB_DATA_BUFFER_POINTER_MASK)
  35 +
  36 +/* offset 4 */
  37 +#define TRB_TRANSFER_LENGTH_MASK 0x1FFFF
  38 +#define TRB_SET_TRANSFER_LENGTH(l) (l & TRB_TRANSFER_LENGTH_MASK)
  39 +
  40 +#define TRB_BURST_LENGTH_MASK 0xFF
  41 +#define TRB_SET_BURST_LENGTH(l) ((l & TRB_BURST_LENGTH_MASK) << 24)
  42 +
  43 +/* offset 8 */
  44 +#define TRB_SET_INT_ON_SHORT_PACKET 0x04
  45 +#define TRB_SET_FIFO_MODE 0x08
  46 +#define TRB_SET_INT_ON_COMPLETION 0x20
  47 +
  48 +#define TRB_TYPE_NORMAL 0x400
  49 +
  50 +#define TRB_STREAM_ID_MASK 0xFFFF
  51 +#define TRB_SET_STREAM_ID(sid) ((sid & TRB_STREAM_ID_MASK) << 16)
  52 +
  53 +/*-------------------------------------------------------------------------*/
  54 +/* Driver numeric constants */
  55 +
  56 +
  57 +#define DEVICE_ADDRESS_MAX 127
  58 +
  59 +/* Endpoint init values */
  60 +#define ENDPOINT_MAX_PACKET_LIMIT 1024
  61 +#define ENDPOINT_MAX_STREAMS 15
  62 +
  63 +#define ENDPOINT0_MAX_PACKET_LIMIT 512
  64 +
  65 +/* All endpoints except EP0 */
  66 +#define USB_SS_ENDPOINTS_MAX_COUNT 30
  67 +
  68 +#define USB_SS_TRBS_NUM 32
  69 +
  70 +/* Standby mode */
  71 +#define STB_CLK_SWITCH_DONE_MASK 0x200
  72 +#define STB_CLK_SWITCH_EN_MASK 0x100
  73 +#define STB_CLK_SWITCH_EN_SHIFT 8
  74 +
  75 +#define ENDPOINT_MAX_PACKET_SIZE_0 0
  76 +#define ENDPOINT_MAX_PACKET_SIZE_8 8
  77 +#define ENDPOINT_MAX_PACKET_SIZE_64 64
  78 +#define ENDPOINT_MAX_PACKET_SIZE_512 512
  79 +#define ENDPOINT_MAX_PACKET_SIZE_1023 1023
  80 +#define ENDPOINT_MAX_PACKET_SIZE_1024 1024
  81 +
  82 +#define SS_LINK_STATE_U3 3
  83 +#define FSHS_LPM_STATE_L2 2
  84 +
  85 +#define ADDR_MODULO_8 8
  86 +
  87 +#define INTERRUPT_MASK 0xFFFFFFFF
  88 +
  89 +#define ACTUAL_TRANSFERRED_BYTES_MASK 0x1FFFF
  90 +
  91 +#define ENDPOINT_DIR_MASK 0x80
  92 +
  93 +/*-------------------------------------------------------------------------*/
  94 +
  95 +/**
  96 + * IS_REG_REQUIRING_ACTIVE_REF_CLOCK - Macro checks if desired
  97 + * register requires active clock, it involves such registers as:
  98 + * EP_CFG, EP_TR_ADDR, EP_CMD, EP_SEL, USB_CONF
  99 + * @usb_ss: extended gadget object
  100 + * @reg: register address
  101 + */
  102 +#define IS_REG_REQUIRING_ACTIVE_REF_CLOCK(usb_ss, reg) (!reg || \
  103 + (reg >= &usb_ss->regs->ep_sel && reg <= &usb_ss->regs->ep_cmd))
  104 +
  105 +/**
  106 + * CAST_EP_REG_POS_TO_INDEX - Macro converts bit position of ep_ists register to
  107 + * index of endpoint object in usb_ss_dev.eps[] container
  108 + * @i: bit position of endpoint for which endpoint object is required
  109 + *
  110 + * Remember that endpoint container doesn't contain default endpoint
  111 + */
  112 +#define CAST_EP_REG_POS_TO_INDEX(i) (((i) / 16) + ((((i) % 16) - 2) * 2))
  113 +
  114 +/**
  115 + * CAST_EP_ADDR_TO_INDEX - Macro converts endpoint address to
  116 + * index of endpoint object in usb_ss_dev.eps[] container
  117 + * @ep_addr: endpoint address for which endpoint object is required
  118 + *
  119 + * Remember that endpoint container doesn't contain default endpoint
  120 + */
  121 +#define CAST_EP_ADDR_TO_INDEX(ep_addr) \
  122 + (((ep_addr & 0x7F) - 1) + ((ep_addr & 0x80) ? 1 : 0))
  123 +
  124 +/**
  125 + * CAST_EP_ADDR_TO_BIT_POS - Macro converts endpoint address to
  126 + * bit position in ep_ists register
  127 + * @ep_addr: endpoint address for which bit position is required
  128 + *
  129 + * Remember that endpoint container doesn't contain default endpoint
  130 + */
  131 +#define CAST_EP_ADDR_TO_BIT_POS(ep_addr) \
  132 + (((uint32_t)1 << (ep_addr & 0x7F)) << ((ep_addr & 0x80) ? 16 : 0))
  133 +
  134 +
  135 +#define CAST_INDEX_TO_EP_ADDR(index) \
  136 + ((index / 2 + 1) | ((index % 2) ? 0x80 : 0x00))
  137 +
  138 +/*-------------------------------------------------------------------------*/
  139 +/* Used structs */
  140 +
  141 +struct usb_ss_trb {
  142 + u32 offset0;
  143 + u32 offset4;
  144 + u32 offset8;
  145 +};
  146 +
  147 +struct usb_ss_dev;
  148 +
  149 +struct usb_ep_caps {
  150 + unsigned type_control:1;
  151 + unsigned type_iso:1;
  152 + unsigned type_bulk:1;
  153 + unsigned type_int:1;
  154 + unsigned dir_in:1;
  155 + unsigned dir_out:1;
  156 +};
  157 +
  158 +struct usb_ss_endpoint {
  159 + struct usb_ep endpoint;
  160 + struct list_head request_list;
  161 + struct list_head ep_match_pending_list;
  162 +
  163 + struct usb_ss_trb *trb_pool;
  164 + dma_addr_t trb_pool_dma;
  165 +
  166 + struct usb_ss_dev *usb_ss;
  167 + char name[20];
  168 + int hw_pending_flag;
  169 + int stalled_flag;
  170 + int wedge_flag;
  171 + void *cpu_addr;
  172 + dma_addr_t dma_addr;
  173 + u8 dir;
  174 + u8 num;
  175 + u8 type;
  176 + u8 address;
  177 + bool used;
  178 + bool enabled;
  179 + struct usb_ep_caps caps;
  180 +};
  181 +
  182 +struct usb_ss_dev {
  183 + struct device dev;
  184 + struct usbss_dev_register_block_type __iomem *regs;
  185 +
  186 + struct usb_gadget gadget;
  187 + struct usb_gadget_driver *gadget_driver;
  188 +
  189 + dma_addr_t setup_dma;
  190 + dma_addr_t trb_ep0_dma;
  191 + u32 *trb_ep0;
  192 + u8 *setup;
  193 +
  194 + struct usb_ss_endpoint *eps[USB_SS_ENDPOINTS_MAX_COUNT];
  195 + int ep_nums;
  196 + struct usb_request *actual_ep0_request;
  197 + int ep0_data_dir;
  198 + int hw_configured_flag;
  199 + int wake_up_flag;
  200 + u16 isoch_delay;
  201 + spinlock_t lock;
  202 +
  203 + unsigned is_connected:1;
  204 + unsigned in_standby_mode:1;
  205 +
  206 + u32 usb_ien;
  207 + u32 ep_ien;
  208 + int setup_pending;
  209 + struct device *sysdev;
  210 + bool start_gadget; /* The device mode is enabled */
  211 + struct list_head ep_match_list;
  212 +};
  213 +
  214 +#define OTG_STS_SELECTOR 0xF000 /* OTG status selector */
  215 +
  216 +#endif /* __DRIVERS_CDNS3_GADGET */
drivers/usb/cdns3/io.h
Diff comments   View file @ db2cc87
  1 +/*
  2 + * Copyright (C) 2016 Cadence Design Systems - https://www.cadence.com/
  3 + * Copyright 2018 NXP
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0
  6 + */
  7 +
  8 +#ifndef __DRIVERS_USB_CDNS_IO_H
  9 +#define __DRIVERS_USB_CDNS_IO_H
  10 +
  11 +#include <linux/io.h>
  12 +
  13 +static inline u32 cdns_readl(uint32_t __iomem *reg)
  14 +{
  15 + u32 value = 0;
  16 +
  17 + value = readl(reg);
  18 + return value;
  19 +}
  20 +
  21 +static inline void cdns_writel(uint32_t __iomem *reg, u32 value)
  22 +{
  23 + writel(value, reg);
  24 +}
  25 +
  26 +static inline void cdns_flush_cache(uintptr_t addr, int length)
  27 +{
  28 + flush_dcache_range(addr, addr + ROUND(length, ARCH_DMA_MINALIGN));
  29 +}
  30 +
  31 +#endif /* __DRIVERS_USB_CDNS_IO_H */
drivers/usb/cdns3/linux-compat.h
Diff comments   View file @ db2cc87
  1 +/*
  2 + * Copyright 2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0
  5 + *
  6 + */
  7 +
  8 +#ifndef __CDNS3_LINUX_COMPAT__
  9 +#define __CDNS3_LINUX_COMPAT__
  10 +
  11 +#define WARN(val, format, arg...) debug(format, ##arg)
  12 +#define dev_WARN(dev, format, arg...) debug(format, ##arg)
  13 +
  14 +static inline void *devm_kzalloc(struct device *dev, unsigned int size,
  15 + unsigned int flags)
  16 +{
  17 + return kzalloc(size, flags);
  18 +}
  19 +#endif
drivers/usb/gadget/epautoconf.c
Diff comments   View file @ db2cc87
... ... @@ -170,6 +170,10 @@
170 170 size = 64;
171 171 put_unaligned(cpu_to_le16(size), &desc->wMaxPacketSize);
172 172 }
  173 +
  174 + if (gadget->ops->match_ep)
  175 + return gadget->ops->match_ep(gadget, ep, desc);
  176 +
173 177 return 1;
174 178 }
175 179  
drivers/usb/gadget/gadget_chips.h
Diff comments   View file @ db2cc87
... ... @@ -149,6 +149,11 @@
149 149 #define gadget_is_dwc3(g) 0
150 150 #endif
151 151  
  152 +#ifdef CONFIG_USB_CDNS3_GADGET
  153 +#define gadget_is_cdns3(g) (!strcmp("cdns3-gadget", (g)->name))
  154 +#else
  155 +#define gadget_is_cdns3(g) 0
  156 +#endif
152 157  
153 158  
154 159 /*
... ... @@ -214,6 +219,8 @@
214 219 return 0x21;
215 220 else if (gadget_is_fotg210(gadget))
216 221 return 0x22;
  222 + else if (gadget_is_cdns3(gadget))
  223 + return 0x23;
217 224 return -ENOENT;
218 225 }
drivers/usb/gadget/udc/Makefile
Diff comments   View file @ db2cc87
... ... @@ -5,4 +5,5 @@
5 5 #
6 6  
7 7 obj-$(CONFIG_USB_DWC3_GADGET) += udc-core.o
  8 +obj-$(CONFIG_USB_CDNS3_GADGET) += udc-core.o
include/cdns3-uboot.h
Diff comments   View file @ db2cc87
  1 +/*
  2 + * Copyright 2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0
  5 + */
  6 +
  7 +#ifndef __CDNS3_UBOOT_H_
  8 +#define __CDNS3_UBOOT_H_
  9 +
  10 +#include <linux/usb/otg.h>
  11 +
  12 +struct cdns3_device {
  13 + unsigned long none_core_base;
  14 + unsigned long xhci_base;
  15 + unsigned long dev_base;
  16 + unsigned long phy_base;
  17 + unsigned long otg_base;
  18 + enum usb_dr_mode dr_mode;
  19 + int index;
  20 +};
  21 +
  22 +int cdns3_uboot_init(struct cdns3_device *dev);
  23 +void cdns3_uboot_exit(int index);
  24 +void cdns3_uboot_handle_interrupt(int index);
  25 +#endif /* __CDNS3_UBOOT_H_ */
include/linux/usb/gadget.h
Diff comments   View file @ db2cc87
... ... @@ -446,6 +446,9 @@
446 446 int (*udc_start)(struct usb_gadget *,
447 447 struct usb_gadget_driver *);
448 448 int (*udc_stop)(struct usb_gadget *);
  449 + int (*match_ep)(struct usb_gadget *,
  450 + struct usb_ep *,
  451 + struct usb_endpoint_descriptor *);
449 452 };
450 453  
451 454 /**