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Commit db402e005a7db7c60811deb199e0df3eec479601

Authored by Alexander Stein
Committed by Tom Rini
1 parent 4342557fad
Exists in v2017.01-smarct4x and in 33 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf-6.6.52-2.2.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

dwc2: Add dcache support 

This adds dcache support for dwc2. The DMA buffers must be DMA aligned and
is flushed for outgoing transactions before starting transfer. For
ingoing transactions it is invalidated after the transfer has finished.

Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
[trini: Update to apply again on top of DM patches]
Signed-off-by: Tom Rini <trini@konsulko.com>

Showing 1 changed file with 17 additions and 7 deletions Side-by-side Diff

drivers/usb/host/dwc2.c
Diff comments   View file @ db402e0
... ... @@ -27,8 +27,8 @@
27 27  
28 28 struct dwc2_priv {
29 29 #ifdef CONFIG_DM_USB
30   - uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(8);
31   - uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(8);
  30 + uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
  31 + uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
32 32 #else
33 33 uint8_t *aligned_buffer;
34 34 uint8_t *status_buffer;
... ... @@ -39,9 +39,11 @@
39 39 };
40 40  
41 41 #ifndef CONFIG_DM_USB
42   -/* We need doubleword-aligned buffers for DMA transfers */
43   -DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE, 8);
44   -DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE, 8);
  42 +/* We need cacheline-aligned buffers for DMA transfers and dcache support */
  43 +DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
  44 + ARCH_DMA_MINALIGN);
  45 +DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
  46 + ARCH_DMA_MINALIGN);
45 47  
46 48 static struct dwc2_priv local;
47 49 #endif
... ... @@ -821,8 +823,11 @@
821 823 &hc_regs->hctsiz);
822 824  
823 825 if (!in) {
824   - memcpy(priv->aligned_buffer, (char *)buffer + done,
825   - len);
  826 + memcpy(priv->aligned_buffer, (char *)buffer + done, len);
  827 +
  828 + flush_dcache_range((unsigned long)priv->aligned_buffer,
  829 + (unsigned long)((void *)priv->aligned_buffer +
  830 + roundup(len, ARCH_DMA_MINALIGN)));
826 831 }
827 832  
828 833 writel(phys_to_bus((unsigned long)priv->aligned_buffer),
... ... @@ -840,6 +845,11 @@
840 845  
841 846 if (in) {
842 847 xfer_len -= sub;
  848 +
  849 + invalidate_dcache_range((unsigned long)priv->aligned_buffer,
  850 + (unsigned long)((void *)priv->aligned_buffer +
  851 + roundup(xfer_len, ARCH_DMA_MINALIGN)));
  852 +
843 853 memcpy(buffer + done, priv->aligned_buffer, xfer_len);
844 854 if (sub)
845 855 stop_transfer = 1;