Commit db9e5e63bec7a0b1997b747161a3d667ed37525c
Committed by
Minkyu Kang
1 parent
dc993a65f4
Exists in
master
and in
54 other branches
Exynos: clock: Fix a bug in PLL lock check condition
The condition for testing of PLL getting locked was incorrect. Rectify this error in this patch. Reported-by: Alexei Fedorov <alexie.fedorov@arm.com> Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Showing 1 changed file with 7 additions and 7 deletions Inline Diff
board/samsung/smdk5250/clock_init.c
1 | /* | 1 | /* |
2 | * Clock setup for SMDK5250 board based on EXYNOS5 | 2 | * Clock setup for SMDK5250 board based on EXYNOS5 |
3 | * | 3 | * |
4 | * Copyright (C) 2012 Samsung Electronics | 4 | * Copyright (C) 2012 Samsung Electronics |
5 | * | 5 | * |
6 | * See file CREDITS for list of people who contributed to this | 6 | * See file CREDITS for list of people who contributed to this |
7 | * project. | 7 | * project. |
8 | * | 8 | * |
9 | * This program is free software; you can redistribute it and/or | 9 | * This program is free software; you can redistribute it and/or |
10 | * modify it under the terms of the GNU General Public License as | 10 | * modify it under the terms of the GNU General Public License as |
11 | * published by the Free Software Foundation; either version 2 of | 11 | * published by the Free Software Foundation; either version 2 of |
12 | * the License, or (at your option) any later version. | 12 | * the License, or (at your option) any later version. |
13 | * | 13 | * |
14 | * This program is distributed in the hope that it will be useful, | 14 | * This program is distributed in the hope that it will be useful, |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
17 | * GNU General Public License for more details. | 17 | * GNU General Public License for more details. |
18 | * | 18 | * |
19 | * You should have received a copy of the GNU General Public License | 19 | * You should have received a copy of the GNU General Public License |
20 | * along with this program; if not, write to the Free Software | 20 | * along with this program; if not, write to the Free Software |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
22 | * MA 02111-1307 USA | 22 | * MA 02111-1307 USA |
23 | */ | 23 | */ |
24 | 24 | ||
25 | #include <common.h> | 25 | #include <common.h> |
26 | #include <config.h> | 26 | #include <config.h> |
27 | #include <asm/io.h> | 27 | #include <asm/io.h> |
28 | #include <asm/arch/clk.h> | 28 | #include <asm/arch/clk.h> |
29 | #include <asm/arch/clock.h> | 29 | #include <asm/arch/clock.h> |
30 | #include <asm/arch/spl.h> | 30 | #include <asm/arch/spl.h> |
31 | 31 | ||
32 | #include "clock_init.h" | 32 | #include "clock_init.h" |
33 | #include "setup.h" | 33 | #include "setup.h" |
34 | 34 | ||
35 | DECLARE_GLOBAL_DATA_PTR; | 35 | DECLARE_GLOBAL_DATA_PTR; |
36 | 36 | ||
37 | struct arm_clk_ratios arm_clk_ratios[] = { | 37 | struct arm_clk_ratios arm_clk_ratios[] = { |
38 | { | 38 | { |
39 | .arm_freq_mhz = 600, | 39 | .arm_freq_mhz = 600, |
40 | 40 | ||
41 | .apll_mdiv = 0xc8, | 41 | .apll_mdiv = 0xc8, |
42 | .apll_pdiv = 0x4, | 42 | .apll_pdiv = 0x4, |
43 | .apll_sdiv = 0x1, | 43 | .apll_sdiv = 0x1, |
44 | 44 | ||
45 | .arm2_ratio = 0x0, | 45 | .arm2_ratio = 0x0, |
46 | .apll_ratio = 0x1, | 46 | .apll_ratio = 0x1, |
47 | .pclk_dbg_ratio = 0x1, | 47 | .pclk_dbg_ratio = 0x1, |
48 | .atb_ratio = 0x2, | 48 | .atb_ratio = 0x2, |
49 | .periph_ratio = 0x7, | 49 | .periph_ratio = 0x7, |
50 | .acp_ratio = 0x7, | 50 | .acp_ratio = 0x7, |
51 | .cpud_ratio = 0x1, | 51 | .cpud_ratio = 0x1, |
52 | .arm_ratio = 0x0, | 52 | .arm_ratio = 0x0, |
53 | }, { | 53 | }, { |
54 | .arm_freq_mhz = 800, | 54 | .arm_freq_mhz = 800, |
55 | 55 | ||
56 | .apll_mdiv = 0x64, | 56 | .apll_mdiv = 0x64, |
57 | .apll_pdiv = 0x3, | 57 | .apll_pdiv = 0x3, |
58 | .apll_sdiv = 0x0, | 58 | .apll_sdiv = 0x0, |
59 | 59 | ||
60 | .arm2_ratio = 0x0, | 60 | .arm2_ratio = 0x0, |
61 | .apll_ratio = 0x1, | 61 | .apll_ratio = 0x1, |
62 | .pclk_dbg_ratio = 0x1, | 62 | .pclk_dbg_ratio = 0x1, |
63 | .atb_ratio = 0x3, | 63 | .atb_ratio = 0x3, |
64 | .periph_ratio = 0x7, | 64 | .periph_ratio = 0x7, |
65 | .acp_ratio = 0x7, | 65 | .acp_ratio = 0x7, |
66 | .cpud_ratio = 0x2, | 66 | .cpud_ratio = 0x2, |
67 | .arm_ratio = 0x0, | 67 | .arm_ratio = 0x0, |
68 | }, { | 68 | }, { |
69 | .arm_freq_mhz = 1000, | 69 | .arm_freq_mhz = 1000, |
70 | 70 | ||
71 | .apll_mdiv = 0x7d, | 71 | .apll_mdiv = 0x7d, |
72 | .apll_pdiv = 0x3, | 72 | .apll_pdiv = 0x3, |
73 | .apll_sdiv = 0x0, | 73 | .apll_sdiv = 0x0, |
74 | 74 | ||
75 | .arm2_ratio = 0x0, | 75 | .arm2_ratio = 0x0, |
76 | .apll_ratio = 0x1, | 76 | .apll_ratio = 0x1, |
77 | .pclk_dbg_ratio = 0x1, | 77 | .pclk_dbg_ratio = 0x1, |
78 | .atb_ratio = 0x4, | 78 | .atb_ratio = 0x4, |
79 | .periph_ratio = 0x7, | 79 | .periph_ratio = 0x7, |
80 | .acp_ratio = 0x7, | 80 | .acp_ratio = 0x7, |
81 | .cpud_ratio = 0x2, | 81 | .cpud_ratio = 0x2, |
82 | .arm_ratio = 0x0, | 82 | .arm_ratio = 0x0, |
83 | }, { | 83 | }, { |
84 | .arm_freq_mhz = 1200, | 84 | .arm_freq_mhz = 1200, |
85 | 85 | ||
86 | .apll_mdiv = 0x96, | 86 | .apll_mdiv = 0x96, |
87 | .apll_pdiv = 0x3, | 87 | .apll_pdiv = 0x3, |
88 | .apll_sdiv = 0x0, | 88 | .apll_sdiv = 0x0, |
89 | 89 | ||
90 | .arm2_ratio = 0x0, | 90 | .arm2_ratio = 0x0, |
91 | .apll_ratio = 0x3, | 91 | .apll_ratio = 0x3, |
92 | .pclk_dbg_ratio = 0x1, | 92 | .pclk_dbg_ratio = 0x1, |
93 | .atb_ratio = 0x5, | 93 | .atb_ratio = 0x5, |
94 | .periph_ratio = 0x7, | 94 | .periph_ratio = 0x7, |
95 | .acp_ratio = 0x7, | 95 | .acp_ratio = 0x7, |
96 | .cpud_ratio = 0x3, | 96 | .cpud_ratio = 0x3, |
97 | .arm_ratio = 0x0, | 97 | .arm_ratio = 0x0, |
98 | }, { | 98 | }, { |
99 | .arm_freq_mhz = 1400, | 99 | .arm_freq_mhz = 1400, |
100 | 100 | ||
101 | .apll_mdiv = 0xaf, | 101 | .apll_mdiv = 0xaf, |
102 | .apll_pdiv = 0x3, | 102 | .apll_pdiv = 0x3, |
103 | .apll_sdiv = 0x0, | 103 | .apll_sdiv = 0x0, |
104 | 104 | ||
105 | .arm2_ratio = 0x0, | 105 | .arm2_ratio = 0x0, |
106 | .apll_ratio = 0x3, | 106 | .apll_ratio = 0x3, |
107 | .pclk_dbg_ratio = 0x1, | 107 | .pclk_dbg_ratio = 0x1, |
108 | .atb_ratio = 0x6, | 108 | .atb_ratio = 0x6, |
109 | .periph_ratio = 0x7, | 109 | .periph_ratio = 0x7, |
110 | .acp_ratio = 0x7, | 110 | .acp_ratio = 0x7, |
111 | .cpud_ratio = 0x3, | 111 | .cpud_ratio = 0x3, |
112 | .arm_ratio = 0x0, | 112 | .arm_ratio = 0x0, |
113 | }, { | 113 | }, { |
114 | .arm_freq_mhz = 1700, | 114 | .arm_freq_mhz = 1700, |
115 | 115 | ||
116 | .apll_mdiv = 0x1a9, | 116 | .apll_mdiv = 0x1a9, |
117 | .apll_pdiv = 0x6, | 117 | .apll_pdiv = 0x6, |
118 | .apll_sdiv = 0x0, | 118 | .apll_sdiv = 0x0, |
119 | 119 | ||
120 | .arm2_ratio = 0x0, | 120 | .arm2_ratio = 0x0, |
121 | .apll_ratio = 0x3, | 121 | .apll_ratio = 0x3, |
122 | .pclk_dbg_ratio = 0x1, | 122 | .pclk_dbg_ratio = 0x1, |
123 | .atb_ratio = 0x6, | 123 | .atb_ratio = 0x6, |
124 | .periph_ratio = 0x7, | 124 | .periph_ratio = 0x7, |
125 | .acp_ratio = 0x7, | 125 | .acp_ratio = 0x7, |
126 | .cpud_ratio = 0x3, | 126 | .cpud_ratio = 0x3, |
127 | .arm_ratio = 0x0, | 127 | .arm_ratio = 0x0, |
128 | } | 128 | } |
129 | }; | 129 | }; |
130 | struct mem_timings mem_timings[] = { | 130 | struct mem_timings mem_timings[] = { |
131 | { | 131 | { |
132 | .mem_manuf = MEM_MANUF_ELPIDA, | 132 | .mem_manuf = MEM_MANUF_ELPIDA, |
133 | .mem_type = DDR_MODE_DDR3, | 133 | .mem_type = DDR_MODE_DDR3, |
134 | .frequency_mhz = 800, | 134 | .frequency_mhz = 800, |
135 | .mpll_mdiv = 0xc8, | 135 | .mpll_mdiv = 0xc8, |
136 | .mpll_pdiv = 0x3, | 136 | .mpll_pdiv = 0x3, |
137 | .mpll_sdiv = 0x0, | 137 | .mpll_sdiv = 0x0, |
138 | .cpll_mdiv = 0xde, | 138 | .cpll_mdiv = 0xde, |
139 | .cpll_pdiv = 0x4, | 139 | .cpll_pdiv = 0x4, |
140 | .cpll_sdiv = 0x2, | 140 | .cpll_sdiv = 0x2, |
141 | .gpll_mdiv = 0x215, | 141 | .gpll_mdiv = 0x215, |
142 | .gpll_pdiv = 0xc, | 142 | .gpll_pdiv = 0xc, |
143 | .gpll_sdiv = 0x1, | 143 | .gpll_sdiv = 0x1, |
144 | .epll_mdiv = 0x60, | 144 | .epll_mdiv = 0x60, |
145 | .epll_pdiv = 0x3, | 145 | .epll_pdiv = 0x3, |
146 | .epll_sdiv = 0x3, | 146 | .epll_sdiv = 0x3, |
147 | .vpll_mdiv = 0x96, | 147 | .vpll_mdiv = 0x96, |
148 | .vpll_pdiv = 0x3, | 148 | .vpll_pdiv = 0x3, |
149 | .vpll_sdiv = 0x2, | 149 | .vpll_sdiv = 0x2, |
150 | 150 | ||
151 | .bpll_mdiv = 0x64, | 151 | .bpll_mdiv = 0x64, |
152 | .bpll_pdiv = 0x3, | 152 | .bpll_pdiv = 0x3, |
153 | .bpll_sdiv = 0x0, | 153 | .bpll_sdiv = 0x0, |
154 | .pclk_cdrex_ratio = 0x5, | 154 | .pclk_cdrex_ratio = 0x5, |
155 | .direct_cmd_msr = { | 155 | .direct_cmd_msr = { |
156 | 0x00020018, 0x00030000, 0x00010042, 0x00000d70 | 156 | 0x00020018, 0x00030000, 0x00010042, 0x00000d70 |
157 | }, | 157 | }, |
158 | .timing_ref = 0x000000bb, | 158 | .timing_ref = 0x000000bb, |
159 | .timing_row = 0x8c36650e, | 159 | .timing_row = 0x8c36650e, |
160 | .timing_data = 0x3630580b, | 160 | .timing_data = 0x3630580b, |
161 | .timing_power = 0x41000a44, | 161 | .timing_power = 0x41000a44, |
162 | .phy0_dqs = 0x08080808, | 162 | .phy0_dqs = 0x08080808, |
163 | .phy1_dqs = 0x08080808, | 163 | .phy1_dqs = 0x08080808, |
164 | .phy0_dq = 0x08080808, | 164 | .phy0_dq = 0x08080808, |
165 | .phy1_dq = 0x08080808, | 165 | .phy1_dq = 0x08080808, |
166 | .phy0_tFS = 0x4, | 166 | .phy0_tFS = 0x4, |
167 | .phy1_tFS = 0x4, | 167 | .phy1_tFS = 0x4, |
168 | .phy0_pulld_dqs = 0xf, | 168 | .phy0_pulld_dqs = 0xf, |
169 | .phy1_pulld_dqs = 0xf, | 169 | .phy1_pulld_dqs = 0xf, |
170 | 170 | ||
171 | .lpddr3_ctrl_phy_reset = 0x1, | 171 | .lpddr3_ctrl_phy_reset = 0x1, |
172 | .ctrl_start_point = 0x10, | 172 | .ctrl_start_point = 0x10, |
173 | .ctrl_inc = 0x10, | 173 | .ctrl_inc = 0x10, |
174 | .ctrl_start = 0x1, | 174 | .ctrl_start = 0x1, |
175 | .ctrl_dll_on = 0x1, | 175 | .ctrl_dll_on = 0x1, |
176 | .ctrl_ref = 0x8, | 176 | .ctrl_ref = 0x8, |
177 | 177 | ||
178 | .ctrl_force = 0x1a, | 178 | .ctrl_force = 0x1a, |
179 | .ctrl_rdlat = 0x0b, | 179 | .ctrl_rdlat = 0x0b, |
180 | .ctrl_bstlen = 0x08, | 180 | .ctrl_bstlen = 0x08, |
181 | 181 | ||
182 | .fp_resync = 0x8, | 182 | .fp_resync = 0x8, |
183 | .iv_size = 0x7, | 183 | .iv_size = 0x7, |
184 | .dfi_init_start = 1, | 184 | .dfi_init_start = 1, |
185 | .aref_en = 1, | 185 | .aref_en = 1, |
186 | 186 | ||
187 | .rd_fetch = 0x3, | 187 | .rd_fetch = 0x3, |
188 | 188 | ||
189 | .zq_mode_dds = 0x7, | 189 | .zq_mode_dds = 0x7, |
190 | .zq_mode_term = 0x1, | 190 | .zq_mode_term = 0x1, |
191 | .zq_mode_noterm = 0, | 191 | .zq_mode_noterm = 0, |
192 | 192 | ||
193 | /* | 193 | /* |
194 | * Dynamic Clock: Always Running | 194 | * Dynamic Clock: Always Running |
195 | * Memory Burst length: 8 | 195 | * Memory Burst length: 8 |
196 | * Number of chips: 1 | 196 | * Number of chips: 1 |
197 | * Memory Bus width: 32 bit | 197 | * Memory Bus width: 32 bit |
198 | * Memory Type: DDR3 | 198 | * Memory Type: DDR3 |
199 | * Additional Latancy for PLL: 0 Cycle | 199 | * Additional Latancy for PLL: 0 Cycle |
200 | */ | 200 | */ |
201 | .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | | 201 | .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | |
202 | DMC_MEMCONTROL_DPWRDN_DISABLE | | 202 | DMC_MEMCONTROL_DPWRDN_DISABLE | |
203 | DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | | 203 | DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | |
204 | DMC_MEMCONTROL_TP_DISABLE | | 204 | DMC_MEMCONTROL_TP_DISABLE | |
205 | DMC_MEMCONTROL_DSREF_ENABLE | | 205 | DMC_MEMCONTROL_DSREF_ENABLE | |
206 | DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | | 206 | DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | |
207 | DMC_MEMCONTROL_MEM_TYPE_DDR3 | | 207 | DMC_MEMCONTROL_MEM_TYPE_DDR3 | |
208 | DMC_MEMCONTROL_MEM_WIDTH_32BIT | | 208 | DMC_MEMCONTROL_MEM_WIDTH_32BIT | |
209 | DMC_MEMCONTROL_NUM_CHIP_1 | | 209 | DMC_MEMCONTROL_NUM_CHIP_1 | |
210 | DMC_MEMCONTROL_BL_8 | | 210 | DMC_MEMCONTROL_BL_8 | |
211 | DMC_MEMCONTROL_PZQ_DISABLE | | 211 | DMC_MEMCONTROL_PZQ_DISABLE | |
212 | DMC_MEMCONTROL_MRR_BYTE_7_0, | 212 | DMC_MEMCONTROL_MRR_BYTE_7_0, |
213 | .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | | 213 | .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | |
214 | DMC_MEMCONFIGx_CHIP_COL_10 | | 214 | DMC_MEMCONFIGx_CHIP_COL_10 | |
215 | DMC_MEMCONFIGx_CHIP_ROW_15 | | 215 | DMC_MEMCONFIGx_CHIP_ROW_15 | |
216 | DMC_MEMCONFIGx_CHIP_BANK_8, | 216 | DMC_MEMCONFIGx_CHIP_BANK_8, |
217 | .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), | 217 | .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), |
218 | .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), | 218 | .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), |
219 | .prechconfig_tp_cnt = 0xff, | 219 | .prechconfig_tp_cnt = 0xff, |
220 | .dpwrdn_cyc = 0xff, | 220 | .dpwrdn_cyc = 0xff, |
221 | .dsref_cyc = 0xffff, | 221 | .dsref_cyc = 0xffff, |
222 | .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | | 222 | .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | |
223 | DMC_CONCONTROL_TIMEOUT_LEVEL0 | | 223 | DMC_CONCONTROL_TIMEOUT_LEVEL0 | |
224 | DMC_CONCONTROL_RD_FETCH_DISABLE | | 224 | DMC_CONCONTROL_RD_FETCH_DISABLE | |
225 | DMC_CONCONTROL_EMPTY_DISABLE | | 225 | DMC_CONCONTROL_EMPTY_DISABLE | |
226 | DMC_CONCONTROL_AREF_EN_DISABLE | | 226 | DMC_CONCONTROL_AREF_EN_DISABLE | |
227 | DMC_CONCONTROL_IO_PD_CON_DISABLE, | 227 | DMC_CONCONTROL_IO_PD_CON_DISABLE, |
228 | .dmc_channels = 2, | 228 | .dmc_channels = 2, |
229 | .chips_per_channel = 2, | 229 | .chips_per_channel = 2, |
230 | .chips_to_configure = 1, | 230 | .chips_to_configure = 1, |
231 | .send_zq_init = 1, | 231 | .send_zq_init = 1, |
232 | .impedance = IMP_OUTPUT_DRV_30_OHM, | 232 | .impedance = IMP_OUTPUT_DRV_30_OHM, |
233 | .gate_leveling_enable = 0, | 233 | .gate_leveling_enable = 0, |
234 | }, { | 234 | }, { |
235 | .mem_manuf = MEM_MANUF_SAMSUNG, | 235 | .mem_manuf = MEM_MANUF_SAMSUNG, |
236 | .mem_type = DDR_MODE_DDR3, | 236 | .mem_type = DDR_MODE_DDR3, |
237 | .frequency_mhz = 800, | 237 | .frequency_mhz = 800, |
238 | .mpll_mdiv = 0xc8, | 238 | .mpll_mdiv = 0xc8, |
239 | .mpll_pdiv = 0x3, | 239 | .mpll_pdiv = 0x3, |
240 | .mpll_sdiv = 0x0, | 240 | .mpll_sdiv = 0x0, |
241 | .cpll_mdiv = 0xde, | 241 | .cpll_mdiv = 0xde, |
242 | .cpll_pdiv = 0x4, | 242 | .cpll_pdiv = 0x4, |
243 | .cpll_sdiv = 0x2, | 243 | .cpll_sdiv = 0x2, |
244 | .gpll_mdiv = 0x215, | 244 | .gpll_mdiv = 0x215, |
245 | .gpll_pdiv = 0xc, | 245 | .gpll_pdiv = 0xc, |
246 | .gpll_sdiv = 0x1, | 246 | .gpll_sdiv = 0x1, |
247 | .epll_mdiv = 0x60, | 247 | .epll_mdiv = 0x60, |
248 | .epll_pdiv = 0x3, | 248 | .epll_pdiv = 0x3, |
249 | .epll_sdiv = 0x3, | 249 | .epll_sdiv = 0x3, |
250 | .vpll_mdiv = 0x96, | 250 | .vpll_mdiv = 0x96, |
251 | .vpll_pdiv = 0x3, | 251 | .vpll_pdiv = 0x3, |
252 | .vpll_sdiv = 0x2, | 252 | .vpll_sdiv = 0x2, |
253 | 253 | ||
254 | .bpll_mdiv = 0x64, | 254 | .bpll_mdiv = 0x64, |
255 | .bpll_pdiv = 0x3, | 255 | .bpll_pdiv = 0x3, |
256 | .bpll_sdiv = 0x0, | 256 | .bpll_sdiv = 0x0, |
257 | .pclk_cdrex_ratio = 0x5, | 257 | .pclk_cdrex_ratio = 0x5, |
258 | .direct_cmd_msr = { | 258 | .direct_cmd_msr = { |
259 | 0x00020018, 0x00030000, 0x00010000, 0x00000d70 | 259 | 0x00020018, 0x00030000, 0x00010000, 0x00000d70 |
260 | }, | 260 | }, |
261 | .timing_ref = 0x000000bb, | 261 | .timing_ref = 0x000000bb, |
262 | .timing_row = 0x8c36650e, | 262 | .timing_row = 0x8c36650e, |
263 | .timing_data = 0x3630580b, | 263 | .timing_data = 0x3630580b, |
264 | .timing_power = 0x41000a44, | 264 | .timing_power = 0x41000a44, |
265 | .phy0_dqs = 0x08080808, | 265 | .phy0_dqs = 0x08080808, |
266 | .phy1_dqs = 0x08080808, | 266 | .phy1_dqs = 0x08080808, |
267 | .phy0_dq = 0x08080808, | 267 | .phy0_dq = 0x08080808, |
268 | .phy1_dq = 0x08080808, | 268 | .phy1_dq = 0x08080808, |
269 | .phy0_tFS = 0x8, | 269 | .phy0_tFS = 0x8, |
270 | .phy1_tFS = 0x8, | 270 | .phy1_tFS = 0x8, |
271 | .phy0_pulld_dqs = 0xf, | 271 | .phy0_pulld_dqs = 0xf, |
272 | .phy1_pulld_dqs = 0xf, | 272 | .phy1_pulld_dqs = 0xf, |
273 | 273 | ||
274 | .lpddr3_ctrl_phy_reset = 0x1, | 274 | .lpddr3_ctrl_phy_reset = 0x1, |
275 | .ctrl_start_point = 0x10, | 275 | .ctrl_start_point = 0x10, |
276 | .ctrl_inc = 0x10, | 276 | .ctrl_inc = 0x10, |
277 | .ctrl_start = 0x1, | 277 | .ctrl_start = 0x1, |
278 | .ctrl_dll_on = 0x1, | 278 | .ctrl_dll_on = 0x1, |
279 | .ctrl_ref = 0x8, | 279 | .ctrl_ref = 0x8, |
280 | 280 | ||
281 | .ctrl_force = 0x1a, | 281 | .ctrl_force = 0x1a, |
282 | .ctrl_rdlat = 0x0b, | 282 | .ctrl_rdlat = 0x0b, |
283 | .ctrl_bstlen = 0x08, | 283 | .ctrl_bstlen = 0x08, |
284 | 284 | ||
285 | .fp_resync = 0x8, | 285 | .fp_resync = 0x8, |
286 | .iv_size = 0x7, | 286 | .iv_size = 0x7, |
287 | .dfi_init_start = 1, | 287 | .dfi_init_start = 1, |
288 | .aref_en = 1, | 288 | .aref_en = 1, |
289 | 289 | ||
290 | .rd_fetch = 0x3, | 290 | .rd_fetch = 0x3, |
291 | 291 | ||
292 | .zq_mode_dds = 0x5, | 292 | .zq_mode_dds = 0x5, |
293 | .zq_mode_term = 0x1, | 293 | .zq_mode_term = 0x1, |
294 | .zq_mode_noterm = 1, | 294 | .zq_mode_noterm = 1, |
295 | 295 | ||
296 | /* | 296 | /* |
297 | * Dynamic Clock: Always Running | 297 | * Dynamic Clock: Always Running |
298 | * Memory Burst length: 8 | 298 | * Memory Burst length: 8 |
299 | * Number of chips: 1 | 299 | * Number of chips: 1 |
300 | * Memory Bus width: 32 bit | 300 | * Memory Bus width: 32 bit |
301 | * Memory Type: DDR3 | 301 | * Memory Type: DDR3 |
302 | * Additional Latancy for PLL: 0 Cycle | 302 | * Additional Latancy for PLL: 0 Cycle |
303 | */ | 303 | */ |
304 | .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | | 304 | .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | |
305 | DMC_MEMCONTROL_DPWRDN_DISABLE | | 305 | DMC_MEMCONTROL_DPWRDN_DISABLE | |
306 | DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | | 306 | DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | |
307 | DMC_MEMCONTROL_TP_DISABLE | | 307 | DMC_MEMCONTROL_TP_DISABLE | |
308 | DMC_MEMCONTROL_DSREF_ENABLE | | 308 | DMC_MEMCONTROL_DSREF_ENABLE | |
309 | DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | | 309 | DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | |
310 | DMC_MEMCONTROL_MEM_TYPE_DDR3 | | 310 | DMC_MEMCONTROL_MEM_TYPE_DDR3 | |
311 | DMC_MEMCONTROL_MEM_WIDTH_32BIT | | 311 | DMC_MEMCONTROL_MEM_WIDTH_32BIT | |
312 | DMC_MEMCONTROL_NUM_CHIP_1 | | 312 | DMC_MEMCONTROL_NUM_CHIP_1 | |
313 | DMC_MEMCONTROL_BL_8 | | 313 | DMC_MEMCONTROL_BL_8 | |
314 | DMC_MEMCONTROL_PZQ_DISABLE | | 314 | DMC_MEMCONTROL_PZQ_DISABLE | |
315 | DMC_MEMCONTROL_MRR_BYTE_7_0, | 315 | DMC_MEMCONTROL_MRR_BYTE_7_0, |
316 | .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | | 316 | .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | |
317 | DMC_MEMCONFIGx_CHIP_COL_10 | | 317 | DMC_MEMCONFIGx_CHIP_COL_10 | |
318 | DMC_MEMCONFIGx_CHIP_ROW_15 | | 318 | DMC_MEMCONFIGx_CHIP_ROW_15 | |
319 | DMC_MEMCONFIGx_CHIP_BANK_8, | 319 | DMC_MEMCONFIGx_CHIP_BANK_8, |
320 | .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), | 320 | .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), |
321 | .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), | 321 | .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), |
322 | .prechconfig_tp_cnt = 0xff, | 322 | .prechconfig_tp_cnt = 0xff, |
323 | .dpwrdn_cyc = 0xff, | 323 | .dpwrdn_cyc = 0xff, |
324 | .dsref_cyc = 0xffff, | 324 | .dsref_cyc = 0xffff, |
325 | .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | | 325 | .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | |
326 | DMC_CONCONTROL_TIMEOUT_LEVEL0 | | 326 | DMC_CONCONTROL_TIMEOUT_LEVEL0 | |
327 | DMC_CONCONTROL_RD_FETCH_DISABLE | | 327 | DMC_CONCONTROL_RD_FETCH_DISABLE | |
328 | DMC_CONCONTROL_EMPTY_DISABLE | | 328 | DMC_CONCONTROL_EMPTY_DISABLE | |
329 | DMC_CONCONTROL_AREF_EN_DISABLE | | 329 | DMC_CONCONTROL_AREF_EN_DISABLE | |
330 | DMC_CONCONTROL_IO_PD_CON_DISABLE, | 330 | DMC_CONCONTROL_IO_PD_CON_DISABLE, |
331 | .dmc_channels = 2, | 331 | .dmc_channels = 2, |
332 | .chips_per_channel = 2, | 332 | .chips_per_channel = 2, |
333 | .chips_to_configure = 1, | 333 | .chips_to_configure = 1, |
334 | .send_zq_init = 1, | 334 | .send_zq_init = 1, |
335 | .impedance = IMP_OUTPUT_DRV_40_OHM, | 335 | .impedance = IMP_OUTPUT_DRV_40_OHM, |
336 | .gate_leveling_enable = 1, | 336 | .gate_leveling_enable = 1, |
337 | } | 337 | } |
338 | }; | 338 | }; |
339 | 339 | ||
340 | /** | 340 | /** |
341 | * Get the required memory type and speed (SPL version). | 341 | * Get the required memory type and speed (SPL version). |
342 | * | 342 | * |
343 | * In SPL we have no device tree, so we use the machine parameters | 343 | * In SPL we have no device tree, so we use the machine parameters |
344 | * | 344 | * |
345 | * @param mem_type Returns memory type | 345 | * @param mem_type Returns memory type |
346 | * @param frequency_mhz Returns memory speed in MHz | 346 | * @param frequency_mhz Returns memory speed in MHz |
347 | * @param arm_freq Returns ARM clock speed in MHz | 347 | * @param arm_freq Returns ARM clock speed in MHz |
348 | * @param mem_manuf Return Memory Manufacturer name | 348 | * @param mem_manuf Return Memory Manufacturer name |
349 | * @return 0 if all ok | 349 | * @return 0 if all ok |
350 | */ | 350 | */ |
351 | static int clock_get_mem_selection(enum ddr_mode *mem_type, | 351 | static int clock_get_mem_selection(enum ddr_mode *mem_type, |
352 | unsigned *frequency_mhz, unsigned *arm_freq, | 352 | unsigned *frequency_mhz, unsigned *arm_freq, |
353 | enum mem_manuf *mem_manuf) | 353 | enum mem_manuf *mem_manuf) |
354 | { | 354 | { |
355 | struct spl_machine_param *params; | 355 | struct spl_machine_param *params; |
356 | 356 | ||
357 | params = spl_get_machine_params(); | 357 | params = spl_get_machine_params(); |
358 | *mem_type = params->mem_type; | 358 | *mem_type = params->mem_type; |
359 | *frequency_mhz = params->frequency_mhz; | 359 | *frequency_mhz = params->frequency_mhz; |
360 | *arm_freq = params->arm_freq_mhz; | 360 | *arm_freq = params->arm_freq_mhz; |
361 | *mem_manuf = params->mem_manuf; | 361 | *mem_manuf = params->mem_manuf; |
362 | 362 | ||
363 | return 0; | 363 | return 0; |
364 | } | 364 | } |
365 | 365 | ||
366 | /* Get the ratios for setting ARM clock */ | 366 | /* Get the ratios for setting ARM clock */ |
367 | struct arm_clk_ratios *get_arm_ratios(void) | 367 | struct arm_clk_ratios *get_arm_ratios(void) |
368 | { | 368 | { |
369 | struct arm_clk_ratios *arm_ratio; | 369 | struct arm_clk_ratios *arm_ratio; |
370 | enum ddr_mode mem_type; | 370 | enum ddr_mode mem_type; |
371 | enum mem_manuf mem_manuf; | 371 | enum mem_manuf mem_manuf; |
372 | unsigned frequency_mhz, arm_freq; | 372 | unsigned frequency_mhz, arm_freq; |
373 | int i; | 373 | int i; |
374 | 374 | ||
375 | if (clock_get_mem_selection(&mem_type, &frequency_mhz, | 375 | if (clock_get_mem_selection(&mem_type, &frequency_mhz, |
376 | &arm_freq, &mem_manuf)) | 376 | &arm_freq, &mem_manuf)) |
377 | ; | 377 | ; |
378 | for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios); | 378 | for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios); |
379 | i++, arm_ratio++) { | 379 | i++, arm_ratio++) { |
380 | if (arm_ratio->arm_freq_mhz == arm_freq) | 380 | if (arm_ratio->arm_freq_mhz == arm_freq) |
381 | return arm_ratio; | 381 | return arm_ratio; |
382 | } | 382 | } |
383 | 383 | ||
384 | /* will hang if failed to find clock ratio */ | 384 | /* will hang if failed to find clock ratio */ |
385 | while (1) | 385 | while (1) |
386 | ; | 386 | ; |
387 | 387 | ||
388 | return NULL; | 388 | return NULL; |
389 | } | 389 | } |
390 | 390 | ||
391 | struct mem_timings *clock_get_mem_timings(void) | 391 | struct mem_timings *clock_get_mem_timings(void) |
392 | { | 392 | { |
393 | struct mem_timings *mem; | 393 | struct mem_timings *mem; |
394 | enum ddr_mode mem_type; | 394 | enum ddr_mode mem_type; |
395 | enum mem_manuf mem_manuf; | 395 | enum mem_manuf mem_manuf; |
396 | unsigned frequency_mhz, arm_freq; | 396 | unsigned frequency_mhz, arm_freq; |
397 | int i; | 397 | int i; |
398 | 398 | ||
399 | if (!clock_get_mem_selection(&mem_type, &frequency_mhz, | 399 | if (!clock_get_mem_selection(&mem_type, &frequency_mhz, |
400 | &arm_freq, &mem_manuf)) { | 400 | &arm_freq, &mem_manuf)) { |
401 | for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings); | 401 | for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings); |
402 | i++, mem++) { | 402 | i++, mem++) { |
403 | if (mem->mem_type == mem_type && | 403 | if (mem->mem_type == mem_type && |
404 | mem->frequency_mhz == frequency_mhz && | 404 | mem->frequency_mhz == frequency_mhz && |
405 | mem->mem_manuf == mem_manuf) | 405 | mem->mem_manuf == mem_manuf) |
406 | return mem; | 406 | return mem; |
407 | } | 407 | } |
408 | } | 408 | } |
409 | 409 | ||
410 | /* will hang if failed to find memory timings */ | 410 | /* will hang if failed to find memory timings */ |
411 | while (1) | 411 | while (1) |
412 | ; | 412 | ; |
413 | 413 | ||
414 | return NULL; | 414 | return NULL; |
415 | } | 415 | } |
416 | 416 | ||
417 | void system_clock_init() | 417 | void system_clock_init() |
418 | { | 418 | { |
419 | struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; | 419 | struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; |
420 | struct mem_timings *mem; | 420 | struct mem_timings *mem; |
421 | struct arm_clk_ratios *arm_clk_ratio; | 421 | struct arm_clk_ratios *arm_clk_ratio; |
422 | u32 val, tmp; | 422 | u32 val, tmp; |
423 | 423 | ||
424 | mem = clock_get_mem_timings(); | 424 | mem = clock_get_mem_timings(); |
425 | arm_clk_ratio = get_arm_ratios(); | 425 | arm_clk_ratio = get_arm_ratios(); |
426 | 426 | ||
427 | clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK); | 427 | clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK); |
428 | do { | 428 | do { |
429 | val = readl(&clk->mux_stat_cpu); | 429 | val = readl(&clk->mux_stat_cpu); |
430 | } while ((val | MUX_APLL_SEL_MASK) != val); | 430 | } while ((val | MUX_APLL_SEL_MASK) != val); |
431 | 431 | ||
432 | clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK); | 432 | clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK); |
433 | do { | 433 | do { |
434 | val = readl(&clk->mux_stat_core1); | 434 | val = readl(&clk->mux_stat_core1); |
435 | } while ((val | MUX_MPLL_SEL_MASK) != val); | 435 | } while ((val | MUX_MPLL_SEL_MASK) != val); |
436 | 436 | ||
437 | clrbits_le32(&clk->src_core1, MUX_CPLL_SEL_MASK); | 437 | clrbits_le32(&clk->src_core1, MUX_CPLL_SEL_MASK); |
438 | clrbits_le32(&clk->src_core1, MUX_EPLL_SEL_MASK); | 438 | clrbits_le32(&clk->src_core1, MUX_EPLL_SEL_MASK); |
439 | clrbits_le32(&clk->src_core1, MUX_VPLL_SEL_MASK); | 439 | clrbits_le32(&clk->src_core1, MUX_VPLL_SEL_MASK); |
440 | clrbits_le32(&clk->src_core1, MUX_GPLL_SEL_MASK); | 440 | clrbits_le32(&clk->src_core1, MUX_GPLL_SEL_MASK); |
441 | tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK | 441 | tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK |
442 | | MUX_GPLL_SEL_MASK; | 442 | | MUX_GPLL_SEL_MASK; |
443 | do { | 443 | do { |
444 | val = readl(&clk->mux_stat_top2); | 444 | val = readl(&clk->mux_stat_top2); |
445 | } while ((val | tmp) != val); | 445 | } while ((val | tmp) != val); |
446 | 446 | ||
447 | clrbits_le32(&clk->src_cdrex, MUX_BPLL_SEL_MASK); | 447 | clrbits_le32(&clk->src_cdrex, MUX_BPLL_SEL_MASK); |
448 | do { | 448 | do { |
449 | val = readl(&clk->mux_stat_cdrex); | 449 | val = readl(&clk->mux_stat_cdrex); |
450 | } while ((val | MUX_BPLL_SEL_MASK) != val); | 450 | } while ((val | MUX_BPLL_SEL_MASK) != val); |
451 | 451 | ||
452 | /* PLL locktime */ | 452 | /* PLL locktime */ |
453 | writel(APLL_LOCK_VAL, &clk->apll_lock); | 453 | writel(APLL_LOCK_VAL, &clk->apll_lock); |
454 | 454 | ||
455 | writel(MPLL_LOCK_VAL, &clk->mpll_lock); | 455 | writel(MPLL_LOCK_VAL, &clk->mpll_lock); |
456 | 456 | ||
457 | writel(BPLL_LOCK_VAL, &clk->bpll_lock); | 457 | writel(BPLL_LOCK_VAL, &clk->bpll_lock); |
458 | 458 | ||
459 | writel(CPLL_LOCK_VAL, &clk->cpll_lock); | 459 | writel(CPLL_LOCK_VAL, &clk->cpll_lock); |
460 | 460 | ||
461 | writel(GPLL_LOCK_VAL, &clk->gpll_lock); | 461 | writel(GPLL_LOCK_VAL, &clk->gpll_lock); |
462 | 462 | ||
463 | writel(EPLL_LOCK_VAL, &clk->epll_lock); | 463 | writel(EPLL_LOCK_VAL, &clk->epll_lock); |
464 | 464 | ||
465 | writel(VPLL_LOCK_VAL, &clk->vpll_lock); | 465 | writel(VPLL_LOCK_VAL, &clk->vpll_lock); |
466 | 466 | ||
467 | writel(CLK_REG_DISABLE, &clk->pll_div2_sel); | 467 | writel(CLK_REG_DISABLE, &clk->pll_div2_sel); |
468 | 468 | ||
469 | writel(MUX_HPM_SEL_MASK, &clk->src_cpu); | 469 | writel(MUX_HPM_SEL_MASK, &clk->src_cpu); |
470 | do { | 470 | do { |
471 | val = readl(&clk->mux_stat_cpu); | 471 | val = readl(&clk->mux_stat_cpu); |
472 | } while ((val | HPM_SEL_SCLK_MPLL) != val); | 472 | } while ((val | HPM_SEL_SCLK_MPLL) != val); |
473 | 473 | ||
474 | val = arm_clk_ratio->arm2_ratio << 28 | 474 | val = arm_clk_ratio->arm2_ratio << 28 |
475 | | arm_clk_ratio->apll_ratio << 24 | 475 | | arm_clk_ratio->apll_ratio << 24 |
476 | | arm_clk_ratio->pclk_dbg_ratio << 20 | 476 | | arm_clk_ratio->pclk_dbg_ratio << 20 |
477 | | arm_clk_ratio->atb_ratio << 16 | 477 | | arm_clk_ratio->atb_ratio << 16 |
478 | | arm_clk_ratio->periph_ratio << 12 | 478 | | arm_clk_ratio->periph_ratio << 12 |
479 | | arm_clk_ratio->acp_ratio << 8 | 479 | | arm_clk_ratio->acp_ratio << 8 |
480 | | arm_clk_ratio->cpud_ratio << 4 | 480 | | arm_clk_ratio->cpud_ratio << 4 |
481 | | arm_clk_ratio->arm_ratio; | 481 | | arm_clk_ratio->arm_ratio; |
482 | writel(val, &clk->div_cpu0); | 482 | writel(val, &clk->div_cpu0); |
483 | do { | 483 | do { |
484 | val = readl(&clk->div_stat_cpu0); | 484 | val = readl(&clk->div_stat_cpu0); |
485 | } while (0 != val); | 485 | } while (0 != val); |
486 | 486 | ||
487 | writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1); | 487 | writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1); |
488 | do { | 488 | do { |
489 | val = readl(&clk->div_stat_cpu1); | 489 | val = readl(&clk->div_stat_cpu1); |
490 | } while (0 != val); | 490 | } while (0 != val); |
491 | 491 | ||
492 | /* Set APLL */ | 492 | /* Set APLL */ |
493 | writel(APLL_CON1_VAL, &clk->apll_con1); | 493 | writel(APLL_CON1_VAL, &clk->apll_con1); |
494 | val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv, | 494 | val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv, |
495 | arm_clk_ratio->apll_sdiv); | 495 | arm_clk_ratio->apll_sdiv); |
496 | writel(val, &clk->apll_con0); | 496 | writel(val, &clk->apll_con0); |
497 | while (readl(&clk->apll_con0) & APLL_CON0_LOCKED) | 497 | while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0) |
498 | ; | 498 | ; |
499 | 499 | ||
500 | /* Set MPLL */ | 500 | /* Set MPLL */ |
501 | writel(MPLL_CON1_VAL, &clk->mpll_con1); | 501 | writel(MPLL_CON1_VAL, &clk->mpll_con1); |
502 | val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv); | 502 | val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv); |
503 | writel(val, &clk->mpll_con0); | 503 | writel(val, &clk->mpll_con0); |
504 | while (readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) | 504 | while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0) |
505 | ; | 505 | ; |
506 | 506 | ||
507 | /* Set BPLL */ | 507 | /* Set BPLL */ |
508 | writel(BPLL_CON1_VAL, &clk->bpll_con1); | 508 | writel(BPLL_CON1_VAL, &clk->bpll_con1); |
509 | val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv); | 509 | val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv); |
510 | writel(val, &clk->bpll_con0); | 510 | writel(val, &clk->bpll_con0); |
511 | while (readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) | 511 | while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0) |
512 | ; | 512 | ; |
513 | 513 | ||
514 | /* Set CPLL */ | 514 | /* Set CPLL */ |
515 | writel(CPLL_CON1_VAL, &clk->cpll_con1); | 515 | writel(CPLL_CON1_VAL, &clk->cpll_con1); |
516 | val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv); | 516 | val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv); |
517 | writel(val, &clk->cpll_con0); | 517 | writel(val, &clk->cpll_con0); |
518 | while (readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) | 518 | while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0) |
519 | ; | 519 | ; |
520 | 520 | ||
521 | /* Set GPLL */ | 521 | /* Set GPLL */ |
522 | writel(GPLL_CON1_VAL, &clk->gpll_con1); | 522 | writel(GPLL_CON1_VAL, &clk->gpll_con1); |
523 | val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv); | 523 | val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv); |
524 | writel(val, &clk->gpll_con0); | 524 | writel(val, &clk->gpll_con0); |
525 | while (readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) | 525 | while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0) |
526 | ; | 526 | ; |
527 | 527 | ||
528 | /* Set EPLL */ | 528 | /* Set EPLL */ |
529 | writel(EPLL_CON2_VAL, &clk->epll_con2); | 529 | writel(EPLL_CON2_VAL, &clk->epll_con2); |
530 | writel(EPLL_CON1_VAL, &clk->epll_con1); | 530 | writel(EPLL_CON1_VAL, &clk->epll_con1); |
531 | val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv); | 531 | val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv); |
532 | writel(val, &clk->epll_con0); | 532 | writel(val, &clk->epll_con0); |
533 | while (readl(&clk->epll_con0) & EPLL_CON0_LOCKED) | 533 | while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0) |
534 | ; | 534 | ; |
535 | 535 | ||
536 | /* Set VPLL */ | 536 | /* Set VPLL */ |
537 | writel(VPLL_CON2_VAL, &clk->vpll_con2); | 537 | writel(VPLL_CON2_VAL, &clk->vpll_con2); |
538 | writel(VPLL_CON1_VAL, &clk->vpll_con1); | 538 | writel(VPLL_CON1_VAL, &clk->vpll_con1); |
539 | val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv); | 539 | val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv); |
540 | writel(val, &clk->vpll_con0); | 540 | writel(val, &clk->vpll_con0); |
541 | while (readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) | 541 | while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0) |
542 | ; | 542 | ; |
543 | 543 | ||
544 | writel(CLK_SRC_CORE0_VAL, &clk->src_core0); | 544 | writel(CLK_SRC_CORE0_VAL, &clk->src_core0); |
545 | writel(CLK_DIV_CORE0_VAL, &clk->div_core0); | 545 | writel(CLK_DIV_CORE0_VAL, &clk->div_core0); |
546 | while (readl(&clk->div_stat_core0) != 0) | 546 | while (readl(&clk->div_stat_core0) != 0) |
547 | ; | 547 | ; |
548 | 548 | ||
549 | writel(CLK_DIV_CORE1_VAL, &clk->div_core1); | 549 | writel(CLK_DIV_CORE1_VAL, &clk->div_core1); |
550 | while (readl(&clk->div_stat_core1) != 0) | 550 | while (readl(&clk->div_stat_core1) != 0) |
551 | ; | 551 | ; |
552 | 552 | ||
553 | writel(CLK_DIV_SYSRGT_VAL, &clk->div_sysrgt); | 553 | writel(CLK_DIV_SYSRGT_VAL, &clk->div_sysrgt); |
554 | while (readl(&clk->div_stat_sysrgt) != 0) | 554 | while (readl(&clk->div_stat_sysrgt) != 0) |
555 | ; | 555 | ; |
556 | 556 | ||
557 | writel(CLK_DIV_ACP_VAL, &clk->div_acp); | 557 | writel(CLK_DIV_ACP_VAL, &clk->div_acp); |
558 | while (readl(&clk->div_stat_acp) != 0) | 558 | while (readl(&clk->div_stat_acp) != 0) |
559 | ; | 559 | ; |
560 | 560 | ||
561 | writel(CLK_DIV_SYSLFT_VAL, &clk->div_syslft); | 561 | writel(CLK_DIV_SYSLFT_VAL, &clk->div_syslft); |
562 | while (readl(&clk->div_stat_syslft) != 0) | 562 | while (readl(&clk->div_stat_syslft) != 0) |
563 | ; | 563 | ; |
564 | 564 | ||
565 | writel(CLK_SRC_TOP0_VAL, &clk->src_top0); | 565 | writel(CLK_SRC_TOP0_VAL, &clk->src_top0); |
566 | writel(CLK_SRC_TOP1_VAL, &clk->src_top1); | 566 | writel(CLK_SRC_TOP1_VAL, &clk->src_top1); |
567 | writel(TOP2_VAL, &clk->src_top2); | 567 | writel(TOP2_VAL, &clk->src_top2); |
568 | writel(CLK_SRC_TOP3_VAL, &clk->src_top3); | 568 | writel(CLK_SRC_TOP3_VAL, &clk->src_top3); |
569 | 569 | ||
570 | writel(CLK_DIV_TOP0_VAL, &clk->div_top0); | 570 | writel(CLK_DIV_TOP0_VAL, &clk->div_top0); |
571 | while (readl(&clk->div_stat_top0)) | 571 | while (readl(&clk->div_stat_top0)) |
572 | ; | 572 | ; |
573 | 573 | ||
574 | writel(CLK_DIV_TOP1_VAL, &clk->div_top1); | 574 | writel(CLK_DIV_TOP1_VAL, &clk->div_top1); |
575 | while (readl(&clk->div_stat_top1)) | 575 | while (readl(&clk->div_stat_top1)) |
576 | ; | 576 | ; |
577 | 577 | ||
578 | writel(CLK_SRC_LEX_VAL, &clk->src_lex); | 578 | writel(CLK_SRC_LEX_VAL, &clk->src_lex); |
579 | while (1) { | 579 | while (1) { |
580 | val = readl(&clk->mux_stat_lex); | 580 | val = readl(&clk->mux_stat_lex); |
581 | if (val == (val | 1)) | 581 | if (val == (val | 1)) |
582 | break; | 582 | break; |
583 | } | 583 | } |
584 | 584 | ||
585 | writel(CLK_DIV_LEX_VAL, &clk->div_lex); | 585 | writel(CLK_DIV_LEX_VAL, &clk->div_lex); |
586 | while (readl(&clk->div_stat_lex)) | 586 | while (readl(&clk->div_stat_lex)) |
587 | ; | 587 | ; |
588 | 588 | ||
589 | writel(CLK_DIV_R0X_VAL, &clk->div_r0x); | 589 | writel(CLK_DIV_R0X_VAL, &clk->div_r0x); |
590 | while (readl(&clk->div_stat_r0x)) | 590 | while (readl(&clk->div_stat_r0x)) |
591 | ; | 591 | ; |
592 | 592 | ||
593 | writel(CLK_DIV_R0X_VAL, &clk->div_r0x); | 593 | writel(CLK_DIV_R0X_VAL, &clk->div_r0x); |
594 | while (readl(&clk->div_stat_r0x)) | 594 | while (readl(&clk->div_stat_r0x)) |
595 | ; | 595 | ; |
596 | 596 | ||
597 | writel(CLK_DIV_R1X_VAL, &clk->div_r1x); | 597 | writel(CLK_DIV_R1X_VAL, &clk->div_r1x); |
598 | while (readl(&clk->div_stat_r1x)) | 598 | while (readl(&clk->div_stat_r1x)) |
599 | ; | 599 | ; |
600 | 600 | ||
601 | writel(CLK_REG_DISABLE, &clk->src_cdrex); | 601 | writel(CLK_REG_DISABLE, &clk->src_cdrex); |
602 | 602 | ||
603 | writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex); | 603 | writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex); |
604 | while (readl(&clk->div_stat_cdrex)) | 604 | while (readl(&clk->div_stat_cdrex)) |
605 | ; | 605 | ; |
606 | 606 | ||
607 | val = readl(&clk->src_cpu); | 607 | val = readl(&clk->src_cpu); |
608 | val |= CLK_SRC_CPU_VAL; | 608 | val |= CLK_SRC_CPU_VAL; |
609 | writel(val, &clk->src_cpu); | 609 | writel(val, &clk->src_cpu); |
610 | 610 | ||
611 | val = readl(&clk->src_top2); | 611 | val = readl(&clk->src_top2); |
612 | val |= CLK_SRC_TOP2_VAL; | 612 | val |= CLK_SRC_TOP2_VAL; |
613 | writel(val, &clk->src_top2); | 613 | writel(val, &clk->src_top2); |
614 | 614 | ||
615 | val = readl(&clk->src_core1); | 615 | val = readl(&clk->src_core1); |
616 | val |= CLK_SRC_CORE1_VAL; | 616 | val |= CLK_SRC_CORE1_VAL; |
617 | writel(val, &clk->src_core1); | 617 | writel(val, &clk->src_core1); |
618 | 618 | ||
619 | writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys); | 619 | writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys); |
620 | writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0); | 620 | writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0); |
621 | while (readl(&clk->div_stat_fsys0)) | 621 | while (readl(&clk->div_stat_fsys0)) |
622 | ; | 622 | ; |
623 | 623 | ||
624 | writel(CLK_REG_DISABLE, &clk->clkout_cmu_cpu); | 624 | writel(CLK_REG_DISABLE, &clk->clkout_cmu_cpu); |
625 | writel(CLK_REG_DISABLE, &clk->clkout_cmu_core); | 625 | writel(CLK_REG_DISABLE, &clk->clkout_cmu_core); |
626 | writel(CLK_REG_DISABLE, &clk->clkout_cmu_acp); | 626 | writel(CLK_REG_DISABLE, &clk->clkout_cmu_acp); |
627 | writel(CLK_REG_DISABLE, &clk->clkout_cmu_top); | 627 | writel(CLK_REG_DISABLE, &clk->clkout_cmu_top); |
628 | writel(CLK_REG_DISABLE, &clk->clkout_cmu_lex); | 628 | writel(CLK_REG_DISABLE, &clk->clkout_cmu_lex); |
629 | writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x); | 629 | writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x); |
630 | writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x); | 630 | writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x); |
631 | writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex); | 631 | writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex); |
632 | 632 | ||
633 | writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0); | 633 | writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0); |
634 | writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0); | 634 | writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0); |
635 | 635 | ||
636 | writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1); | 636 | writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1); |
637 | writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1); | 637 | writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1); |
638 | writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2); | 638 | writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2); |
639 | writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3); | 639 | writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3); |
640 | 640 | ||
641 | writel(SCLK_SRC_ISP_VAL, &clk->sclk_src_isp); | 641 | writel(SCLK_SRC_ISP_VAL, &clk->sclk_src_isp); |
642 | writel(SCLK_DIV_ISP_VAL, &clk->sclk_div_isp); | 642 | writel(SCLK_DIV_ISP_VAL, &clk->sclk_div_isp); |
643 | writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); | 643 | writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); |
644 | writel(CLK_DIV_ISP1_VAL, &clk->div_isp1); | 644 | writel(CLK_DIV_ISP1_VAL, &clk->div_isp1); |
645 | writel(CLK_DIV_ISP2_VAL, &clk->div_isp2); | 645 | writel(CLK_DIV_ISP2_VAL, &clk->div_isp2); |
646 | 646 | ||
647 | /* FIMD1 SRC CLK SELECTION */ | 647 | /* FIMD1 SRC CLK SELECTION */ |
648 | writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp1_0); | 648 | writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp1_0); |
649 | 649 | ||
650 | val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET | 650 | val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET |
651 | | MMC2_RATIO_VAL << MMC2_RATIO_OFFSET | 651 | | MMC2_RATIO_VAL << MMC2_RATIO_OFFSET |
652 | | MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET | 652 | | MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET |
653 | | MMC3_RATIO_VAL << MMC3_RATIO_OFFSET; | 653 | | MMC3_RATIO_VAL << MMC3_RATIO_OFFSET; |
654 | writel(val, &clk->div_fsys2); | 654 | writel(val, &clk->div_fsys2); |
655 | } | 655 | } |
656 | 656 | ||
657 | void clock_init_dp_clock(void) | 657 | void clock_init_dp_clock(void) |
658 | { | 658 | { |
659 | struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; | 659 | struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; |
660 | 660 | ||
661 | /* DP clock enable */ | 661 | /* DP clock enable */ |
662 | setbits_le32(&clk->gate_ip_disp1, CLK_GATE_DP1_ALLOW); | 662 | setbits_le32(&clk->gate_ip_disp1, CLK_GATE_DP1_ALLOW); |
663 | 663 | ||
664 | /* We run DP at 267 Mhz */ | 664 | /* We run DP at 267 Mhz */ |
665 | setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); | 665 | setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); |
666 | } | 666 | } |
667 | 667 |