Exynos: clock: Fix a bug in PLL lock check condition

The condition for testing of PLL getting locked was incorrect. Rectify this error in this patch. Reported-by: Alexei Fedorov <alexie.fedorov@arm.com> Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

Exynos: clock: Fix a bug in PLL lock check condition
The condition for testing of PLL getting locked was incorrect. Rectify this error in this patch. Reported-by: Alexei Fedorov <alexie.fedorov@arm.com> Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Akshay Saraswat · Minkyu Kang
1 parent dc993a65f4
Showing 1 changed file with 7 additions and 7 deletions Side-by-side Diff
board/samsung/smdk5250/clock_init.c
@@ -494,35 +494,35 @@
 	val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
 			arm_clk_ratio->apll_sdiv);
 	writel(val, &clk->apll_con0);
-	while (readl(&clk->apll_con0) & APLL_CON0_LOCKED)
+	while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0)
 		;
  
 	/* Set MPLL */
 	writel(MPLL_CON1_VAL, &clk->mpll_con1);
 	val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
 	writel(val, &clk->mpll_con0);
-	while (readl(&clk->mpll_con0) & MPLL_CON0_LOCKED)
+	while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0)
 		;
  
 	/* Set BPLL */
 	writel(BPLL_CON1_VAL, &clk->bpll_con1);
 	val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
 	writel(val, &clk->bpll_con0);
-	while (readl(&clk->bpll_con0) & BPLL_CON0_LOCKED)
+	while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0)
 		;
  
 	/* Set CPLL */
 	writel(CPLL_CON1_VAL, &clk->cpll_con1);
 	val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
 	writel(val, &clk->cpll_con0);
-	while (readl(&clk->cpll_con0) & CPLL_CON0_LOCKED)
+	while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0)
 		;
  
 	/* Set GPLL */
 	writel(GPLL_CON1_VAL, &clk->gpll_con1);
 	val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
 	writel(val, &clk->gpll_con0);
-	while (readl(&clk->gpll_con0) & GPLL_CON0_LOCKED)
+	while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0)
 		;
  
 	/* Set EPLL */
@@ -530,7 +530,7 @@
 	writel(EPLL_CON1_VAL, &clk->epll_con1);
 	val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
 	writel(val, &clk->epll_con0);
-	while (readl(&clk->epll_con0) & EPLL_CON0_LOCKED)
+	while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0)
 		;
  
 	/* Set VPLL */
@@ -538,7 +538,7 @@
 	writel(VPLL_CON1_VAL, &clk->vpll_con1);
 	val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
 	writel(val, &clk->vpll_con0);
-	while (readl(&clk->vpll_con0) & VPLL_CON0_LOCKED)
+	while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0)
 		;
  
 	writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
...	...	@@ -494,35 +494,35 @@
494	494	val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
495	495	arm_clk_ratio->apll_sdiv);
496	496	writel(val, &clk->apll_con0);
497		- while (readl(&clk->apll_con0) & APLL_CON0_LOCKED)
	497	+ while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0)
498	498	;
499	499
500	500	/* Set MPLL */
501	501	writel(MPLL_CON1_VAL, &clk->mpll_con1);
502	502	val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
503	503	writel(val, &clk->mpll_con0);
504		- while (readl(&clk->mpll_con0) & MPLL_CON0_LOCKED)
	504	+ while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0)
505	505	;
506	506
507	507	/* Set BPLL */
508	508	writel(BPLL_CON1_VAL, &clk->bpll_con1);
509	509	val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
510	510	writel(val, &clk->bpll_con0);
511		- while (readl(&clk->bpll_con0) & BPLL_CON0_LOCKED)
	511	+ while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0)
512	512	;
513	513
514	514	/* Set CPLL */
515	515	writel(CPLL_CON1_VAL, &clk->cpll_con1);
516	516	val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
517	517	writel(val, &clk->cpll_con0);
518		- while (readl(&clk->cpll_con0) & CPLL_CON0_LOCKED)
	518	+ while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0)
519	519	;
520	520
521	521	/* Set GPLL */
522	522	writel(GPLL_CON1_VAL, &clk->gpll_con1);
523	523	val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
524	524	writel(val, &clk->gpll_con0);
525		- while (readl(&clk->gpll_con0) & GPLL_CON0_LOCKED)
	525	+ while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0)
526	526	;
527	527
528	528	/* Set EPLL */
...	...	@@ -530,7 +530,7 @@
530	530	writel(EPLL_CON1_VAL, &clk->epll_con1);
531	531	val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
532	532	writel(val, &clk->epll_con0);
533		- while (readl(&clk->epll_con0) & EPLL_CON0_LOCKED)
	533	+ while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0)
534	534	;
535	535
536	536	/* Set VPLL */
...	...	@@ -538,7 +538,7 @@
538	538	writel(VPLL_CON1_VAL, &clk->vpll_con1);
539	539	val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
540	540	writel(val, &clk->vpll_con0);
541		- while (readl(&clk->vpll_con0) & VPLL_CON0_LOCKED)
	541	+ while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0)
542	542	;
543	543
544	544	writel(CLK_SRC_CORE0_VAL, &clk->src_core0);