Eric Lee / smarc-uboot

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Commit dbbdc81c6064b4cb7ffc796b71713a19488a2c4c

Authored by Jagan Teki
1 parent cb56caacf8
Exists in smarc_8mq_lf_v2020.04 and in 9 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

spi: rk: Limit transfers to (64K - 1) bytes 

The Rockchip SPI controller's length register only supports 16-bits,
yielding a maximum length of 64KiB (the CTRLR1 register holds "length -
1"). Trying to transfer more than that (e.g., with a large SPI flash
read) will cause the driver to hang.

Now, it seems that while theoretically we should be able to program
CTRLR1 with 0xffff, and get a 64KiB transfer, but that also seems to
cause the core to choke, so stick with a maximum of 64K - 1 bytes --
i.e., 0xffff.

Note, that the size is further divided into 'minus 1' while writing
into CTRLR1.

This change fixed two different read issues,

1. sf read failure when with > 0x10000

2. Boot from SPI flash failed during spi_flash_read call in
   common/spl/spl_spi.c

Observed and Tested in
- Rockpro64 with Gigadevice flash
- ROC-RK3399-PC with Winbond flash

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Showing 1 changed file with 8 additions and 2 deletions Side-by-side Diff

drivers/spi/rk_spi.c
Diff comments   View file @ dbbdc81
... ... @@ -27,6 +27,12 @@
27 27 /* Change to 1 to output registers at the start of each transaction */
28 28 #define DEBUG_RK_SPI 0
29 29  
  30 +/*
  31 + * ctrlr1 is 16-bits, so we should support lengths of 0xffff + 1. However,
  32 + * the controller seems to hang when given 0x10000, so stick with this for now.
  33 + */
  34 +#define ROCKCHIP_SPI_MAX_TRANLEN 0xffff
  35 +
30 36 struct rockchip_spi_params {
31 37 /* RXFIFO overruns and TXFIFO underruns stop the master clock */
32 38 bool master_manages_fifo;
... ... @@ -367,7 +373,7 @@
367 373 * represented in CTRLR1.
368 374 */
369 375 if (data && data->master_manages_fifo)
370   - max_chunk_size = 0x10000;
  376 + max_chunk_size = ROCKCHIP_SPI_MAX_TRANLEN;
371 377  
372 378 // rockchip_spi_configure(dev, mode, size)
373 379 rkspi_enable_chip(regs, false);
... ... @@ -451,7 +457,7 @@
451 457  
452 458 /* This is the original 8bit reader/writer code */
453 459 while (len > 0) {
454   - int todo = min(len, 0x10000);
  460 + int todo = min(len, ROCKCHIP_SPI_MAX_TRANLEN);
455 461  
456 462 rkspi_enable_chip(regs, false);
457 463 writel(todo - 1, &regs->ctrlr1);