Eric Lee / smarc-uboot

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Commit dd8a14dd46f8b508cfc879100942bcb05a6d6c1c

Authored by Peng Fan
1 parent 88a3952de9
Exists in smarc_8mq-imx_v2020.04_5.4.24_2.1.0 and in 1 other branch smarc_8mm-imx_v2020.04_5.4.24_2.1.0

MLK-24188-1 imx8: add AHB clk for SDHC 

Add AHB clk for SDHC, without AHB clock, sdhc cmd will not finish.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 3ea6b86eecbfd5a1e082b86c99e411af1310afa1)

Showing 7 changed files with 26 additions and 11 deletions Side-by-side Diff

arch/arm/dts/fsl-imx8dx.dtsi
Diff comments   View file @ dd8a14d
... ... @@ -3149,7 +3149,7 @@
3149 3149 reg = <0x0 0x5b010000 0x0 0x10000>;
3150 3150 clocks = <&clk IMX8QXP_SDHC0_IPG_CLK>,
3151 3151 <&clk IMX8QXP_SDHC0_CLK>,
3152   - <&clk IMX8QXP_CLK_DUMMY>;
  3152 + <&clk IMX8QXP_SDHC0_AHB_CLK>;
3153 3153 clock-names = "ipg", "per", "ahb";
3154 3154 assigned-clocks = <&clk IMX8QXP_SDHC0_SEL>, <&clk IMX8QXP_SDHC0_DIV>;
3155 3155 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>;
... ... @@ -3167,7 +3167,7 @@
3167 3167 reg = <0x0 0x5b020000 0x0 0x10000>;
3168 3168 clocks = <&clk IMX8QXP_SDHC1_IPG_CLK>,
3169 3169 <&clk IMX8QXP_SDHC1_CLK>,
3170   - <&clk IMX8QXP_CLK_DUMMY>;
  3170 + <&clk IMX8QXP_SDHC1_AHB_CLK>;
3171 3171 clock-names = "ipg", "per", "ahb";
3172 3172 assigned-clocks = <&clk IMX8QXP_SDHC1_SEL>, <&clk IMX8QXP_SDHC1_DIV>;
3173 3173 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>;
... ... @@ -3185,7 +3185,7 @@
3185 3185 reg = <0x0 0x5b030000 0x0 0x10000>;
3186 3186 clocks = <&clk IMX8QXP_SDHC2_IPG_CLK>,
3187 3187 <&clk IMX8QXP_SDHC2_CLK>,
3188   - <&clk IMX8QXP_CLK_DUMMY>;
  3188 + <&clk IMX8QXP_SDHC2_AHB_CLK>;
3189 3189 clock-names = "ipg", "per", "ahb";
3190 3190 assigned-clocks = <&clk IMX8QXP_SDHC2_SEL>, <&clk IMX8QXP_SDHC2_DIV>;
3191 3191 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>;
arch/arm/dts/fsl-imx8dxl.dtsi
Diff comments   View file @ dd8a14d
... ... @@ -1619,7 +1619,7 @@
1619 1619 reg = <0x0 0x5b010000 0x0 0x10000>;
1620 1620 clocks = <&clk IMX8QXP_SDHC0_IPG_CLK>,
1621 1621 <&clk IMX8QXP_SDHC0_CLK>,
1622   - <&clk IMX8QXP_CLK_DUMMY>;
  1622 + <&clk IMX8QXP_SDHC0_AHB_CLK>;
1623 1623 clock-names = "ipg", "per", "ahb";
1624 1624 assigned-clocks = <&clk IMX8QXP_SDHC0_SEL>, <&clk IMX8QXP_SDHC0_DIV>;
1625 1625 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>;
... ... @@ -1637,7 +1637,7 @@
1637 1637 reg = <0x0 0x5b020000 0x0 0x10000>;
1638 1638 clocks = <&clk IMX8QXP_SDHC1_IPG_CLK>,
1639 1639 <&clk IMX8QXP_SDHC1_CLK>,
1640   - <&clk IMX8QXP_CLK_DUMMY>;
  1640 + <&clk IMX8QXP_SDHC1_AHB_CLK>;
1641 1641 clock-names = "ipg", "per", "ahb";
1642 1642 assigned-clocks = <&clk IMX8QXP_SDHC1_SEL>, <&clk IMX8QXP_SDHC1_DIV>;
1643 1643 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>;
... ... @@ -1655,7 +1655,7 @@
1655 1655 reg = <0x0 0x5b030000 0x0 0x10000>;
1656 1656 clocks = <&clk IMX8QXP_SDHC2_IPG_CLK>,
1657 1657 <&clk IMX8QXP_SDHC2_CLK>,
1658   - <&clk IMX8QXP_CLK_DUMMY>;
  1658 + <&clk IMX8QXP_SDHC2_AHB_CLK>;
1659 1659 clock-names = "ipg", "per", "ahb";
1660 1660 assigned-clocks = <&clk IMX8QXP_SDHC2_SEL>, <&clk IMX8QXP_SDHC2_DIV>;
1661 1661 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>;
arch/arm/dts/fsl-imx8qm-device.dtsi
Diff comments   View file @ dd8a14d
... ... @@ -1928,7 +1928,7 @@
1928 1928 reg = <0x0 0x5b010000 0x0 0x10000>;
1929 1929 clocks = <&clk IMX8QM_SDHC0_IPG_CLK>,
1930 1930 <&clk IMX8QM_SDHC0_CLK>,
1931   - <&clk IMX8QM_CLK_DUMMY>;
  1931 + <&clk IMX8QM_SDHC0_AHB_CLK>;
1932 1932 clock-names = "ipg", "per", "ahb";
1933 1933 assigned-clocks = <&clk IMX8QM_SDHC0_DIV>;
1934 1934 assigned-clock-rates = <400000000>;
... ... @@ -1946,7 +1946,7 @@
1946 1946 reg = <0x0 0x5b020000 0x0 0x10000>;
1947 1947 clocks = <&clk IMX8QM_SDHC1_IPG_CLK>,
1948 1948 <&clk IMX8QM_SDHC1_CLK>,
1949   - <&clk IMX8QM_CLK_DUMMY>;
  1949 + <&clk IMX8QM_SDHC1_AHB_CLK>;
1950 1950 clock-names = "ipg", "per", "ahb";
1951 1951 assigned-clocks = <&clk IMX8QM_SDHC1_DIV>;
1952 1952 assigned-clock-rates = <200000000>;
... ... @@ -1964,7 +1964,7 @@
1964 1964 reg = <0x0 0x5b030000 0x0 0x10000>;
1965 1965 clocks = <&clk IMX8QM_SDHC2_IPG_CLK>,
1966 1966 <&clk IMX8QM_SDHC2_CLK>,
1967   - <&clk IMX8QM_CLK_DUMMY>;
  1967 + <&clk IMX8QM_SDHC2_AHB_CLK>;
1968 1968 clock-names = "ipg", "per", "ahb";
1969 1969 assigned-clocks = <&clk IMX8QM_SDHC2_DIV>;
1970 1970 assigned-clock-rates = <200000000>;
drivers/clk/imx/clk-imx8qm.c
Diff comments   View file @ dd8a14d
... ... @@ -142,10 +142,13 @@
142 142  
143 143 CLK_5( IMX8QM_SDHC0_CLK, "SDHC0_CLK", 0, USDHC_0_LPCG, IMX8QM_SDHC0_DIV ),
144 144 CLK_5( IMX8QM_SDHC0_IPG_CLK, "SDHC0_IPG", 16, USDHC_0_LPCG, IMX8QM_IPG_CONN_CLK_ROOT ),
  145 + CLK_5( IMX8QM_SDHC0_AHB_CLK, "SDHC0_AHB", 20, USDHC_0_LPCG, IMX8QM_AHB_CONN_CLK_ROOT ),
145 146 CLK_5( IMX8QM_SDHC1_CLK, "SDHC1_CLK", 0, USDHC_1_LPCG, IMX8QM_SDHC1_DIV ),
146 147 CLK_5( IMX8QM_SDHC1_IPG_CLK, "SDHC1_IPG", 16, USDHC_1_LPCG, IMX8QM_IPG_CONN_CLK_ROOT ),
  148 + CLK_5( IMX8QM_SDHC1_AHB_CLK, "SDHC1_AHB", 20, USDHC_1_LPCG, IMX8QM_AHB_CONN_CLK_ROOT ),
147 149 CLK_5( IMX8QM_SDHC2_CLK, "SDHC2_CLK", 0, USDHC_2_LPCG, IMX8QM_SDHC2_DIV ),
148 150 CLK_5( IMX8QM_SDHC2_IPG_CLK, "SDHC2_IPG", 16, USDHC_2_LPCG, IMX8QM_IPG_CONN_CLK_ROOT ),
  151 + CLK_5( IMX8QM_SDHC2_AHB_CLK, "SDHC2_AHB", 20, USDHC_2_LPCG, IMX8QM_AHB_CONN_CLK_ROOT ),
149 152  
150 153 CLK_5( IMX8QM_ENET0_IPG_S_CLK, "ENET0_IPG_S", 20, ENET_0_LPCG, IMX8QM_IPG_CONN_CLK_ROOT ),
151 154 CLK_5( IMX8QM_ENET0_IPG_CLK, "ENET0_IPG", 16, ENET_0_LPCG, IMX8QM_ENET0_IPG_S_CLK ),
drivers/clk/imx/clk-imx8qxp.c
Diff comments   View file @ dd8a14d
... ... @@ -108,10 +108,13 @@
108 108  
109 109 CLK_5( IMX8QXP_SDHC0_CLK, "SDHC0_CLK", 0, USDHC_0_LPCG, IMX8QXP_SDHC0_DIV ),
110 110 CLK_5( IMX8QXP_SDHC0_IPG_CLK, "SDHC0_IPG", 16, USDHC_0_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ),
  111 + CLK_5( IMX8QXP_SDHC0_AHB_CLK, "SDHC0_AHB", 20, USDHC_0_LPCG, IMX8QXP_AHB_CONN_CLK_ROOT ),
111 112 CLK_5( IMX8QXP_SDHC1_CLK, "SDHC1_CLK", 0, USDHC_1_LPCG, IMX8QXP_SDHC1_DIV ),
112 113 CLK_5( IMX8QXP_SDHC1_IPG_CLK, "SDHC1_IPG", 16, USDHC_1_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ),
  114 + CLK_5( IMX8QXP_SDHC1_AHB_CLK, "SDHC1_AHB", 20, USDHC_1_LPCG, IMX8QXP_AHB_CONN_CLK_ROOT ),
113 115 CLK_5( IMX8QXP_SDHC2_CLK, "SDHC2_CLK", 0, USDHC_2_LPCG, IMX8QXP_SDHC2_DIV ),
114 116 CLK_5( IMX8QXP_SDHC2_IPG_CLK, "SDHC2_IPG", 16, USDHC_2_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ),
  117 + CLK_5( IMX8QXP_SDHC2_AHB_CLK, "SDHC2_AHB", 20, USDHC_2_LPCG, IMX8QXP_AHB_CONN_CLK_ROOT ),
115 118  
116 119 CLK_5( IMX8QXP_ENET0_IPG_S_CLK, "ENET0_IPG_S", 20, ENET_0_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ),
117 120 CLK_5( IMX8QXP_ENET0_IPG_CLK, "ENET0_IPG", 16, ENET_0_LPCG, IMX8QXP_ENET0_IPG_S_CLK ),
include/dt-bindings/clock/imx8qm-clock.h
Diff comments   View file @ dd8a14d
... ... @@ -847,7 +847,11 @@
847 847 #define IMX8QM_MIPI1_DSI_PHY_DIV 798
848 848 #define IMX8QM_MIPI1_DSI_PHY_CLK 799
849 849  
850   -#define IMX8QM_CLK_END 800
  850 +#define IMX8QM_SDHC0_AHB_CLK 800
  851 +#define IMX8QM_SDHC1_AHB_CLK 801
  852 +#define IMX8QM_SDHC2_AHB_CLK 802
  853 +
  854 +#define IMX8QM_CLK_END 813
851 855  
852 856 #endif /* __DT_BINDINGS_CLOCK_IMX8QM_H */
include/dt-bindings/clock/imx8qxp-clock.h
Diff comments   View file @ dd8a14d
... ... @@ -591,6 +591,11 @@
591 591 #define IMX8DXL_EQOS_PTP_CLK 542
592 592  
593 593 #define IMX8DXL_USB2_PHY2_IPG_CLK 543
594   -#define IMX8DXL_CLK_END 544
  594 +
  595 +#define IMX8QXP_SDHC0_AHB_CLK 544
  596 +#define IMX8QXP_SDHC1_AHB_CLK 545
  597 +#define IMX8QXP_SDHC2_AHB_CLK 546
  598 +
  599 +#define IMX8DXL_CLK_END 547
595 600 #endif /* __DT_BINDINGS_CLOCK_IMX8QXP_H */